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authorMichal Simek <monstr@monstr.eu>2010-04-26 13:43:23 +0200
committerMichal Simek <monstr@monstr.eu>2010-05-06 11:21:59 +0200
commit598acab44dcbda0e300d9d080e81566334138e7d (patch)
tree19f8a929ce264068a21b25b91258afe4bad64b75
parent77543cebab7387eab7d482e90018a64d6f2ced1e (diff)
downloadconfigs-598acab44dcbda0e300d9d080e81566334138e7d.tar.gz
microblaze: Define correct L1_CACHE_SHIFT value
Microblaze cacheline length is configurable and current cpu uses two cacheline length 4 and 8. We are taking conservative maximum value to be sure that cacheline alignment is satisfied for all cases. Here is the calculation for cacheline lenght 8 32bit=4Byte values which is corresponding with SHIFT 5. Signed-off-by: Michal Simek <monstr@monstr.eu>
-rw-r--r--arch/microblaze/include/asm/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index e52210891d7..4efe96a036f 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -15,7 +15,7 @@
#include <asm/registers.h>
-#define L1_CACHE_SHIFT 2
+#define L1_CACHE_SHIFT 5
/* word-granular cache in microblaze */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)