From fcdca1fe734d6d58771636873c1b292e6de13383 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Fri, 15 Feb 2013 16:15:10 +0000 Subject: ARM: perf: [WIP] Skip PMU register save/restore when no active counters This patch checks whether any counters are active in the PMU's per- CPU event_mask before attempting save/restore. In practice, this means that the save/restore is skipped if there is no active perf session. If there are no active counters, nothing is saved or restored. The PMU is still reset and quiesced on the restore path, as previously. Signed-off-by: Dave Martin --- arch/arm/kernel/perf_event_v7.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 24e195a00af..7e38f1fa712 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1117,6 +1117,9 @@ static void armv7pmu_save_regs(struct arm_pmu *pmu, if (!cpupmu->active) return; + if (!*cpupmu->cpu_hw_events.used_mask) + return; + if (!__v7_pmu_save_reg(cpupmu, PMCR) & ARMV7_PMNC_E) return; @@ -1148,6 +1151,9 @@ static void armv7pmu_restore_regs(struct arm_pmu *pmu, if (!cpupmu->active) return; + if (!*cpupmu->cpu_hw_events.used_mask) + return; + pmcr = __v7_pmu_read_logical(cpupmu, PMCR); if (!pmcr & ARMV7_PMNC_E) return; -- cgit v1.2.3