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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä
2013-01-24drm/i915: DSPFW registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä
2013-01-24drm/i915: Cursor registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Pipe registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Primary plane registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä
2013-01-24drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä
2013-01-24drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä
2013-01-23drm/i915: Disable AsyncFlip performance optimisationsChris Wilson
2013-01-20drm/i915: Fix RGB color range property for PCH platformsVille Syrjälä
2013-01-17drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLVVille Syrjälä
2013-01-17Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet...Dave Airlie
2013-01-15drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-stateChris Wilson
2012-12-17drm/i915: Implement WaSetupGtModeTdRowDispatchDaniel Vetter
2012-12-17drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabledDaniel Vetter
2012-12-17drm/i915: clean up PIPECONF bpc #definesDaniel Vetter
2012-12-14drm/i915: Cleanup SHOTPLUG_CTL status bits definitionsDamien Lespiau
2012-12-10drm/i915: set the LPT FDI RX polarity reversal bit when neededPaulo Zanoni
2012-12-10drm/i915: add lpt_init_pch_refclkPaulo Zanoni
2012-12-10drm/i915: add support for mPHY destination on intel_sbi_{read, write}Paulo Zanoni
2012-12-06drm/i915: Remove duplicate and unused register #defines in i915_reg.hDexuan Cui
2012-11-29drm/i915: remove duplicate register #definesDaniel Vetter
2012-11-21drm/i915: make the panel fitter work on pipes B and C on IVBPaulo Zanoni
2012-11-21drm/i915: don't intel_crt_init if DDI A has 4 lanesPaulo Zanoni
2012-11-21drm/i915: make DP work on LPT-LP machinesPaulo Zanoni
2012-11-11drm/i915: Move the remaining gtt codeBen Widawsky
2012-11-11drm/i915: flush system agent TLBs on SNBBen Widawsky
2012-11-11drm/i915: Calculate correct stolen size for GEN7+Ben Widawsky
2012-11-11drm/i915: Stop using AGP layer for GEN6+Ben Widawsky
2012-11-11drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3Jesse Barnes
2012-11-11drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLVJesse Barnes
2012-11-11drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLVJesse Barnes
2012-11-11drm/i915: implement WaDisableDopClockGatingisable on VLV and IVBJesse Barnes
2012-11-11drm/i915: implement WaDisableL3CacheAging on VLVJesse Barnes
2012-11-11drm/i915: fix Haswell FDI link training codePaulo Zanoni
2012-11-11drm/i915: implement WADP0ClockGatingDisableDaniel Vetter
2012-11-11drm/i915: CPT+ pch transcoder workaroundDaniel Vetter
2012-11-11drm/i915: Add SURFLIVE register definitionsVille Syrjälä
2012-11-11drm/i915: Fix display pixel format handlingVille Syrjälä
2012-11-11drm/i915: implement WaDisableRenderCachePipelinedFlushDaniel Vetter
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