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-rw-r--r--arch/arm/mach-u300/include/mach/dma_channels.h11
-rw-r--r--arch/arm/mach-u300/include/mach/irqs.h34
-rw-r--r--arch/arm/mach-u300/include/mach/syscon.h32
-rw-r--r--arch/arm/mach-u300/include/mach/u300-regs.h19
4 files changed, 8 insertions, 88 deletions
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
index b239149ba0d..4e8a88fbca4 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/dma_channels.h
*
*
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
* Map file for the U300 dma driver.
* Author: Per Friden <per.friden@stericsson.com>
@@ -50,19 +50,10 @@
#define U300_DMA_GENERAL_PURPOSE_6 35
#define U300_DMA_GENERAL_PURPOSE_7 36
#define U300_DMA_GENERAL_PURPOSE_8 37
-#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_UART1_TX 38
#define U300_DMA_UART1_RX 39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9 38
-#define U300_DMA_GENERAL_PURPOSE_10 39
-#endif
-#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_DEVICE_CHANNELS 32
-#else
-#define U300_DMA_DEVICE_CHANNELS 30
-#endif
#define U300_DMA_CHANNELS 40
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e07b1..c09386bca20 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/irqs.h
*
*
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* IRQ channel definitions for the U300 platforms.
* Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,10 +31,6 @@
#define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC 17
-#endif
#define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 20
@@ -55,8 +51,6 @@
#define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 35
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
- defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 37
@@ -68,15 +62,8 @@
#define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 45
-#endif
-
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END 46
-#endif
/* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 48
@@ -89,25 +76,6 @@
#define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 57
-#endif
-
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3 36
-#define IRQ_U300_GPIO_PORT4 37
-#define IRQ_U300_WDOG 38
-#define IRQ_U300_EVHIST 39
-#define IRQ_U300_MSPRO 40
-#define IRQ_U300_MMCSD_MCIINTR0 41
-#define IRQ_U300_MMCSD_MCIINTR1 42
-#define IRQ_U300_I2C0 43
-#define IRQ_U300_I2C1 44
-#define IRQ_U300_RTC 45
-#define IRQ_U300_NFIF 46
-#define IRQ_U300_NFIF2 47
-#define IRQ_U300_SYSCON_PLL_LOCK 48
-#define U300_VIC_IRQS_END 49
-#endif
/* Maximum 8*7 GPIO lines */
#ifdef CONFIG_PINCTRL_COH901
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07a7c6..10bdd0be977 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/syscon.h
*
*
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
*
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
@@ -36,9 +36,7 @@
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
-#endif
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
@@ -50,9 +48,7 @@
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
-#endif
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
@@ -62,10 +58,8 @@
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
-#endif
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
@@ -79,9 +73,7 @@
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
-#endif
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
@@ -92,24 +84,20 @@
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
-#endif
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
-#endif
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
@@ -124,9 +112,7 @@
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
-#endif
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
@@ -135,9 +121,7 @@
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
-#endif
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
@@ -147,10 +131,8 @@
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
-#endif
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
@@ -168,9 +150,7 @@
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
-#endif
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
@@ -184,10 +164,8 @@
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
-#endif
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c52389..1e49d901f2c 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
-
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
@@ -46,11 +45,7 @@
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE 0x30000000
-#endif
/*
* AHB peripherals
@@ -99,10 +94,8 @@
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
-#ifdef CONFIG_MACH_U300_BS335
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
/*
* SLOW peripherals
@@ -151,10 +144,8 @@
* REST peripherals
*/
-/* ISP (image signal processor) is only available in U335 */
-#ifdef CONFIG_MACH_U300_BS335
+/* ISP (image signal processor) */
#define U300_ISP_BASE (0xA0008000)
-#endif
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
@@ -166,17 +157,9 @@
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
#define U300_VIDEOENC_BASE (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE (0xc0040000)
-#endif
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
-/*
- * Virtual accessor macros for static devices
- */
-
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 18:00:18 +0000