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authorCatalin Marinas <catalin.marinas@arm.com>2012-02-23 17:16:41 +0000
committerJon Medhurst <tixy@linaro.org>2013-07-01 11:04:35 +0100
commit85705038621c022cffc4e36b3b60720d5dd421ec (patch)
tree2dc28017136b59cc14fa61e6a2b66bd111e3309d /drivers
parent8bb495e3f02401ee6f76d1b1d77f3ac9f079e376 (diff)
ARM: LPAE: Invalidate the TLB for module addresses during translation fault
During the free_pgtables() call all user and modules/pkmap entries are removed. If a translation fault for the modules/pkmap area occurs before we switched away from the current pgd, do_translation_fault() would copy the init_mm pud into the user pud. There is a small window between pud_clear() and pmd_free_tlb() in free_pmd_range() where the pud entry was cleared but the TLB has not been invalidated yet and the CPU may have cached the original (valid) pud entry in the TLB. A scenario like below would get stuck in continuous prefetch abort: 1. Current process exiting. The modules pmd entries not populated 2. exit_mmap() -> ... -> pmd_free_tlb() 3. pud_clear() for the 1GB pud containing user stack and modules (no TLB invalidation yet) 4. Interrupt -> module interrupt routine 5. Level 2 (pmd) translation fault occurs when executing the module interrupt routine. The CPU previously cached (TLB) the old valid pud value for the modules area, so we don't get a level 1 translation fault 6. do_translation fault() copies the pud_k into the pud 7. Linux returns to the faulty instruction. Goes back to 5 At point 7, since the CPU still has the old pud value, it goes back to point 5 and never gets out of this loop. With this patch, the stale pud TLB entry is invalidated after point 6 and the subsequent prefetch abort doesn't occur. Reported-by: Tony Thompson <Anthony.Thompson@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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