diff options
| author | Daniel Cotey <puff65537@bansheeslibrary.com> | 2012-09-15 06:05:51 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-09-17 05:37:56 -0700 |
| commit | 97ef0a461ba82cb641ae53314997ce44161b749a (patch) | |
| tree | d435f8d94a985c8d96d97e2098d31a261352c1a7 /drivers/staging/silicom/bp_mod.h | |
| parent | fab85699f34293f3914f561ff6e50a2f69717cab (diff) | |
Staging: silicom: bp_mod.h: checkpatch tab and space cleanup
tenth chunk of bp_mod.h's cleanup
Signed-off-by: Daniel Cotey <puff65537@bansheeslibrary.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/silicom/bp_mod.h')
| -rw-r--r-- | drivers/staging/silicom/bp_mod.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/staging/silicom/bp_mod.h b/drivers/staging/silicom/bp_mod.h index 3a97b2d483e..2862c5790c2 100644 --- a/drivers/staging/silicom/bp_mod.h +++ b/drivers/staging/silicom/bp_mod.h @@ -445,22 +445,22 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j) (pid == SILICOM_PE2G4BPFi35ZX_SSID)) #define PEGF80_IF_SERIES(pid) \ -((pid==SILICOM_PE2G4BPFi80_SSID)|| \ -(pid==SILICOM_PE2G4BPFi80LX_SSID)|| \ -(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \ -(pid==SILICOM_PE2G4BPFi80ZX_SSID)|| \ -(pid==SILICOM_M1E2G4BPFi80_SSID)|| \ -(pid==SILICOM_M1E2G4BPFi80LX_SSID)|| \ -(pid==SILICOM_M1E2G4BPFi80ZX_SSID)|| \ -(pid==SILICOM_PE2G2BPFi80_SSID)|| \ -(pid==SILICOM_PE2G2BPFi80LX_SSID)|| \ -(pid==SILICOM_PE2G2BPFi80ZX_SSID)|| \ -(pid==SILICOM_PE2G2BPFi35_SSID)|| \ -(pid==SILICOM_PE2G2BPFi35LX_SSID)|| \ -(pid==SILICOM_PE2G2BPFi35ZX_SSID)|| \ -(pid==SILICOM_PE2G4BPFi35_SSID)|| \ -(pid==SILICOM_PE2G4BPFi35LX_SSID)|| \ -(pid==SILICOM_PE2G4BPFi35ZX_SSID)) + ((pid == SILICOM_PE2G4BPFi80_SSID) || \ + (pid == SILICOM_PE2G4BPFi80LX_SSID) || \ + (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \ + (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \ + (pid == SILICOM_M1E2G4BPFi80_SSID) || \ + (pid == SILICOM_M1E2G4BPFi80LX_SSID) || \ + (pid == SILICOM_M1E2G4BPFi80ZX_SSID) || \ + (pid == SILICOM_PE2G2BPFi80_SSID) || \ + (pid == SILICOM_PE2G2BPFi80LX_SSID) || \ + (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \ + (pid == SILICOM_PE2G2BPFi35_SSID) || \ + (pid == SILICOM_PE2G2BPFi35LX_SSID) || \ + (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \ + (pid == SILICOM_PE2G4BPFi35_SSID) || \ + (pid == SILICOM_PE2G4BPFi35LX_SSID) || \ + (pid == SILICOM_PE2G4BPFi35ZX_SSID)) #define BP10G9_IF_SERIES(pid) \ ((pid==INTEL_PE210G2SPI9_SSID)|| \ |