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authorAlex Deucher <alexander.deucher@amd.com>2012-06-14 22:06:36 +0200
committerDave Airlie <airlied@redhat.com>2012-06-16 14:30:47 +0100
commitb866d1334ba2d544bc575d75357dea6bdcdc7f46 (patch)
tree3441b51902258315ae4a9d0fe100996ddb49b901 /drivers/gpu/drm/radeon/r600.c
parent6b53a0507b6e728c53f2fc60912a8511f151e5d8 (diff)
drm/radeon: add some additional 6xx/7xx/EG register init
- SMX_SAR_CTL0 needs to be programmed correctly to prevent problems with memory exports in certain cases. - VC_ENHANCE needs to be initialized on 6xx/7xx. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f30dc95f83b..bff62729381 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
NUM_CLIP_SEQ(3)));
WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+ WREG32(VC_ENHANCE, 0);
}