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authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>2013-02-13 22:20:22 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-02-20 00:21:46 +0100
commit4f7dfb6788dd022446847fbbfbe45e13bedb5be2 (patch)
tree822ff1448493a7bf474805dc210ed74b50ddb7d3 /drivers/gpu/drm/i915/intel_ringbuffer.c
parent53a7d2d15ef45fb892defaf624ad6db7d528d8ac (diff)
drm/i915: Set i9xx sdvo clock limits according to specifications
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359 Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions