diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-27 00:44:57 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-28 01:09:29 +0100 |
| commit | 965e0c489f360df1beeb567e4540777a09b8896e (patch) | |
| tree | 89710f6280e7b83c7434ddf74634602f2c86be4f /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 50f3b016b055dbc83094bc2d7a91c3c69edbc88b (diff) | |
drm/i915: introduce pipe_config->dither|pipe_bpp
We want to compute this earlier. To avoid a big complicated patch,
this patch here just does the big search&replace and still calls the
old functions at the same places.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index baeb4700e5e..3d09df0d4b9 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -931,7 +931,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { temp = TRANS_MSA_SYNC_CLK; - switch (intel_crtc->bpp) { + switch (intel_crtc->config.pipe_bpp) { case 18: temp |= TRANS_MSA_6_BPC; break; @@ -947,7 +947,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) default: temp |= TRANS_MSA_8_BPC; WARN(1, "%d bpp unsupported by DDI function\n", - intel_crtc->bpp); + intel_crtc->config.pipe_bpp); } I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); } @@ -969,7 +969,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) temp = TRANS_DDI_FUNC_ENABLE; temp |= TRANS_DDI_SELECT_PORT(port); - switch (intel_crtc->bpp) { + switch (intel_crtc->config.pipe_bpp) { case 18: temp |= TRANS_DDI_BPC_6; break; @@ -984,7 +984,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) break; default: WARN(1, "%d bpp unsupported by transcoder DDI function\n", - intel_crtc->bpp); + intel_crtc->config.pipe_bpp); } if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |