diff options
| author | Borislav Petkov <borislav.petkov@amd.com> | 2010-12-22 14:28:24 +0100 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-03-17 14:46:14 +0100 |
| commit | cb32850744b8b574966637ae98d55692717eced4 (patch) | |
| tree | 3052886f38108f72a5d6c60be43af68198ef2ac5 /drivers/edac/amd64_edac.h | |
| parent | 525a1b20a6830317db17b62df322b45d92ecd550 (diff) | |
amd64_edac: Cleanup Dram Configuration registers handling
* Restrict DCT ganged mode check since only Fam10h supports it
* Adjust DRAM type detection for BD since it only supports DDR3
* Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do
that in read_mc_regs()
* Cleanup comments and remove family names from register macros
* Remove unused defines
There should be no functional change resulting from this patch.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
| -rw-r--r-- | drivers/edac/amd64_edac.h | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index ba181830594..7323f1b493a 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -218,27 +218,23 @@ #define DBAM_MAX_VALUE 11 - -#define F10_DCLR_0 0x90 -#define F10_DCLR_1 0x190 +#define DCLR0 0x90 +#define DCLR1 0x190 #define REVE_WIDTH_128 BIT(16) #define F10_WIDTH_128 BIT(11) - -#define F10_DCHR_0 0x94 -#define F10_DCHR_1 0x194 - -#define F10_DCHR_FOUR_RANK_DIMM BIT(18) +#define DCHR0 0x94 +#define DCHR1 0x194 #define DDR3_MODE BIT(8) -#define F10_DCHR_MblMode BIT(6) - #define F10_DCTL_SEL_LOW 0x110 #define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800) #define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3) #define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0)) #define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2)) -#define dct_ganging_enabled(pvt) (pvt->dct_sel_low & BIT(4)) + +#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_low & BIT(4))) + #define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5)) #define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8)) #define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10)) @@ -262,7 +258,6 @@ #define K8_NBSL 0x48 - /* Family F10h: Normalized Extended Error Codes */ #define F10_NBSL_EXT_ERR_RES 0x0 #define F10_NBSL_EXT_ERR_ECC 0x8 |