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authorShow Liu <show.liu@linaro.org>2014-08-21 23:52:53 +0800
committerShow Liu <show.liu@linaro.org>2014-08-21 23:52:53 +0800
commit33cadf8b5dce86e742e63e0b79f0229e7d4a6e71 (patch)
tree6ea879b8768f8363aca1032982648faf5033cb38 /arch
parent99a44813718baa18b5ef101aa2fb5dddd692a1a5 (diff)
downloadlinaro-lsk-33cadf8b5dce86e742e63e0b79f0229e7d4a6e71.tar.gz
added exynos 542x support
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h205
1 files changed, 205 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 57344b7e98c..5deb43d9558 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -370,4 +370,209 @@
#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
+/* Only for EXYNOS5420 */
+#define EXYNOS5420_EMA_CON0 S5P_SYSREG(0x0400)
+#define EXYNOS5420_EMA_CON1 S5P_SYSREG(0x0404)
+#define EXYNOS5420_LPI_MASK S5P_PMUREG(0x0004)
+#define EXYNOS5420_LPI_MASK1 S5P_PMUREG(0x0008)
+#define EXYNOS5420_UFS (1 << 8)
+#define EXYNOS5420_ATB_KFC (1 << 13)
+#define EXYNOS5422_POWER_GATE_CTRL (1 << 15)
+#define EXYNOS5420_ATB_ISP_ARM (1 << 19)
+#define EXYNOS5420_EMULATION (1 << 31)
+#define ATB_ISP_ARM (1 << 12)
+#define ATB_KFC (1 << 13)
+#define ATB_NOC (1 << 14)
+
+#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE S5P_PMUREG(0x0100)+#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI S5P_PMUREG(0x0104)
+#define EXYNOS5420_UP_SCHEDULER S5P_PMUREG(0x0120)
+#define SPREAD_ENABLE 0xF
+#define SPREAD_USE_STANDWFI 0xF
+
+#define EXYNOS5420_BB_SEL_EN (1 << 31)
+#define EXYNOS5420_BB_PMOS_EN (1 << 7)
+#define EXYNOS5420_BB_1300X 0XF
+#define EXYNOS5420_BIAS_CON_ARM S5P_PMUREG(0x0780)
+#define EXYNOS5420_BIAS_CON_INT S5P_PMUREG(0x0784)
+#define EXYNOS5420_BIAS_CON_MIF S5P_PMUREG(0x0788)
+#define EXYNOS5420_BIAS_CON_KFC S5P_PMUREG(0x078C)
+#define EXYNOS5420_BIAS_CON_G3D S5P_PMUREG(0x0790)
+
+#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG S5P_PMUREG(0x1020)
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1024)
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1028)
+#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG S5P_PMUREG(0x1030)
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1034)
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1038)
+#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG S5P_PMUREG(0x1040)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1044)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
+#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG S5P_PMUREG(0x1050)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
+#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG S5P_PMUREG(0x1060)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1064)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1068)
+#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG S5P_PMUREG(0x1070)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1074)
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1078)
+#define EXYNOS5420_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1090)
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1094)
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1098)
+#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x10A0)
+#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG S5P_PMUREG(0x10B0)
+#define EXYNOS5420_KFC_L2_SYS_PWR_REG S5P_PMUREG(0x10D0)
+#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1158)
+#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x115C)
+#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1160)
+#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1174)
+#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1178)
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11B8)
+#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11BC)
+#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR S5P_PMUREG(0x11C0)
+#define EXYNOS5420_USBDEV_MEM_SYS_PWR S5P_PMUREG(0x11CC)
+#define EXYNOS5420_USBDEV1_MEM_SYS_PWR S5P_PMUREG(0x11D0)
+#define EXYNOS5420_SDMMC_MEM_SYS_PWR S5P_PMUREG(0x11D4)
+#define EXYNOS5420_CSSYS_MEM_SYS_PWR S5P_PMUREG(0x11D8)
+#define EXYNOS5420_SECSS_MEM_SYS_PWR S5P_PMUREG(0x11DC)
+#define EXYNOS5420_ROTATOR_MEM_SYS_PWR S5P_PMUREG(0x11E0)
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR S5P_PMUREG(0x11E4)
+#define EXYNOS5420_INTROM_MEM_SYS_PWR S5P_PMUREG(0x11E8)
+#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG S5P_PMUREG(0x1208)
+#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1210)
+#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1214)
+#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG S5P_PMUREG(0x1218)
+#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG S5P_PMUREG(0x121C)
+#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG S5P_PMUREG(0x1220)
+#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG S5P_PMUREG(0x1224)
+#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1228)
+#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x122C)
+#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1230)
+#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG S5P_PMUREG(0x1234)
+#define EXYNOS5420_DISP1_SYS_PWR_REG S5P_PMUREG(0x1410)
+#define EXYNOS5420_MAU_SYS_PWR_REG S5P_PMUREG(0x1414)
+#define EXYNOS5420_G2D_SYS_PWR_REG S5P_PMUREG(0x1418)
+#define EXYNOS5420_MSC_SYS_PWR_REG S5P_PMUREG(0x141C)
+#define EXYNOS5420_FSYS_SYS_PWR_REG S5P_PMUREG(0x1420)
+#define EXYNOS5420_FSYS2_SYS_PWR_REG S5P_PMUREG(0x1424)
+#define EXYNOS5420_PSGEN_SYS_PWR_REG S5P_PMUREG(0x1428)
+#define EXYNOS5420_PERIC_SYS_PWR_REG S5P_PMUREG(0x142C)
+#define EXYNOS5420_WCORE_SYS_PWR_REG S5P_PMUREG(0x1430)
+#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1490)
+#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1494)
+#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG S5P_PMUREG(0x1498)
+#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG S5P_PMUREG(0x149C)
+#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG S5P_PMUREG(0x14A0)
+#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG S5P_PMUREG(0x14A4)
+#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG S5P_PMUREG(0x14A8)
+#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG S5P_PMUREG(0x14AC)
+#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG S5P_PMUREG(0x14B0)
+#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG S5P_PMUREG(0x14BC)
+#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D0)
+#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D4)
+#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG S5P_PMUREG(0x14D8)
+#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG S5P_PMUREG(0x14DC)
+#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG S5P_PMUREG(0x14E0)
+#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG S5P_PMUREG(0x14E4)
+#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG S5P_PMUREG(0x14E8)
+#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG S5P_PMUREG(0x14EC)
+#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG S5P_PMUREG(0x14F0)
+#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG S5P_PMUREG(0x14F4)
+#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG S5P_PMUREG(0x1570)
+#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG S5P_PMUREG(0x1574)
+#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG S5P_PMUREG(0x1578)
+#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG S5P_PMUREG(0x157C)
+#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1590)
+#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1594)
+#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG S5P_PMUREG(0x1598)
+#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG S5P_PMUREG(0x159C)
+#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG S5P_PMUREG(0x15A0)
+#define EXYNOS5420_SFR_AXI_CGDIS1 S5P_PMUREG(0x15E4)
+#define EXYNOS_ARM_CORE2_CONFIGURATION S5P_PMUREG(0x2100)
+#define EXYNOS5420_ARM_CORE2_OPTION S5P_PMUREG(0x2108)
+#define EXYNOS_ARM_CORE3_CONFIGURATION S5P_PMUREG(0x2180)
+#define EXYNOS5420_ARM_CORE3_OPTION S5P_PMUREG(0x2188)
+#define EXYNOS5420_ARM_COMMON_STATUS S5P_PMUREG(0x2504)
+#define EXYNOS5420_ARM_COMMON_OPTION S5P_PMUREG(0x2508)
+#define EXYNOS5420_KFC_COMMON_STATUS S5P_PMUREG(0x2584)
+#define EXYNOS5420_KFC_COMMON_OPTION S5P_PMUREG(0x2588)
+#define EXYNOS5420_LOGIC_RESET_DURATION3 S5P_PMUREG(0x2D1C)
+
+#define EXYNOS5420_PAD_RET_GPIO_OPTION S5P_PMUREG(0x30C8)
+#define EXYNOS5420_PAD_RET_UART_OPTION S5P_PMUREG(0x30E8)
+#define EXYNOS5420_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3108)
+#define EXYNOS5420_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3128)
+#define EXYNOS5420_PAD_RET_MMCC_OPTION S5P_PMUREG(0x3148)
+#define EXYNOS5420_PAD_RET_HSI_OPTION S5P_PMUREG(0x3168)
+#define EXYNOS5420_PAD_RET_SPI_OPTION S5P_PMUREG(0x31C8)
+#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION S5P_PMUREG(0x31E8)
+#define EXYNOS_PAD_RET_DRAM_OPTION S5P_PMUREG(0x3008)
+#define EXYNOS_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
+#define EXYNOS_PAD_RET_JTAG_OPTION S5P_PMUREG(0x3048)
+#define EXYNOS_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
+#define EXYNOS_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
+#define EXYNOS_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
+#define EXYNOS_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
+#define EXYNOS_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
+#define EXYNOS_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
+
+#define EXYNOS_PS_HOLD_CONTROL S5P_PMUREG(0x330C)
+#define EXYNOS5_XXTI_DURATION3 S5P_PMUREG(0x343C)
+
+/* For SYS_PWR_REG */
+#define EXYNOS_SYS_PWR_CFG (1 << 0)
+
+#define EXYNOS5420_MFC_CONFIGURATION S5P_PMUREG(0x4060)
+#define EXYNOS5420_MFC_STATUS S5P_PMUREG(0x4064)
+#define EXYNOS5420_MFC_OPTION S5P_PMUREG(0x4068)
+#define EXYNOS5420_G3D_CONFIGURATION S5P_PMUREG(0x4080)
+#define EXYNOS5420_G3D_STATUS S5P_PMUREG(0x4084)
+#define EXYNOS5420_G3D_OPTION S5P_PMUREG(0x4088)
+#define EXYNOS5420_DISP0_CONFIGURATION S5P_PMUREG(0x40A0)
+#define EXYNOS5420_DISP0_STATUS S5P_PMUREG(0x40A4)
+#define EXYNOS5420_DISP0_OPTION S5P_PMUREG(0x40A8)
+#define EXYNOS5420_DISP1_CONFIGURATION S5P_PMUREG(0x40C0)
+#define EXYNOS5420_DISP1_STATUS S5P_PMUREG(0x40C4)
+#define EXYNOS5420_DISP1_OPTION S5P_PMUREG(0x40C8)
+#define EXYNOS5420_MAU_CONFIGURATION S5P_PMUREG(0x40E0)
+#define EXYNOS5420_MAU_STATUS S5P_PMUREG(0x40E4)
+#define EXYNOS5420_MAU_OPTION S5P_PMUREG(0x40E8)
+#define EXYNOS5420_FSYS2_OPTION S5P_PMUREG(0x4168)
+#define EXYNOS5420_PSGEN_OPTION S5P_PMUREG(0x4188)
+
+/* For EXYNOS_CENTRAL_SEQ_OPTION */
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 (1 << 16)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 (1 << 17)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 (1 << 24)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 (1 << 25)
+
+#define EXYNOS5420_ARM_USE_STANDBY_WFI0 (1 << 4)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI1 (1 << 5)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI2 (1 << 6)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI3 (1 << 7)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI0 (1 << 8)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI1 (1 << 9)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI2 (1 << 10)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI3 (1 << 11)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE0 (1 << 16)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE1 (1 << 17)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE2 (1 << 18)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE3 (1 << 19)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE0 (1 << 20)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE1 (1 << 21)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE2 (1 << 22)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE3 (1 << 23)
+
+#define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \
+ | EXYNOS5420_ARM_USE_STANDBY_WFI1 \
+ | EXYNOS5420_ARM_USE_STANDBY_WFI2 \
+ | EXYNOS5420_ARM_USE_STANDBY_WFI3 \
+ | EXYNOS5420_KFC_USE_STANDBY_WFI0 \
+ | EXYNOS5420_KFC_USE_STANDBY_WFI1 \
+ | EXYNOS5420_KFC_USE_STANDBY_WFI2 \
+ | EXYNOS5420_KFC_USE_STANDBY_WFI3)
+
+#define DUR_WAIT_RESET 0xF
+#define EXYNOS5420_SWRESET_KFC_SEL 0x3
+
#endif /* __ASM_ARCH_REGS_PMU_H */