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authorEric Miao <eric.y.miao@gmail.com>2007-06-06 06:32:38 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-12 14:28:10 +0100
commitc08b7b3ef6bf489ddabadc03e050f3db2ea44b5d (patch)
tree7933a8126ed112ae1cb7c40de14904d01c2fde86 /arch
parent486c955118dbbb0f13dc4d40cc5dac2b23f82676 (diff)
[ARM] 4435/1: PXA: remove PXA_INTERNAL_IRQS
1. define PXA_GPIO_IRQ_BASE to be right after the internal IRQs, and define PXA_GPIO_IRQ_NUM to be 128 for all PXA2xx variants 2. make the code specific to the high IRQ numbers (32..64) to be PXA27x specific 3. add a function pxa_init_irq_high() to initialize the internal high IRQ chip, the invoke of this function could be moved to PXA27x specific initialization code Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-pxa/irq.c26
1 files changed, 16 insertions, 10 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 45ce711f047..844d3de3ef4 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -67,7 +67,7 @@ static struct irq_chip pxa_internal_chip_low = {
.set_wake = pxa_set_wake,
};
-#if PXA_INTERNAL_IRQS > 32
+#ifdef CONFIG_PXA27x
/*
* This is for the second set of internal IRQs as found on the PXA27x.
@@ -90,6 +90,19 @@ static struct irq_chip pxa_internal_chip_high = {
.unmask = pxa_unmask_high_irq,
};
+void __init pxa_init_irq_high(void)
+{
+ int irq;
+
+ ICMR2 = 0;
+ ICLR2 = 0;
+
+ for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
+ set_irq_chip(irq, &pxa_internal_chip_high);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+}
#endif
/* Note that if an input/irq line ever gets changed to an output during
@@ -314,7 +327,6 @@ static struct irq_chip pxa_muxed_gpio_chip = {
.set_wake = pxa_set_gpio_wake,
};
-
void __init pxa_init_irq(void)
{
int irq;
@@ -338,8 +350,6 @@ void __init pxa_init_irq(void)
#ifdef CONFIG_PXA27x
/* And similarly for the extra regs on the PXA27x */
- ICMR2 = 0;
- ICLR2 = 0;
GFER3 = 0;
GRER3 = 0;
GEDR3 = GEDR3;
@@ -357,12 +367,8 @@ void __init pxa_init_irq(void)
set_irq_flags(irq, IRQF_VALID);
}
-#if PXA_INTERNAL_IRQS > 32
- for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
- set_irq_chip(irq, &pxa_internal_chip_high);
- set_irq_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
- }
+#ifdef CONFIG_PXA27x
+ pxa_init_irq_high();
#endif
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {