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authorMilton Miller <miltonm@bga.com>2011-06-29 20:58:33 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-11-25 14:11:26 +1100
commit8d3d589a7901dd93743e98a60a0bacde485437f3 (patch)
tree8c8d201d35f1eb606dd38c51620448ac7691fdd6 /arch/powerpc/include
parent7df1027542c9353bef4d027cb4ab8e99f69017b7 (diff)
downloadlinaro-lsk-8d3d589a7901dd93743e98a60a0bacde485437f3.tar.gz
powerpc/pseries: Software invalidatation of TCEs
Some pseries IOMMUs cache TCEs but don't snoop when the TCEs are changed in memory, hence we need manually invalidate in software. This adds code to do the invalidate. It keys off a device tree property to say where the to do the MMIO for the invalidate and some information on what the format of the invalidate including some magic routing info. it_busno get overloaded with this magic routing info and it_index with the MMIO address for the invalidate command. This then gets hooked into the building and freeing of TCEs. This is only useful on bare metal pseries. pHyp takes care of this when virtualised. Based on patch from Milton with cleanups from Mikey. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/tce.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index f663634cccc..3dead82d597 100644
--- a/arch/powerpc/include/asm/tce.h
+++ b/arch/powerpc/include/asm/tce.h
@@ -26,10 +26,12 @@
/*
* Tces come in two formats, one for the virtual bus and a different
- * format for PCI
+ * format for PCI. PCI TCEs can have hardware or software maintianed
+ * coherency.
*/
-#define TCE_VB 0
-#define TCE_PCI 1
+#define TCE_VB 0
+#define TCE_PCI 1
+#define TCE_PCI_SW_INVAL 2
/* TCE page size is 4096 bytes (1 << 12) */