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authorKumar Gala <galak@kernel.crashing.org>2011-08-27 06:14:23 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-10-06 23:36:55 -0500
commit37caf9f2a1b99d11ba71e17168d221da9ca13f24 (patch)
tree0f6c5452edf6d52b84e2d5a088779ad382d75a00 /arch/powerpc/include
parent09af52f78e58d9aee0980276833bf3adee3ed07b (diff)
downloadlinaro-lsk-37caf9f2a1b99d11ba71e17168d221da9ca13f24.tar.gz
powerpc/fsl-booke: Handle L1 D-cache parity error correctly on e500mc
If the L1 D-Cache is in write shadow mode the HW will auto-recover the error. However we might still log the error and cause a machine check (if L1CSR0[CPE] - Cache error checking enable). We should only treat the non-write shadow case as non-recoverable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/reg_booke.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39f9dd..28cdbd9f399 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -548,6 +548,9 @@
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
+/* Bit definitions for L1CSR2. */
+#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
+
/* Bit definitions for L2CSR0. */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */