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authorKyle Moffett <Kyle.D.Moffett@boeing.com>2011-12-02 06:28:03 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 13:43:08 +1100
commitbe8bec56dfac0574c4c08a50cd37e09bea941e3f (patch)
tree2c31c63a1b56f8cd79a49c358be9b6020118e7c8 /arch/powerpc/include/asm
parent996983b75cebb1bc1c2c545f20336f24ebfa17af (diff)
downloadlinaro-lsk-be8bec56dfac0574c4c08a50cd37e09bea941e3f.tar.gz
powerpc/mpic: Invert the meaning of MPIC_PRIMARY
It turns out that there are only 2 in-tree platforms which use MPICs which are not "primary": IBM Cell and PowerMac. To reduce the complexity of the typical board setup code, invert the MPIC_PRIMARY bit into MPIC_SECONDARY. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/mpic.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index ba0b2046106..b9d2c0fb049 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -334,11 +334,11 @@ struct mpic
* Note setting any ID (leaving those bits to 0) means standard MPIC
*/
-/* This is the primary controller, only that one has IPIs and
- * has afinity control. A non-primary MPIC always uses CPU0
- * registers only
+/*
+ * This is a secondary ("chained") controller; it only uses the CPU0
+ * registers. Primary controllers have IPIs and affinity control.
*/
-#define MPIC_PRIMARY 0x00000001
+#define MPIC_SECONDARY 0x00000001
/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN 0x00000002