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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 18:22:47 +1100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-12-07 18:22:47 +1100
commit48b1bf86c308532669571e929619e98a8d88ef54 (patch)
treef37beaafc114ca07e9fc807ca8544a4b5d5e3386 /arch/powerpc/include/asm
parent4666ca2aa344105da0da3afda48d987c82261c05 (diff)
parent09dc34a95bfbc6062e1e7de0b96175480924aea8 (diff)
downloadlinaro-lsk-48b1bf86c308532669571e929619e98a8d88ef54.tar.gz
Merge branch 'mpic' into next
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/mpic.h14
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e6fae49e0b7..67b4d983723 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -251,6 +251,9 @@ struct mpic_irq_save {
/* The instance data of a given MPIC */
struct mpic
{
+ /* The OpenFirmware dt node for this MPIC */
+ struct device_node *node;
+
/* The remapper for this MPIC */
struct irq_host *irqhost;
@@ -293,6 +296,9 @@ struct mpic
/* Register access method */
enum mpic_reg_type reg_type;
+ /* The physical base address of the MPIC */
+ phys_addr_t paddr;
+
/* The various ioremap'ed bases */
struct mpic_reg_bank gregs;
struct mpic_reg_bank tmregs;
@@ -331,11 +337,11 @@ struct mpic
* Note setting any ID (leaving those bits to 0) means standard MPIC
*/
-/* This is the primary controller, only that one has IPIs and
- * has afinity control. A non-primary MPIC always uses CPU0
- * registers only
+/*
+ * This is a secondary ("chained") controller; it only uses the CPU0
+ * registers. Primary controllers have IPIs and affinity control.
*/
-#define MPIC_PRIMARY 0x00000001
+#define MPIC_SECONDARY 0x00000001
/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN 0x00000002