diff options
| author | Jimi Xenidis <jimix@pobox.com> | 2011-09-29 10:55:13 +0000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2011-11-25 14:11:28 +1100 |
| commit | fac26ad4f9cb794c9d1032f55f40a31cb55be09a (patch) | |
| tree | 6acb31ab3fbc959de6f62aa4dd6ea08c004205f4 /arch/powerpc/include/asm/reg_booke.h | |
| parent | 9d670280908013004f173b2b86414d9b6918511b (diff) | |
powerpc/book3e: Add ICSWX/ACOP support to Book3e cores like A2
ICSWX is also used by the A2 processor to access coprocessors,
although not all "chips" that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis <jimix@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 03c48e819c8..500fe1dc43e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -187,6 +187,10 @@ #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ #endif +#ifdef CONFIG_PPC_ICSWX +#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */ +#endif + /* Bit definitions for CCR1. */ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ |