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authorKumar Gala <galak@kernel.crashing.org>2013-04-05 09:15:01 -0500
committerKumar Gala <galak@kernel.crashing.org>2013-04-09 09:52:32 -0500
commit9ac8f50a35a93928e750d6edc4133d1308f4f95d (patch)
treeaadbe97ba3d301ae54fa3b8709c7a6a2bda4e011 /arch/powerpc/boot
parentddb487dca347956ed3bedda1f5a00ab62d05ebff (diff)
downloadlinaro-lsk-9ac8f50a35a93928e750d6edc4133d1308f4f95d.tar.gz
powerpc/fsl-booke: Minor fixes to T4240 Si device tree
* Fix cpu unit address to match reg * Update compatible for rcpm & clockgen to be 2.0 instead of 2 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi22
2 files changed, 13 insertions, 13 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 1d7292627b7..e77e6adba05 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -364,12 +364,12 @@
};
clockgen: global-utilities@e1000 {
- compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2";
+ compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
};
rcpm: global-utilities@e2000 {
- compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2";
+ compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 9b39a438d69..a93c55a8856 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,57 +69,57 @@
reg = <0 1>;
next-level-cache = <&L2_1>;
};
- cpu1: PowerPC,e6500@1 {
+ cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2_1>;
};
- cpu2: PowerPC,e6500@2 {
+ cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
next-level-cache = <&L2_1>;
};
- cpu3: PowerPC,e6500@3 {
+ cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
next-level-cache = <&L2_1>;
};
- cpu4: PowerPC,e6500@4 {
+ cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
next-level-cache = <&L2_2>;
};
- cpu5: PowerPC,e6500@5 {
+ cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
next-level-cache = <&L2_2>;
};
- cpu6: PowerPC,e6500@6 {
+ cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
next-level-cache = <&L2_2>;
};
- cpu7: PowerPC,e6500@7 {
+ cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
next-level-cache = <&L2_2>;
};
- cpu8: PowerPC,e6500@8 {
+ cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
next-level-cache = <&L2_3>;
};
- cpu9: PowerPC,e6500@9 {
+ cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
next-level-cache = <&L2_3>;
};
- cpu10: PowerPC,e6500@10 {
+ cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
next-level-cache = <&L2_3>;
};
- cpu11: PowerPC,e6500@11 {
+ cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
next-level-cache = <&L2_3>;