diff options
authorJames Hogan <james.hogan@imgtec.com>2013-12-16 10:41:38 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-01-15 15:28:52 -0800
commitf783d8b1299501f0aa0586dbd4fa0460f5f33be0 (patch)
parent6e3eb1670fb74dd18a294990c52ff2f3f2e29824 (diff)
clk: clk-divider: fix divisor > 255 bug
commit 778037e1ccb75609846deca9e419449c1dc137fa upstream. Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers) merged in v3.6 added the _get_val function to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high. E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6d967416043..2ce22447d76 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,
return 0;
-static unsigned int _get_val(struct clk_divider *divider, u8 div)
+static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
if (divider->flags & CLK_DIVIDER_ONE_BASED)
return div;