arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  * Mike Turquette (mturquette@ti.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  * XXX Some of the ES1 clocks have been removed/changed; once support
  23  * is added for discriminating clocks by ES level, these should be added back
  24  * in.
  25  */
  26
  27 #include <linux/kernel.h>
  28 #include <linux/list.h>
  29 #include <linux/clk-private.h>
  30 #include <linux/clkdev.h>
  31
  32 #include "clock.h"
  33 #include "clock44xx.h"
  34 #include "cm1_44xx.h"
  35 #include "cm2_44xx.h"
  36 #include "cm-regbits-44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "control.h"
  40 #include "scrm44xx.h"
  41
  42 /* OMAP4 modulemode control */
  43 #define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
  44 #define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
  45
  46 /*LIST_HEAD(clocks);*/
  47
  48 /* Root clocks */
  49
  50 #if 0
  51 static struct clk_ops virt_ck_ops = {
  52         .recalc_rate    = &omap2_recalc_rate_fixed,
  53 };
  54
  55 static struct clk_ops root_ck_gate_ops = {
  56         .recalc_rate    = &omap2_recalc_rate_fixed,
  57         .enable         = &omap2_dflt_clk_enable,
  58         .disable                = &omap2_dflt_clk_disable,
  59 };
  60
  61 static struct clk_ops root_ck_ops = {
  62         .recalc_rate    = &omap2_recalc_rate_fixed,
  63 };
  64
  65 #endif
  66 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
  67
  68 DEFINE_CLK_FIXED_RATE(pad_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
  69
  70 DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
  71
  72 DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
  73
  74 DEFINE_CLK_FIXED_RATE(slimbus_clk, CLK_IS_ROOT, 12000000, 0x0);
  75
  76 DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
  77
  78 DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
  79
  80 DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
  81
  82 DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
  83
  84 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  85
  86 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  87
  88 DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
  89
  90 DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
  91
  92 static const struct clksel_rate div_1_0_rates[] = {
  93         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
  94         { .div = 0 },
  95 };
  96
  97 static const struct clksel_rate div_1_1_rates[] = {
  98         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
  99         { .div = 0 },
 100 };
 101
 102 static const struct clksel_rate div_1_2_rates[] = {
 103         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 104         { .div = 0 },
 105 };
 106
 107 static const struct clksel_rate div_1_3_rates[] = {
 108         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 109         { .div = 0 },
 110 };
 111
 112 static const struct clksel_rate div_1_4_rates[] = {
 113         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 114         { .div = 0 },
 115 };
 116
 117 static const struct clksel_rate div_1_5_rates[] = {
 118         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 119         { .div = 0 },
 120 };
 121
 122 static const struct clksel_rate div_1_6_rates[] = {
 123         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 124         { .div = 0 },
 125 };
 126
 127 static const struct clksel_rate div_1_7_rates[] = {
 128         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 129         { .div = 0 },
 130 };
 131
 132 static const struct clksel sys_clkin_sel[] = {
 133         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 134         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 135         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 136         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 137         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 138         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 139         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 140         { .parent = NULL },
 141 };
 142
 143 static char *sys_clkin_ck_parent_names[] = {
 144         "virt_12000000_ck",
 145         "virt_13000000_ck",
 146         "virt_16800000_ck",
 147         "virt_19200000_ck",
 148         "virt_26000000_ck",
 149         "virt_27000000_ck",
 150         "virt_38400000_ck",
 151 };
 152
 153 static struct clk *sys_clkin_ck_parents[] = {
 154         &virt_12000000_ck,
 155         &virt_13000000_ck,
 156         &virt_16800000_ck,
 157         &virt_19200000_ck,
 158         &virt_26000000_ck,
 159         &virt_27000000_ck,
 160         &virt_38400000_ck,
 161 };
 162
 163 DEFINE_CLK_MUX(sys_clkin_ck,
 164         sys_clkin_ck_parent_names,
 165         sys_clkin_ck_parents,
 166         0x0,
 167         OMAP4430_CM_SYS_CLKSEL,
 168         OMAP4430_SYS_CLKSEL_SHIFT,
 169         OMAP4430_SYS_CLKSEL_WIDTH,
 170         CLK_MUX_INDEX_ONE,
 171         NULL);
 172
 173 DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
 174
 175 DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
 176
 177 DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
 178
 179 DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
 180
 181 DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
 182
 183 /* Module clocks and DPLL outputs */
 184
 185 static char *abe_dpll_bypass_clk_mux_ck_parent_names[] = {
 186         "sys_clkin_ck",
 187         "sys_32k_ck",
 188 };
 189
 190 static struct clk *abe_dpll_bypass_clk_mux_ck_parents[] = {
 191         &sys_clkin_ck,
 192         &sys_32k_ck,
 193 };
 194
 195 DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck,
 196         abe_dpll_bypass_clk_mux_ck_parent_names,
 197         abe_dpll_bypass_clk_mux_ck_parents,
 198         0x0,
 199         OMAP4430_CM_L4_WKUP_CLKSEL,
 200         OMAP4430_CLKSEL_SHIFT,
 201         OMAP4430_CLKSEL_WIDTH,
 202         0x0,
 203         NULL);
 204
 205 static char *abe_dpll_refclk_mux_ck_parent_names[] = {
 206         "sys_clkin_ck",
 207         "sys_32k_ck",
 208 };
 209
 210 static struct clk *abe_dpll_refclk_mux_ck_parents[] = {
 211         &sys_clkin_ck,
 212         &sys_32k_ck,
 213 };
 214
 215 DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck,
 216         abe_dpll_refclk_mux_ck_parent_names,
 217         abe_dpll_refclk_mux_ck_parents,
 218         0x0,
 219         OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 220         OMAP4430_CLKSEL_0_0_SHIFT,
 221         OMAP4430_CLKSEL_0_0_WIDTH,
 222         0x0,
 223         NULL);
 224
 225 /* DPLL_ABE */
 226 static struct dpll_data dpll_abe_dd = {
 227         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 228         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 229         .clk_ref        = &abe_dpll_refclk_mux_ck,
 230         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 231         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 232         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 233         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 234         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 235         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 236         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 237         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 238         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 239         .max_multiplier = 2047,
 240         .max_divider    = 128,
 241         .min_divider    = 1,
 242 };
 243
 244
 245 static char *dpll_abe_ck_parents[] = {
 246         "abe_dpll_refclk_mux_ck",
 247 };
 248
 249 static struct clk dpll_abe_ck;
 250
 251 static const struct clk_ops dpll_abe_ck_ops = {
 252         .enable         = &omap3_noncore_dpll_enable,
 253         .disable        = &omap3_noncore_dpll_disable,
 254         .recalc_rate    = &omap3_dpll_recalc,
 255         .round_rate     = &omap2_dpll_round_rate,
 256         .set_rate       = &omap3_noncore_dpll_set_rate,
 257         .get_parent     = &omap2_init_dpll_parent,
 258 };
 259
 260 static struct clk_hw_omap dpll_abe_ck_hw = {
 261         .hw = {
 262                 .clk = &dpll_abe_ck,
 263         },
 264         .dpll_data      = &dpll_abe_dd,
 265         .allow_idle     = &omap3_dpll_allow_idle,
 266         .deny_idle      = &omap3_dpll_deny_idle,
 267 };
 268
 269 static struct clk dpll_abe_ck = {
 270         .name           = "dpll_abe_ck",
 271         .ops            = &dpll_abe_ck_ops,
 272         .hw             = &dpll_abe_ck_hw.hw,
 273         .parent_names = dpll_abe_ck_parents,
 274         .num_parents = ARRAY_SIZE(dpll_abe_ck_parents),
 275 };
 276
 277 static char *dpll_abe_x2_ck_parents[] = {
 278         "dpll_abe_ck",
 279 };
 280
 281 static struct clk dpll_abe_x2_ck;
 282
 283 static const struct clk_ops dpll_abe_x2_ck_ops = {
 284         .recalc_rate    = &omap3_clkoutx2_recalc,
 285 };
 286
 287 static struct clk_hw_omap dpll_abe_x2_ck_hw = {
 288         .hw = {
 289                 .clk = &dpll_abe_x2_ck,
 290         },
 291         .flags          = CLOCK_CLKOUTX2,
 292         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 293         .allow_idle     = &omap4_dpllmx_allow_gatectrl,
 294         .deny_idle      = &omap4_dpllmx_deny_gatectrl,
 295 };
 296
 297 static struct clk dpll_abe_x2_ck = {
 298         .name           = "dpll_abe_x2_ck",
 299         .ops            = &dpll_abe_x2_ck_ops,
 300         .hw             = &dpll_abe_x2_ck_hw.hw,
 301         .parent_names = dpll_abe_x2_ck_parents,
 302         .num_parents = ARRAY_SIZE(dpll_abe_x2_ck_parents),
 303 };
 304
 305 DEFINE_CLK_DIVIDER(dpll_abe_m2x2_ck,
 306         "dpll_abe_x2_ck",
 307         &dpll_abe_x2_ck,
 308         0x0,
 309         OMAP4430_CM_DIV_M2_DPLL_ABE,
 310         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 311         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
 312         CLK_DIVIDER_ONE_BASED,
 313         NULL);
 314
 315 static char *abe_24m_fclk_parents[] = {
 316         "dpll_abe_m2x2_ck",
 317 };
 318
 319 static struct clk abe_24m_fclk;
 320
 321 static const struct clk_ops abe_24m_fclk_ops = {
 322         .recalc_rate    = &omap_fixed_divisor_recalc,
 323 };
 324
 325 static struct clk_hw_omap abe_24m_fclk_hw = {
 326         .hw = {
 327                 .clk = &abe_24m_fclk,
 328         },
 329         .fixed_div              = 8,
 330 };
 331
 332 static struct clk abe_24m_fclk = {
 333         .name           = "abe_24m_fclk",
 334         .ops            = &abe_24m_fclk_ops,
 335         .hw             = &abe_24m_fclk_hw.hw,
 336         .parent_names = abe_24m_fclk_parents,
 337         .num_parents = ARRAY_SIZE(abe_24m_fclk_parents),
 338 };
 339
 340 static const struct clksel_rate div3_1to4_rates[] = {
 341         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 342         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 343         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 344         { .div = 0 },
 345 };
 346
 347 static const struct clksel abe_clk_div[] = {
 348         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 349         { .parent = NULL },
 350 };
 351
 352 static char *abe_clk_parents[] = {
 353         "dpll_abe_m2x2_ck",
 354 };
 355
 356 static struct clk abe_clk;
 357
 358 static const struct clk_ops abe_clk_ops = {
 359         .recalc_rate    = &omap2_clksel_recalc,
 360         .round_rate     = &omap2_clksel_round_rate,
 361         .set_rate       = &omap2_clksel_set_rate,
 362 };
 363
 364 static struct clk_hw_omap abe_clk_hw = {
 365         .hw = {
 366                 .clk = &abe_clk,
 367         },
 368         .clksel         = abe_clk_div,
 369         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 370         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 371 };
 372
 373 static struct clk abe_clk = {
 374         .name           = "abe_clk",
 375         .ops            = &abe_clk_ops,
 376         .hw             = &abe_clk_hw.hw,
 377         .parent_names = abe_clk_parents,
 378         .num_parents = ARRAY_SIZE(abe_clk_parents),
 379 };
 380
 381 static const struct clksel_rate div2_1to2_rates[] = {
 382         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 383         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 384         { .div = 0 },
 385 };
 386
 387 static const struct clksel aess_fclk_div[] = {
 388         { .parent = &abe_clk, .rates = div2_1to2_rates },
 389         { .parent = NULL },
 390 };
 391
 392 static char *aess_fclk_parents[] = {
 393         "abe_clk",
 394 };
 395
 396 static struct clk aess_fclk;
 397
 398 static const struct clk_ops aess_fclk_ops = {
 399         .recalc_rate    = &omap2_clksel_recalc,
 400         .round_rate     = &omap2_clksel_round_rate,
 401         .set_rate       = &omap2_clksel_set_rate,
 402 };
 403
 404 static struct clk_hw_omap aess_fclk_hw = {
 405         .hw = {
 406                 .clk = &aess_fclk,
 407         },
 408         .clksel         = aess_fclk_div,
 409         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 410         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 411 };
 412
 413 static struct clk aess_fclk = {
 414         .name           = "aess_fclk",
 415         .ops            = &aess_fclk_ops,
 416         .hw             = &aess_fclk_hw.hw,
 417         .parent_names = aess_fclk_parents,
 418         .num_parents = ARRAY_SIZE(aess_fclk_parents),
 419 };
 420
 421 DEFINE_CLK_DIVIDER(dpll_abe_m3x2_ck,
 422         "dpll_abe_x2_ck",
 423         &dpll_abe_x2_ck,
 424         0x0,
 425         OMAP4430_CM_DIV_M3_DPLL_ABE,
 426         OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT,
 427         OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH,
 428         CLK_DIVIDER_ONE_BASED,
 429         NULL);
 430
 431 static char *core_hsd_byp_clk_mux_ck_parent_names[] = {
 432         "sys_clkin_ck",
 433         "dpll_abe_m3x2_ck",
 434 };
 435
 436 static struct clk *core_hsd_byp_clk_mux_ck_parents[] = {
 437         &sys_clkin_ck,
 438         &dpll_abe_m3x2_ck,
 439 };
 440
 441 DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck,
 442         core_hsd_byp_clk_mux_ck_parent_names,
 443         core_hsd_byp_clk_mux_ck_parents,
 444         0x0,
 445         OMAP4430_CM_CLKSEL_DPLL_CORE,
 446         OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 447         OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
 448         0x0,
 449         NULL);
 450
 451 /* DPLL_CORE */
 452 static struct dpll_data dpll_core_dd = {
 453         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 454         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 455         .clk_ref        = &sys_clkin_ck,
 456         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 457         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 458         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 459         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 460         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 461         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 462         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 463         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 464         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 465         .max_multiplier = 2047,
 466         .max_divider    = 128,
 467         .min_divider    = 1,
 468 };
 469
 470
 471 static char *dpll_core_ck_parents[] = {
 472         "sys_clkin_ck",
 473 };
 474
 475 static struct clk dpll_core_ck;
 476
 477 static const struct clk_ops dpll_core_ck_ops = {
 478         .recalc_rate    = &omap3_dpll_recalc,
 479         .get_parent     = &omap2_init_dpll_parent,
 480 };
 481
 482 static struct clk_hw_omap dpll_core_ck_hw = {
 483         .hw = {
 484                 .clk = &dpll_core_ck,
 485         },
 486         .dpll_data      = &dpll_core_dd,
 487         .allow_idle     = &omap3_dpll_allow_idle,
 488         .deny_idle      = &omap3_dpll_deny_idle,
 489 };
 490
 491 static struct clk dpll_core_ck = {
 492         .name           = "dpll_core_ck",
 493         .ops            = &dpll_core_ck_ops,
 494         .hw             = &dpll_core_ck_hw.hw,
 495         .parent_names = dpll_core_ck_parents,
 496         .num_parents = ARRAY_SIZE(dpll_core_ck_parents),
 497 };
 498
 499 static char *dpll_core_x2_ck_parents[] = {
 500         "dpll_core_ck",
 501 };
 502
 503 static struct clk dpll_core_x2_ck;
 504
 505 static const struct clk_ops dpll_core_x2_ck_ops = {
 506         .recalc_rate    = &omap3_clkoutx2_recalc,
 507 };
 508
 509 static struct clk_hw_omap dpll_core_x2_ck_hw = {
 510         .hw = {
 511                 .clk = &dpll_core_x2_ck,
 512         },
 513 };
 514
 515 static struct clk dpll_core_x2_ck = {
 516         .name           = "dpll_core_x2_ck",
 517         .ops            = &dpll_core_x2_ck_ops,
 518         .hw             = &dpll_core_x2_ck_hw.hw,
 519         .parent_names = dpll_core_x2_ck_parents,
 520         .num_parents = ARRAY_SIZE(dpll_core_x2_ck_parents),
 521 };
 522
 523 DEFINE_CLK_DIVIDER(dpll_core_m6x2_ck,
 524         "dpll_core_x2_ck",
 525         &dpll_core_x2_ck,
 526         0x0,
 527         OMAP4430_CM_DIV_M6_DPLL_CORE,
 528         OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT,
 529         OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH,
 530         CLK_DIVIDER_ONE_BASED,
 531         NULL);
 532
 533 DEFINE_CLK_DIVIDER(dpll_core_m2_ck,
 534         "dpll_core_ck",
 535         &dpll_core_ck,
 536         0x0,
 537         OMAP4430_CM_DIV_M2_DPLL_CORE,
 538         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 539         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
 540         CLK_DIVIDER_ONE_BASED,
 541         NULL);
 542
 543 static char *ddrphy_ck_parents[] = {
 544         "dpll_core_m2_ck",
 545 };
 546
 547 static struct clk ddrphy_ck;
 548
 549 static const struct clk_ops ddrphy_ck_ops = {
 550         .recalc_rate    = &omap_fixed_divisor_recalc,
 551 };
 552
 553 static struct clk_hw_omap ddrphy_ck_hw = {
 554         .hw = {
 555                 .clk = &ddrphy_ck,
 556         },
 557         .fixed_div              = 2,
 558 };
 559
 560 static struct clk ddrphy_ck = {
 561         .name           = "ddrphy_ck",
 562         .ops            = &ddrphy_ck_ops,
 563         .hw             = &ddrphy_ck_hw.hw,
 564         .parent_names = ddrphy_ck_parents,
 565         .num_parents = ARRAY_SIZE(ddrphy_ck_parents),
 566 };
 567
 568 DEFINE_CLK_DIVIDER(dpll_core_m5x2_ck,
 569         "dpll_core_x2_ck",
 570         &dpll_core_x2_ck,
 571         0x0,
 572         OMAP4430_CM_DIV_M5_DPLL_CORE,
 573         OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
 574         OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
 575         CLK_DIVIDER_ONE_BASED,
 576         NULL);
 577
 578 static const struct clksel div_core_div[] = {
 579         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 580         { .parent = NULL },
 581 };
 582
 583 static char *div_core_ck_parents[] = {
 584         "dpll_core_m5x2_ck",
 585 };
 586
 587 static struct clk div_core_ck;
 588
 589 static const struct clk_ops div_core_ck_ops = {
 590         .recalc_rate    = &omap2_clksel_recalc,
 591         .round_rate     = &omap2_clksel_round_rate,
 592         .set_rate       = &omap2_clksel_set_rate,
 593 };
 594
 595 static struct clk_hw_omap div_core_ck_hw = {
 596         .hw = {
 597                 .clk = &div_core_ck,
 598         },
 599         .clksel         = div_core_div,
 600         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 601         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 602 };
 603
 604 static struct clk div_core_ck = {
 605         .name           = "div_core_ck",
 606         .ops            = &div_core_ck_ops,
 607         .hw             = &div_core_ck_hw.hw,
 608         .parent_names = div_core_ck_parents,
 609         .num_parents = ARRAY_SIZE(div_core_ck_parents),
 610 };
 611
 612 static const struct clksel_rate div4_1to8_rates[] = {
 613         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 614         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 615         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 616         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 617         { .div = 0 },
 618 };
 619
 620 static const struct clksel div_iva_hs_clk_div[] = {
 621         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 622         { .parent = NULL },
 623 };
 624
 625 static char *div_iva_hs_clk_parents[] = {
 626         "dpll_core_m5x2_ck",
 627 };
 628
 629 static struct clk div_iva_hs_clk;
 630
 631 static const struct clk_ops div_iva_hs_clk_ops = {
 632         .recalc_rate    = &omap2_clksel_recalc,
 633         .round_rate     = &omap2_clksel_round_rate,
 634         .set_rate       = &omap2_clksel_set_rate,
 635 };
 636
 637 static struct clk_hw_omap div_iva_hs_clk_hw = {
 638         .hw = {
 639                 .clk = &div_iva_hs_clk,
 640         },
 641         .clksel         = div_iva_hs_clk_div,
 642         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 643         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 644 };
 645
 646 static struct clk div_iva_hs_clk = {
 647         .name           = "div_iva_hs_clk",
 648         .ops            = &div_iva_hs_clk_ops,
 649         .hw             = &div_iva_hs_clk_hw.hw,
 650         .parent_names = div_iva_hs_clk_parents,
 651         .num_parents = ARRAY_SIZE(div_iva_hs_clk_parents),
 652 };
 653
 654 static char *div_mpu_hs_clk_parents[] = {
 655         "dpll_core_m5x2_ck",
 656 };
 657
 658 static struct clk div_mpu_hs_clk;
 659
 660 static const struct clk_ops div_mpu_hs_clk_ops = {
 661         .recalc_rate    = &omap2_clksel_recalc,
 662         .round_rate     = &omap2_clksel_round_rate,
 663         .set_rate       = &omap2_clksel_set_rate,
 664 };
 665
 666 static struct clk_hw_omap div_mpu_hs_clk_hw = {
 667         .hw = {
 668                 .clk = &div_mpu_hs_clk,
 669         },
 670         .clksel         = div_iva_hs_clk_div,
 671         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 672         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 673 };
 674
 675 static struct clk div_mpu_hs_clk = {
 676         .name           = "div_mpu_hs_clk",
 677         .ops            = &div_mpu_hs_clk_ops,
 678         .hw             = &div_mpu_hs_clk_hw.hw,
 679         .parent_names = div_mpu_hs_clk_parents,
 680         .num_parents = ARRAY_SIZE(div_mpu_hs_clk_parents),
 681 };
 682
 683 DEFINE_CLK_DIVIDER(dpll_core_m4x2_ck,
 684         "dpll_core_x2_ck",
 685         &dpll_core_x2_ck,
 686         0x0,
 687         OMAP4430_CM_DIV_M4_DPLL_CORE,
 688         OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT,
 689         OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH,
 690         CLK_DIVIDER_ONE_BASED,
 691         NULL);
 692
 693 static char *dll_clk_div_ck_parents[] = {
 694         "dpll_core_m4x2_ck",
 695 };
 696
 697 static struct clk dll_clk_div_ck;
 698
 699 static const struct clk_ops dll_clk_div_ck_ops = {
 700         .recalc_rate    = &omap_fixed_divisor_recalc,
 701 };
 702
 703 static struct clk_hw_omap dll_clk_div_ck_hw = {
 704         .hw = {
 705                 .clk = &dll_clk_div_ck,
 706         },
 707         .fixed_div              = 2,
 708 };
 709
 710 static struct clk dll_clk_div_ck = {
 711         .name           = "dll_clk_div_ck",
 712         .ops            = &dll_clk_div_ck_ops,
 713         .hw             = &dll_clk_div_ck_hw.hw,
 714         .parent_names = dll_clk_div_ck_parents,
 715         .num_parents = ARRAY_SIZE(dll_clk_div_ck_parents),
 716 };
 717
 718 DEFINE_CLK_DIVIDER(dpll_abe_m2_ck,
 719         "dpll_abe_ck",
 720         &dpll_abe_ck,
 721         0x0,
 722         OMAP4430_CM_DIV_M2_DPLL_ABE,
 723         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 724         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
 725         CLK_DIVIDER_ONE_BASED,
 726         NULL);
 727
 728 DEFINE_CLK_DIVIDER(dpll_core_m3x2_ck,
 729         "dpll_core_x2_ck",
 730         &dpll_core_x2_ck,
 731         0x0,
 732         OMAP4430_CM_DIV_M3_DPLL_CORE,
 733         OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT,
 734         OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH,
 735         CLK_DIVIDER_ONE_BASED,
 736         NULL);
 737
 738 DEFINE_CLK_DIVIDER(dpll_core_m7x2_ck,
 739         "dpll_core_x2_ck",
 740         &dpll_core_x2_ck,
 741         0x0,
 742         OMAP4430_CM_DIV_M7_DPLL_CORE,
 743         OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT,
 744         OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH,
 745         CLK_DIVIDER_ONE_BASED,
 746         NULL);
 747
 748 static char *iva_hsd_byp_clk_mux_ck_parent_names[] = {
 749         "sys_clkin_ck",
 750         "div_iva_hs_clk",
 751 };
 752
 753 static struct clk *iva_hsd_byp_clk_mux_ck_parents[] = {
 754         &sys_clkin_ck,
 755         &div_iva_hs_clk,
 756 };
 757
 758 DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck,
 759         iva_hsd_byp_clk_mux_ck_parent_names,
 760         iva_hsd_byp_clk_mux_ck_parents,
 761         0x0,
 762         OMAP4430_CM_CLKSEL_DPLL_IVA,
 763         OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 764         OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
 765         0x0,
 766         NULL);
 767
 768 /* DPLL_IVA */
 769 static struct dpll_data dpll_iva_dd = {
 770         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 771         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 772         .clk_ref        = &sys_clkin_ck,
 773         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 774         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 775         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 776         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 777         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 778         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 779         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 780         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 781         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 782         .max_multiplier = 2047,
 783         .max_divider    = 128,
 784         .min_divider    = 1,
 785 };
 786
 787
 788 static char *dpll_iva_ck_parents[] = {
 789         "sys_clkin_ck",
 790 };
 791
 792 static struct clk dpll_iva_ck;
 793
 794 static const struct clk_ops dpll_iva_ck_ops = {
 795         .enable         = &omap3_noncore_dpll_enable,
 796         .disable        = &omap3_noncore_dpll_disable,
 797         .recalc_rate    = &omap3_dpll_recalc,
 798         .round_rate     = &omap2_dpll_round_rate,
 799         .set_rate       = &omap3_noncore_dpll_set_rate,
 800         .get_parent     = &omap2_init_dpll_parent,
 801 };
 802
 803 static struct clk_hw_omap dpll_iva_ck_hw = {
 804         .hw = {
 805                 .clk = &dpll_iva_ck,
 806         },
 807         .dpll_data      = &dpll_iva_dd,
 808         .allow_idle     = &omap3_dpll_allow_idle,
 809         .deny_idle      = &omap3_dpll_deny_idle,
 810 };
 811
 812 static struct clk dpll_iva_ck = {
 813         .name           = "dpll_iva_ck",
 814         .ops            = &dpll_iva_ck_ops,
 815         .hw             = &dpll_iva_ck_hw.hw,
 816         .parent_names = dpll_iva_ck_parents,
 817         .num_parents = ARRAY_SIZE(dpll_iva_ck_parents),
 818 };
 819
 820 static char *dpll_iva_x2_ck_parents[] = {
 821         "dpll_iva_ck",
 822 };
 823
 824 static struct clk dpll_iva_x2_ck;
 825
 826 static const struct clk_ops dpll_iva_x2_ck_ops = {
 827         .recalc_rate    = &omap3_clkoutx2_recalc,
 828 };
 829
 830 static struct clk_hw_omap dpll_iva_x2_ck_hw = {
 831         .hw = {
 832                 .clk = &dpll_iva_x2_ck,
 833         },
 834 };
 835
 836 static struct clk dpll_iva_x2_ck = {
 837         .name           = "dpll_iva_x2_ck",
 838         .ops            = &dpll_iva_x2_ck_ops,
 839         .hw             = &dpll_iva_x2_ck_hw.hw,
 840         .parent_names = dpll_iva_x2_ck_parents,
 841         .num_parents = ARRAY_SIZE(dpll_iva_x2_ck_parents),
 842 };
 843
 844 DEFINE_CLK_DIVIDER(dpll_iva_m4x2_ck,
 845         "dpll_iva_x2_ck",
 846         &dpll_iva_x2_ck,
 847         0x0,
 848         OMAP4430_CM_DIV_M4_DPLL_IVA,
 849         OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT,
 850         OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH,
 851         CLK_DIVIDER_ONE_BASED,
 852         NULL);
 853
 854 DEFINE_CLK_DIVIDER(dpll_iva_m5x2_ck,
 855         "dpll_iva_x2_ck",
 856         &dpll_iva_x2_ck,
 857         0x0,
 858         OMAP4430_CM_DIV_M5_DPLL_IVA,
 859         OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
 860         OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
 861         CLK_DIVIDER_ONE_BASED,
 862         NULL);
 863
 864 /* DPLL_MPU */
 865 static struct dpll_data dpll_mpu_dd = {
 866         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 867         .clk_bypass     = &div_mpu_hs_clk,
 868         .clk_ref        = &sys_clkin_ck,
 869         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 870         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 871         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 872         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 873         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 874         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 875         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 876         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 877         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 878         .max_multiplier = 2047,
 879         .max_divider    = 128,
 880         .min_divider    = 1,
 881 };
 882
 883
 884 static char *dpll_mpu_ck_parents[] = {
 885         "sys_clkin_ck",
 886 };
 887
 888 static struct clk dpll_mpu_ck;
 889
 890 static const struct clk_ops dpll_mpu_ck_ops = {
 891         .enable         = &omap3_noncore_dpll_enable,
 892         .disable        = &omap3_noncore_dpll_disable,
 893         .recalc_rate    = &omap3_dpll_recalc,
 894         .round_rate     = &omap2_dpll_round_rate,
 895         .set_rate       = &omap3_noncore_dpll_set_rate,
 896         .get_parent     = &omap2_init_dpll_parent,
 897 };
 898
 899 static struct clk_hw_omap dpll_mpu_ck_hw = {
 900         .hw = {
 901                 .clk = &dpll_mpu_ck,
 902         },
 903         .dpll_data      = &dpll_mpu_dd,
 904         .allow_idle     = &omap3_dpll_allow_idle,
 905         .deny_idle      = &omap3_dpll_deny_idle,
 906 };
 907
 908 static struct clk dpll_mpu_ck = {
 909         .name           = "dpll_mpu_ck",
 910         .ops            = &dpll_mpu_ck_ops,
 911         .hw             = &dpll_mpu_ck_hw.hw,
 912         .parent_names = dpll_mpu_ck_parents,
 913         .num_parents = ARRAY_SIZE(dpll_mpu_ck_parents),
 914 };
 915
 916 DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck,
 917         "dpll_mpu_ck",
 918         &dpll_mpu_ck,
 919         0x0,
 920         OMAP4430_CM_DIV_M2_DPLL_MPU,
 921         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 922         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
 923         CLK_DIVIDER_ONE_BASED,
 924         NULL);
 925
 926 static char *per_hs_clk_div_ck_parents[] = {
 927         "dpll_abe_m3x2_ck",
 928 };
 929
 930 static struct clk per_hs_clk_div_ck;
 931
 932 static const struct clk_ops per_hs_clk_div_ck_ops = {
 933         .recalc_rate    = &omap_fixed_divisor_recalc,
 934 };
 935
 936 static struct clk_hw_omap per_hs_clk_div_ck_hw = {
 937         .hw = {
 938                 .clk = &per_hs_clk_div_ck,
 939         },
 940         .fixed_div              = 2,
 941 };
 942
 943 static struct clk per_hs_clk_div_ck = {
 944         .name           = "per_hs_clk_div_ck",
 945         .ops            = &per_hs_clk_div_ck_ops,
 946         .hw             = &per_hs_clk_div_ck_hw.hw,
 947         .parent_names = per_hs_clk_div_ck_parents,
 948         .num_parents = ARRAY_SIZE(per_hs_clk_div_ck_parents),
 949 };
 950
 951 static char *per_hsd_byp_clk_mux_ck_parent_names[] = {
 952         "sys_clkin_ck",
 953         "per_hs_clk_div_ck",
 954 };
 955
 956 static struct clk *per_hsd_byp_clk_mux_ck_parents[] = {
 957         &sys_clkin_ck,
 958         &per_hs_clk_div_ck,
 959 };
 960
 961 DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck,
 962         per_hsd_byp_clk_mux_ck_parent_names,
 963         per_hsd_byp_clk_mux_ck_parents,
 964         0x0,
 965         OMAP4430_CM_CLKSEL_DPLL_PER,
 966         OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 967         OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
 968         0x0,
 969         NULL);
 970
 971 /* DPLL_PER */
 972 static struct dpll_data dpll_per_dd = {
 973         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 974         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 975         .clk_ref        = &sys_clkin_ck,
 976         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 977         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 978         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 979         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 980         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 981         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 982         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 983         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 984         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 985         .max_multiplier = 2047,
 986         .max_divider    = 128,
 987         .min_divider    = 1,
 988 };
 989
 990
 991 static char *dpll_per_ck_parents[] = {
 992         "sys_clkin_ck",
 993 };
 994
 995 static struct clk dpll_per_ck;
 996
 997 static const struct clk_ops dpll_per_ck_ops = {
 998         .enable         = &omap3_noncore_dpll_enable,
 999         .disable        = &omap3_noncore_dpll_disable,
1000         .recalc_rate    = &omap3_dpll_recalc,
1001         .round_rate     = &omap2_dpll_round_rate,
1002         .set_rate       = &omap3_noncore_dpll_set_rate,
1003         .get_parent     = &omap2_init_dpll_parent,
1004 };
1005
1006 static struct clk_hw_omap dpll_per_ck_hw = {
1007         .hw = {
1008                 .clk = &dpll_per_ck,
1009         },
1010         .dpll_data      = &dpll_per_dd,
1011         .allow_idle     = &omap3_dpll_allow_idle,
1012         .deny_idle      = &omap3_dpll_deny_idle,
1013 };
1014
1015 static struct clk dpll_per_ck = {
1016         .name           = "dpll_per_ck",
1017         .ops            = &dpll_per_ck_ops,
1018         .hw             = &dpll_per_ck_hw.hw,
1019         .parent_names = dpll_per_ck_parents,
1020         .num_parents = ARRAY_SIZE(dpll_per_ck_parents),
1021 };
1022
1023 DEFINE_CLK_DIVIDER(dpll_per_m2_ck,
1024         "dpll_per_ck",
1025         &dpll_per_ck,
1026         0x0,
1027         OMAP4430_CM_DIV_M2_DPLL_PER,
1028         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
1029         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
1030         CLK_DIVIDER_ONE_BASED,
1031         NULL);
1032
1033 static char *dpll_per_x2_ck_parents[] = {
1034         "dpll_per_ck",
1035 };
1036
1037 static struct clk dpll_per_x2_ck;
1038
1039 static const struct clk_ops dpll_per_x2_ck_ops = {
1040         .recalc_rate    = &omap3_clkoutx2_recalc,
1041 };
1042
1043 static struct clk_hw_omap dpll_per_x2_ck_hw = {
1044         .hw = {
1045                 .clk = &dpll_per_x2_ck,
1046         },
1047         .flags          = CLOCK_CLKOUTX2,
1048         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
1049         .allow_idle     = &omap4_dpllmx_allow_gatectrl,
1050         .deny_idle      = &omap4_dpllmx_deny_gatectrl,
1051 };
1052
1053 static struct clk dpll_per_x2_ck = {
1054         .name           = "dpll_per_x2_ck",
1055         .ops            = &dpll_per_x2_ck_ops,
1056         .hw             = &dpll_per_x2_ck_hw.hw,
1057         .parent_names = dpll_per_x2_ck_parents,
1058         .num_parents = ARRAY_SIZE(dpll_per_x2_ck_parents),
1059 };
1060
1061 DEFINE_CLK_DIVIDER(dpll_per_m2x2_ck,
1062         "dpll_per_x2_ck",
1063         &dpll_per_x2_ck,
1064         0x0,
1065         OMAP4430_CM_DIV_M2_DPLL_PER,
1066         OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
1067         OMAP4430_DPLL_CLKOUT_DIV_WIDTH,
1068         CLK_DIVIDER_ONE_BASED,
1069         NULL);
1070
1071 DEFINE_CLK_DIVIDER(dpll_per_m3x2_ck,
1072         "dpll_per_x2_ck",
1073         &dpll_per_x2_ck,
1074         0x0,
1075         OMAP4430_CM_DIV_M3_DPLL_PER,
1076         OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT,
1077         OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH,
1078         CLK_DIVIDER_ONE_BASED,
1079         NULL);
1080
1081 DEFINE_CLK_DIVIDER(dpll_per_m4x2_ck,
1082         "dpll_per_x2_ck",
1083         &dpll_per_x2_ck,
1084         0x0,
1085         OMAP4430_CM_DIV_M4_DPLL_PER,
1086         OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT,
1087         OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH,
1088         CLK_DIVIDER_ONE_BASED,
1089         NULL);
1090
1091 DEFINE_CLK_DIVIDER(dpll_per_m5x2_ck,
1092         "dpll_per_x2_ck",
1093         &dpll_per_x2_ck,
1094         0x0,
1095         OMAP4430_CM_DIV_M5_DPLL_PER,
1096         OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
1097         OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
1098         CLK_DIVIDER_ONE_BASED,
1099         NULL);
1100
1101 DEFINE_CLK_DIVIDER(dpll_per_m6x2_ck,
1102         "dpll_per_x2_ck",
1103         &dpll_per_x2_ck,
1104         0x0,
1105         OMAP4430_CM_DIV_M6_DPLL_PER,
1106         OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT,
1107         OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH,
1108         CLK_DIVIDER_ONE_BASED,
1109         NULL);
1110
1111 DEFINE_CLK_DIVIDER(dpll_per_m7x2_ck,
1112         "dpll_per_x2_ck",
1113         &dpll_per_x2_ck,
1114         0x0,
1115         OMAP4430_CM_DIV_M7_DPLL_PER,
1116         OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT,
1117         OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH,
1118         CLK_DIVIDER_ONE_BASED,
1119         NULL);
1120
1121 static char *usb_hs_clk_div_ck_parents[] = {
1122         "dpll_abe_m3x2_ck",
1123 };
1124
1125 static struct clk usb_hs_clk_div_ck;
1126
1127 static const struct clk_ops usb_hs_clk_div_ck_ops = {
1128         .recalc_rate    = &omap_fixed_divisor_recalc,
1129 };
1130
1131 static struct clk_hw_omap usb_hs_clk_div_ck_hw = {
1132         .hw = {
1133                 .clk = &usb_hs_clk_div_ck,
1134         },
1135         .fixed_div              = 3,
1136 };
1137
1138 static struct clk usb_hs_clk_div_ck = {
1139         .name           = "usb_hs_clk_div_ck",
1140         .ops            = &usb_hs_clk_div_ck_ops,
1141         .hw             = &usb_hs_clk_div_ck_hw.hw,
1142         .parent_names = usb_hs_clk_div_ck_parents,
1143         .num_parents = ARRAY_SIZE(usb_hs_clk_div_ck_parents),
1144 };
1145
1146 /* DPLL_USB */
1147 static struct dpll_data dpll_usb_dd = {
1148         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
1149         .clk_bypass     = &usb_hs_clk_div_ck,
1150         .flags          = DPLL_J_TYPE,
1151         .clk_ref        = &sys_clkin_ck,
1152         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1153         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1154         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1155         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1156         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1157         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1158         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1159         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1160         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1161         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
1162         .max_multiplier = 4095,
1163         .max_divider    = 256,
1164         .min_divider    = 1,
1165 };
1166
1167
1168 static char *dpll_usb_ck_parents[] = {
1169         "sys_clkin_ck",
1170 };
1171
1172 static struct clk dpll_usb_ck;
1173
1174 static const struct clk_ops dpll_usb_ck_ops = {
1175         .enable         = &omap3_noncore_dpll_enable,
1176         .disable        = &omap3_noncore_dpll_disable,
1177         .recalc_rate    = &omap3_dpll_recalc,
1178         .round_rate     = &omap2_dpll_round_rate,
1179         .set_rate       = &omap3_noncore_dpll_set_rate,
1180         .get_parent     = &omap2_init_dpll_parent,
1181 };
1182
1183 static struct clk_hw_omap dpll_usb_ck_hw = {
1184         .hw = {
1185                 .clk = &dpll_usb_ck,
1186         },
1187         .dpll_data      = &dpll_usb_dd,
1188         .allow_idle     = &omap3_dpll_allow_idle,
1189         .deny_idle      = &omap3_dpll_deny_idle,
1190 };
1191
1192 static struct clk dpll_usb_ck = {
1193         .name           = "dpll_usb_ck",
1194         .ops            = &dpll_usb_ck_ops,
1195         .hw             = &dpll_usb_ck_hw.hw,
1196         .parent_names = dpll_usb_ck_parents,
1197         .num_parents = ARRAY_SIZE(dpll_usb_ck_parents),
1198 };
1199
1200 static char *dpll_usb_clkdcoldo_ck_parents[] = {
1201         "dpll_usb_ck",
1202 };
1203
1204 static struct clk dpll_usb_clkdcoldo_ck;
1205
1206 static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
1207 };
1208
1209 static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
1210         .hw = {
1211                 .clk = &dpll_usb_clkdcoldo_ck,
1212         },
1213         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
1214         .allow_idle     = &omap4_dpllmx_allow_gatectrl,
1215         .deny_idle      = &omap4_dpllmx_deny_gatectrl,
1216 };
1217
1218 static struct clk dpll_usb_clkdcoldo_ck = {
1219         .name           = "dpll_usb_clkdcoldo_ck",
1220         .ops            = &dpll_usb_clkdcoldo_ck_ops,
1221         .hw             = &dpll_usb_clkdcoldo_ck_hw.hw,
1222         .parent_names = dpll_usb_clkdcoldo_ck_parents,
1223         .num_parents = ARRAY_SIZE(dpll_usb_clkdcoldo_ck_parents),
1224 };
1225
1226 DEFINE_CLK_DIVIDER(dpll_usb_m2_ck,
1227         "dpll_usb_ck",
1228         &dpll_usb_ck,
1229         0x0,
1230         OMAP4430_CM_DIV_M2_DPLL_USB,
1231         OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT,
1232         OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH,
1233         CLK_DIVIDER_ONE_BASED,
1234         NULL);
1235
1236 static char *ducati_clk_mux_ck_parent_names[] = {
1237         "div_core_ck",
1238         "dpll_per_m6x2_ck",
1239 };
1240
1241 static struct clk *ducati_clk_mux_ck_parents[] = {
1242         &div_core_ck,
1243         &dpll_per_m6x2_ck,
1244 };
1245
1246 DEFINE_CLK_MUX(ducati_clk_mux_ck,
1247         ducati_clk_mux_ck_parent_names,
1248         ducati_clk_mux_ck_parents,
1249         0x0,
1250         OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1251         OMAP4430_CLKSEL_0_0_SHIFT,
1252         OMAP4430_CLKSEL_0_0_WIDTH,
1253         0x0,
1254         NULL);
1255
1256 static char *func_12m_fclk_parents[] = {
1257         "dpll_per_m2x2_ck",
1258 };
1259
1260 static struct clk func_12m_fclk;
1261
1262 static const struct clk_ops func_12m_fclk_ops = {
1263         .recalc_rate    = &omap_fixed_divisor_recalc,
1264 };
1265
1266 static struct clk_hw_omap func_12m_fclk_hw = {
1267         .hw = {
1268                 .clk = &func_12m_fclk,
1269         },
1270         .fixed_div              = 16,
1271 };
1272
1273 static struct clk func_12m_fclk = {
1274         .name           = "func_12m_fclk",
1275         .ops            = &func_12m_fclk_ops,
1276         .hw             = &func_12m_fclk_hw.hw,
1277         .parent_names = func_12m_fclk_parents,
1278         .num_parents = ARRAY_SIZE(func_12m_fclk_parents),
1279 };
1280
1281 static char *func_24m_clk_parents[] = {
1282         "dpll_per_m2_ck",
1283 };
1284
1285 static struct clk func_24m_clk;
1286
1287 static const struct clk_ops func_24m_clk_ops = {
1288         .recalc_rate    = &omap_fixed_divisor_recalc,
1289 };
1290
1291 static struct clk_hw_omap func_24m_clk_hw = {
1292         .hw = {
1293                 .clk = &func_24m_clk,
1294         },
1295         .fixed_div              = 4,
1296 };
1297
1298 static struct clk func_24m_clk = {
1299         .name           = "func_24m_clk",
1300         .ops            = &func_24m_clk_ops,
1301         .hw             = &func_24m_clk_hw.hw,
1302         .parent_names = func_24m_clk_parents,
1303         .num_parents = ARRAY_SIZE(func_24m_clk_parents),
1304 };
1305
1306 static char *func_24mc_fclk_parents[] = {
1307         "dpll_per_m2x2_ck",
1308 };
1309
1310 static struct clk func_24mc_fclk;
1311
1312 static const struct clk_ops func_24mc_fclk_ops = {
1313         .recalc_rate    = &omap_fixed_divisor_recalc,
1314 };
1315
1316 static struct clk_hw_omap func_24mc_fclk_hw = {
1317         .hw = {
1318                 .clk = &func_24mc_fclk,
1319         },
1320         .fixed_div              = 8,
1321 };
1322
1323 static struct clk func_24mc_fclk = {
1324         .name           = "func_24mc_fclk",
1325         .ops            = &func_24mc_fclk_ops,
1326         .hw             = &func_24mc_fclk_hw.hw,
1327         .parent_names = func_24mc_fclk_parents,
1328         .num_parents = ARRAY_SIZE(func_24mc_fclk_parents),
1329 };
1330
1331 static const struct clksel_rate div2_4to8_rates[] = {
1332         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1333         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1334         { .div = 0 },
1335 };
1336
1337 static const struct clksel func_48m_fclk_div[] = {
1338         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1339         { .parent = NULL },
1340 };
1341
1342 static char *func_48m_fclk_parents[] = {
1343         "dpll_per_m2x2_ck",
1344 };
1345
1346 static struct clk func_48m_fclk;
1347
1348 static const struct clk_ops func_48m_fclk_ops = {
1349         .recalc_rate    = &omap2_clksel_recalc,
1350         .round_rate     = &omap2_clksel_round_rate,
1351         .set_rate       = &omap2_clksel_set_rate,
1352 };
1353
1354 static struct clk_hw_omap func_48m_fclk_hw = {
1355         .hw = {
1356                 .clk = &func_48m_fclk,
1357         },
1358         .clksel         = func_48m_fclk_div,
1359         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1360         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1361 };
1362
1363 static struct clk func_48m_fclk = {
1364         .name           = "func_48m_fclk",
1365         .ops            = &func_48m_fclk_ops,
1366         .hw             = &func_48m_fclk_hw.hw,
1367         .parent_names = func_48m_fclk_parents,
1368         .num_parents = ARRAY_SIZE(func_48m_fclk_parents),
1369 };
1370
1371 static char *func_48mc_fclk_parents[] = {
1372         "dpll_per_m2x2_ck",
1373 };
1374
1375 static struct clk func_48mc_fclk;
1376
1377 static const struct clk_ops func_48mc_fclk_ops = {
1378         .recalc_rate    = &omap_fixed_divisor_recalc,
1379 };
1380
1381 static struct clk_hw_omap func_48mc_fclk_hw = {
1382         .hw = {
1383                 .clk = &func_48mc_fclk,
1384         },
1385         .fixed_div              = 4,
1386 };
1387
1388 static struct clk func_48mc_fclk = {
1389         .name           = "func_48mc_fclk",
1390         .ops            = &func_48mc_fclk_ops,
1391         .hw             = &func_48mc_fclk_hw.hw,
1392         .parent_names = func_48mc_fclk_parents,
1393         .num_parents = ARRAY_SIZE(func_48mc_fclk_parents),
1394 };
1395
1396 static const struct clksel_rate div2_2to4_rates[] = {
1397         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1398         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1399         { .div = 0 },
1400 };
1401
1402 static const struct clksel func_64m_fclk_div[] = {
1403         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1404         { .parent = NULL },
1405 };
1406
1407 static char *func_64m_fclk_parents[] = {
1408         "dpll_per_m4x2_ck",
1409 };
1410
1411 static struct clk func_64m_fclk;
1412
1413 static const struct clk_ops func_64m_fclk_ops = {
1414         .recalc_rate    = &omap2_clksel_recalc,
1415         .round_rate     = &omap2_clksel_round_rate,
1416         .set_rate       = &omap2_clksel_set_rate,
1417 };
1418
1419 static struct clk_hw_omap func_64m_fclk_hw = {
1420         .hw = {
1421                 .clk = &func_64m_fclk,
1422         },
1423         .clksel         = func_64m_fclk_div,
1424         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1425         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1426 };
1427
1428 static struct clk func_64m_fclk = {
1429         .name           = "func_64m_fclk",
1430         .ops            = &func_64m_fclk_ops,
1431         .hw             = &func_64m_fclk_hw.hw,
1432         .parent_names = func_64m_fclk_parents,
1433         .num_parents = ARRAY_SIZE(func_64m_fclk_parents),
1434 };
1435
1436 static const struct clksel func_96m_fclk_div[] = {
1437         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1438         { .parent = NULL },
1439 };
1440
1441 static char *func_96m_fclk_parents[] = {
1442         "dpll_per_m2x2_ck",
1443 };
1444
1445 static struct clk func_96m_fclk;
1446
1447 static const struct clk_ops func_96m_fclk_ops = {
1448         .recalc_rate    = &omap2_clksel_recalc,
1449         .round_rate     = &omap2_clksel_round_rate,
1450         .set_rate       = &omap2_clksel_set_rate,
1451 };
1452
1453 static struct clk_hw_omap func_96m_fclk_hw = {
1454         .hw = {
1455                 .clk = &func_96m_fclk,
1456         },
1457         .clksel         = func_96m_fclk_div,
1458         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1459         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1460 };
1461
1462 static struct clk func_96m_fclk = {
1463         .name           = "func_96m_fclk",
1464         .ops            = &func_96m_fclk_ops,
1465         .hw             = &func_96m_fclk_hw.hw,
1466         .parent_names = func_96m_fclk_parents,
1467         .num_parents = ARRAY_SIZE(func_96m_fclk_parents),
1468 };
1469
1470 static const struct clksel_rate div2_1to8_rates[] = {
1471         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1472         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1473         { .div = 0 },
1474 };
1475
1476 static const struct clksel init_60m_fclk_div[] = {
1477         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1478         { .parent = NULL },
1479 };
1480
1481 static char *init_60m_fclk_parents[] = {
1482         "dpll_usb_m2_ck",
1483 };
1484
1485 static struct clk init_60m_fclk;
1486
1487 static const struct clk_ops init_60m_fclk_ops = {
1488         .recalc_rate    = &omap2_clksel_recalc,
1489         .round_rate     = &omap2_clksel_round_rate,
1490         .set_rate       = &omap2_clksel_set_rate,
1491 };
1492
1493 static struct clk_hw_omap init_60m_fclk_hw = {
1494         .hw = {
1495                 .clk = &init_60m_fclk,
1496         },
1497         .clksel         = init_60m_fclk_div,
1498         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1499         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1500 };
1501
1502 static struct clk init_60m_fclk = {
1503         .name           = "init_60m_fclk",
1504         .ops            = &init_60m_fclk_ops,
1505         .hw             = &init_60m_fclk_hw.hw,
1506         .parent_names = init_60m_fclk_parents,
1507         .num_parents = ARRAY_SIZE(init_60m_fclk_parents),
1508 };
1509
1510 static const struct clksel l3_div_div[] = {
1511         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1512         { .parent = NULL },
1513 };
1514
1515 static char *l3_div_ck_parents[] = {
1516         "div_core_ck",
1517 };
1518
1519 static struct clk l3_div_ck;
1520
1521 static const struct clk_ops l3_div_ck_ops = {
1522         .recalc_rate    = &omap2_clksel_recalc,
1523         .round_rate     = &omap2_clksel_round_rate,
1524         .set_rate       = &omap2_clksel_set_rate,
1525 };
1526
1527 static struct clk_hw_omap l3_div_ck_hw = {
1528         .hw = {
1529                 .clk = &l3_div_ck,
1530         },
1531         .clksel         = l3_div_div,
1532         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1533         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1534 };
1535
1536 static struct clk l3_div_ck = {
1537         .name           = "l3_div_ck",
1538         .ops            = &l3_div_ck_ops,
1539         .hw             = &l3_div_ck_hw.hw,
1540         .parent_names = l3_div_ck_parents,
1541         .num_parents = ARRAY_SIZE(l3_div_ck_parents),
1542 };
1543
1544 static const struct clksel l4_div_div[] = {
1545         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1546         { .parent = NULL },
1547 };
1548
1549 static char *l4_div_ck_parents[] = {
1550         "l3_div_ck",
1551 };
1552
1553 static struct clk l4_div_ck;
1554
1555 static const struct clk_ops l4_div_ck_ops = {
1556         .recalc_rate    = &omap2_clksel_recalc,
1557         .round_rate     = &omap2_clksel_round_rate,
1558         .set_rate       = &omap2_clksel_set_rate,
1559 };
1560
1561 static struct clk_hw_omap l4_div_ck_hw = {
1562         .hw = {
1563                 .clk = &l4_div_ck,
1564         },
1565         .clksel         = l4_div_div,
1566         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1567         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1568 };
1569
1570 static struct clk l4_div_ck = {
1571         .name           = "l4_div_ck",
1572         .ops            = &l4_div_ck_ops,
1573         .hw             = &l4_div_ck_hw.hw,
1574         .parent_names = l4_div_ck_parents,
1575         .num_parents = ARRAY_SIZE(l4_div_ck_parents),
1576 };
1577
1578 static char *lp_clk_div_ck_parents[] = {
1579         "dpll_abe_m2x2_ck",
1580 };
1581
1582 static struct clk lp_clk_div_ck;
1583
1584 static const struct clk_ops lp_clk_div_ck_ops = {
1585         .recalc_rate    = &omap_fixed_divisor_recalc,
1586 };
1587
1588 static struct clk_hw_omap lp_clk_div_ck_hw = {
1589         .hw = {
1590                 .clk = &lp_clk_div_ck,
1591         },
1592         .fixed_div              = 16,
1593 };
1594
1595 static struct clk lp_clk_div_ck = {
1596         .name           = "lp_clk_div_ck",
1597         .ops            = &lp_clk_div_ck_ops,
1598         .hw             = &lp_clk_div_ck_hw.hw,
1599         .parent_names = lp_clk_div_ck_parents,
1600         .num_parents = ARRAY_SIZE(lp_clk_div_ck_parents),
1601 };
1602
1603 static char *l4_wkup_clk_mux_ck_parent_names[] = {
1604         "sys_clkin_ck",
1605         "lp_clk_div_ck",
1606 };
1607
1608 static struct clk *l4_wkup_clk_mux_ck_parents[] = {
1609         &sys_clkin_ck,
1610         &lp_clk_div_ck,
1611 };
1612
1613 DEFINE_CLK_MUX(l4_wkup_clk_mux_ck,
1614         l4_wkup_clk_mux_ck_parent_names,
1615         l4_wkup_clk_mux_ck_parents,
1616         0x0,
1617         OMAP4430_CM_L4_WKUP_CLKSEL,
1618         OMAP4430_CLKSEL_0_0_SHIFT,
1619         OMAP4430_CLKSEL_0_0_WIDTH,
1620         0x0,
1621         NULL);
1622
1623 static const struct clksel_rate div2_2to1_rates[] = {
1624         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1625         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1626         { .div = 0 },
1627 };
1628
1629 static const struct clksel ocp_abe_iclk_div[] = {
1630         { .parent = &aess_fclk, .rates = div2_2to1_rates },
1631         { .parent = NULL },
1632 };
1633
1634 static char *ocp_abe_iclk_parents[] = {
1635         "aess_fclk",
1636 };
1637
1638 static struct clk ocp_abe_iclk;
1639
1640 static const struct clk_ops ocp_abe_iclk_ops = {
1641         .recalc_rate    = &omap2_clksel_recalc,
1642         .round_rate     = &omap2_clksel_round_rate,
1643         .set_rate       = &omap2_clksel_set_rate,
1644 };
1645
1646 static struct clk_hw_omap ocp_abe_iclk_hw = {
1647         .hw = {
1648                 .clk = &ocp_abe_iclk,
1649         },
1650         .clksel         = ocp_abe_iclk_div,
1651         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1652         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1653 };
1654
1655 static struct clk ocp_abe_iclk = {
1656         .name           = "ocp_abe_iclk",
1657         .ops            = &ocp_abe_iclk_ops,
1658         .hw             = &ocp_abe_iclk_hw.hw,
1659         .parent_names = ocp_abe_iclk_parents,
1660         .num_parents = ARRAY_SIZE(ocp_abe_iclk_parents),
1661 };
1662
1663 static char *per_abe_24m_fclk_parents[] = {
1664         "dpll_abe_m2_ck",
1665 };
1666
1667 static struct clk per_abe_24m_fclk;
1668
1669 static const struct clk_ops per_abe_24m_fclk_ops = {
1670         .recalc_rate    = &omap_fixed_divisor_recalc,
1671 };
1672
1673 static struct clk_hw_omap per_abe_24m_fclk_hw = {
1674         .hw = {
1675                 .clk = &per_abe_24m_fclk,
1676         },
1677         .fixed_div              = 4,
1678 };
1679
1680 static struct clk per_abe_24m_fclk = {
1681         .name           = "per_abe_24m_fclk",
1682         .ops            = &per_abe_24m_fclk_ops,
1683         .hw             = &per_abe_24m_fclk_hw.hw,
1684         .parent_names = per_abe_24m_fclk_parents,
1685         .num_parents = ARRAY_SIZE(per_abe_24m_fclk_parents),
1686 };
1687
1688 static const struct clksel per_abe_nc_fclk_div[] = {
1689         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1690         { .parent = NULL },
1691 };
1692
1693 static char *per_abe_nc_fclk_parents[] = {
1694         "dpll_abe_m2_ck",
1695 };
1696
1697 static struct clk per_abe_nc_fclk;
1698
1699 static const struct clk_ops per_abe_nc_fclk_ops = {
1700         .recalc_rate    = &omap2_clksel_recalc,
1701         .round_rate     = &omap2_clksel_round_rate,
1702         .set_rate       = &omap2_clksel_set_rate,
1703 };
1704
1705 static struct clk_hw_omap per_abe_nc_fclk_hw = {
1706         .hw = {
1707                 .clk = &per_abe_nc_fclk,
1708         },
1709         .clksel         = per_abe_nc_fclk_div,
1710         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1711         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1712 };
1713
1714 static struct clk per_abe_nc_fclk = {
1715         .name           = "per_abe_nc_fclk",
1716         .ops            = &per_abe_nc_fclk_ops,
1717         .hw             = &per_abe_nc_fclk_hw.hw,
1718         .parent_names = per_abe_nc_fclk_parents,
1719         .num_parents = ARRAY_SIZE(per_abe_nc_fclk_parents),
1720 };
1721
1722 static const struct clksel syc_clk_div_div[] = {
1723         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1724         { .parent = NULL },
1725 };
1726
1727 static char *syc_clk_div_ck_parents[] = {
1728         "sys_clkin_ck",
1729 };
1730
1731 static struct clk syc_clk_div_ck;
1732
1733 static const struct clk_ops syc_clk_div_ck_ops = {
1734         .recalc_rate    = &omap2_clksel_recalc,
1735         .round_rate     = &omap2_clksel_round_rate,
1736         .set_rate       = &omap2_clksel_set_rate,
1737 };
1738
1739 static struct clk_hw_omap syc_clk_div_ck_hw = {
1740         .hw = {
1741                 .clk = &syc_clk_div_ck,
1742         },
1743         .clksel         = syc_clk_div_div,
1744         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1745         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1746 };
1747
1748 static struct clk syc_clk_div_ck = {
1749         .name           = "syc_clk_div_ck",
1750         .ops            = &syc_clk_div_ck_ops,
1751         .hw             = &syc_clk_div_ck_hw.hw,
1752         .parent_names = syc_clk_div_ck_parents,
1753         .num_parents = ARRAY_SIZE(syc_clk_div_ck_parents),
1754 };
1755
1756 /* Leaf clocks controlled by modules */
1757
1758 static struct clk_ops leaf_ck_ops = {
1759         .enable         = &omap2_dflt_clk_enable,
1760         .disable        = &omap2_dflt_clk_disable,
1761 };
1762
1763 static char *aes1_fck_parent_names[] = {
1764         "l3_div_ck",
1765 };
1766
1767 static struct clk aes1_fck;
1768
1769 static struct clk_hw_omap aes1_fck_hw = {
1770         .hw = {
1771                 .clk = &aes1_fck,
1772         },
1773         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1774         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1775         .clkdm_name     = "l4_secure_clkdm",
1776 };
1777
1778 static struct clk aes1_fck = {
1779         .name           = "aes1_fck",
1780         .ops            = &leaf_ck_ops,
1781         .hw             = &aes1_fck_hw.hw,
1782         .parent_names   = aes1_fck_parent_names,
1783         .num_parents    = ARRAY_SIZE(aes1_fck_parent_names),
1784         };
1785
1786 static char *aes2_fck_parent_names[] = {
1787         "l3_div_ck",
1788 };
1789
1790 static struct clk aes2_fck;
1791
1792 static struct clk_hw_omap aes2_fck_hw = {
1793         .hw = {
1794                 .clk = &aes2_fck,
1795         },
1796         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1797         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1798         .clkdm_name     = "l4_secure_clkdm",
1799 };
1800
1801 static struct clk aes2_fck = {
1802         .name           = "aes2_fck",
1803         .ops            = &leaf_ck_ops,
1804         .hw             = &aes2_fck_hw.hw,
1805         .parent_names   = aes2_fck_parent_names,
1806         .num_parents    = ARRAY_SIZE(aes2_fck_parent_names),
1807         };
1808
1809 static char *aess_fck_parent_names[] = {
1810         "aess_fclk",
1811 };
1812
1813 static struct clk aess_fck;
1814
1815 static struct clk_hw_omap aess_fck_hw = {
1816         .hw = {
1817                 .clk = &aess_fck,
1818         },
1819         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1820         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1821         .clkdm_name     = "abe_clkdm",
1822 };
1823
1824 static struct clk aess_fck = {
1825         .name           = "aess_fck",
1826         .ops            = &leaf_ck_ops,
1827         .hw             = &aess_fck_hw.hw,
1828         .parent_names   = aess_fck_parent_names,
1829         .num_parents    = ARRAY_SIZE(aess_fck_parent_names),
1830         };
1831
1832 static struct clk bandgap_fclk;
1833
1834 static char *bandgap_fclk_parent_names[] = {
1835         "sys_32k_ck",
1836 };
1837
1838 static struct clk_hw_omap bandgap_fclk_hw = {
1839         .hw = {
1840                 .clk = &bandgap_fclk,
1841         },
1842         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1843         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1844         .clkdm_name     = "l4_wkup_clkdm",
1845 };
1846
1847 static struct clk bandgap_fclk = {
1848         .name           = "bandgap_fclk",
1849         .ops            = &leaf_ck_ops,
1850         .hw             = &bandgap_fclk_hw.hw,
1851         .parent_names   = bandgap_fclk_parent_names,
1852         .num_parents    = ARRAY_SIZE(bandgap_fclk_parent_names),
1853 };
1854
1855 static char *des3des_fck_parent_names[] = {
1856         "l4_div_ck",
1857 };
1858
1859 static struct clk des3des_fck;
1860
1861 static struct clk_hw_omap des3des_fck_hw = {
1862         .hw = {
1863                 .clk = &des3des_fck,
1864         },
1865         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1866         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1867         .clkdm_name     = "l4_secure_clkdm",
1868 };
1869
1870 static struct clk des3des_fck = {
1871         .name           = "des3des_fck",
1872         .ops            = &leaf_ck_ops,
1873         .hw             = &des3des_fck_hw.hw,
1874         .parent_names   = des3des_fck_parent_names,
1875         .num_parents    = ARRAY_SIZE(des3des_fck_parent_names),
1876         };
1877
1878 static char *dmic_sync_mux_ck_parent_names[] = {
1879         "abe_24m_fclk",
1880         "syc_clk_div_ck",
1881         "func_24m_clk",
1882 };
1883
1884 static struct clk *dmic_sync_mux_ck_parents[] = {
1885         &abe_24m_fclk,
1886         &syc_clk_div_ck,
1887         &func_24m_clk,
1888 };
1889
1890 DEFINE_CLK_MUX(dmic_sync_mux_ck,
1891         dmic_sync_mux_ck_parent_names,
1892         dmic_sync_mux_ck_parents,
1893         0x0,
1894         OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1895         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1896         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
1897         0x0,
1898         NULL);
1899
1900 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1901         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1902         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1903         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1904         { .parent = NULL },
1905 };
1906
1907 static char *dmic_fck_parents[] = {
1908         "dmic_sync_mux_ck",
1909         "pad_clks_ck",
1910         "slimbus_clk",
1911 };
1912
1913 /* Merged func_dmic_abe_gfclk into dmic */
1914 static struct clk dmic_fck;
1915
1916 static const struct clk_ops dmic_fck_ops = {
1917         .enable         = &omap2_dflt_clk_enable,
1918         .disable        = &omap2_dflt_clk_disable,
1919         .recalc_rate    = &omap2_clksel_recalc,
1920         .get_parent     = &omap2_init_clksel_parent,
1921         .set_parent     = &omap2_clksel_set_parent,
1922         .init   = &omap2_init_clk_clkdm,
1923 };
1924
1925 static struct clk_hw_omap dmic_fck_hw = {
1926         .hw = {
1927                 .clk = &dmic_fck,
1928         },
1929         .clkdm_name     = "abe_clkdm",
1930         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1931         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1932         .clksel         = func_dmic_abe_gfclk_sel,
1933         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1934         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1935 };
1936
1937 static struct clk dmic_fck = {
1938         .name           = "dmic_fck",
1939         .ops            = &dmic_fck_ops,
1940         .hw             = &dmic_fck_hw.hw,
1941         .parent_names = dmic_fck_parents,
1942         .num_parents = ARRAY_SIZE(dmic_fck_parents),
1943 };
1944
1945 static char *dsp_fck_parent_names[] = {
1946         "dpll_iva_m4x2_ck",
1947 };
1948
1949 static struct clk dsp_fck;
1950
1951 static struct clk_hw_omap dsp_fck_hw = {
1952         .hw = {
1953                 .clk = &dsp_fck,
1954         },
1955         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1956         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1957         .clkdm_name     = "tesla_clkdm",
1958 };
1959
1960 static struct clk dsp_fck = {
1961         .name           = "dsp_fck",
1962         .ops            = &leaf_ck_ops,
1963         .hw             = &dsp_fck_hw.hw,
1964         .parent_names   = dsp_fck_parent_names,
1965         .num_parents    = ARRAY_SIZE(dsp_fck_parent_names),
1966         };
1967
1968 static struct clk dss_sys_clk;
1969
1970 static char *dss_sys_clk_parent_names[] = {
1971         "syc_clk_div_ck",
1972 };
1973
1974 static struct clk_hw_omap dss_sys_clk_hw = {
1975         .hw = {
1976                 .clk = &dss_sys_clk,
1977         },
1978         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1979         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1980         .clkdm_name     = "l3_dss_clkdm",
1981 };
1982
1983 static struct clk dss_sys_clk = {
1984         .name           = "dss_sys_clk",
1985         .ops            = &leaf_ck_ops,
1986         .hw             = &dss_sys_clk_hw.hw,
1987         .parent_names   = dss_sys_clk_parent_names,
1988         .num_parents    = ARRAY_SIZE(dss_sys_clk_parent_names),
1989 };
1990
1991 static struct clk dss_tv_clk;
1992
1993 static char *dss_tv_clk_parent_names[] = {
1994         "extalt_clkin_ck",
1995 };
1996
1997 static struct clk_hw_omap dss_tv_clk_hw = {
1998         .hw = {
1999                 .clk = &dss_tv_clk,
2000         },
2001         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
2002         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
2003         .clkdm_name     = "l3_dss_clkdm",
2004 };
2005
2006 static struct clk dss_tv_clk = {
2007         .name           = "dss_tv_clk",
2008         .ops            = &leaf_ck_ops,
2009         .hw             = &dss_tv_clk_hw.hw,
2010         .parent_names   = dss_tv_clk_parent_names,
2011         .num_parents    = ARRAY_SIZE(dss_tv_clk_parent_names),
2012 };
2013
2014 static struct clk dss_dss_clk;
2015
2016 static char *dss_dss_clk_parent_names[] = {
2017         "dpll_per_m5x2_ck",
2018 };
2019
2020 static struct clk_hw_omap dss_dss_clk_hw = {
2021         .hw = {
2022                 .clk = &dss_dss_clk,
2023         },
2024         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
2025         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
2026         .clkdm_name     = "l3_dss_clkdm",
2027 };
2028
2029 static struct clk dss_dss_clk = {
2030         .name           = "dss_dss_clk",
2031         .ops            = &leaf_ck_ops,
2032         .hw             = &dss_dss_clk_hw.hw,
2033         .parent_names   = dss_dss_clk_parent_names,
2034         .num_parents    = ARRAY_SIZE(dss_dss_clk_parent_names),
2035 };
2036
2037 static struct clk dss_48mhz_clk;
2038
2039 static char *dss_48mhz_clk_parent_names[] = {
2040         "func_48mc_fclk",
2041 };
2042
2043 static struct clk_hw_omap dss_48mhz_clk_hw = {
2044         .hw = {
2045                 .clk = &dss_48mhz_clk,
2046         },
2047         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
2048         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
2049         .clkdm_name     = "l3_dss_clkdm",
2050 };
2051
2052 static struct clk dss_48mhz_clk = {
2053         .name           = "dss_48mhz_clk",
2054         .ops            = &leaf_ck_ops,
2055         .hw             = &dss_48mhz_clk_hw.hw,
2056         .parent_names   = dss_48mhz_clk_parent_names,
2057         .num_parents    = ARRAY_SIZE(dss_48mhz_clk_parent_names),
2058 };
2059
2060 static char *dss_fck_parent_names[] = {
2061         "l3_div_ck",
2062 };
2063
2064 static struct clk dss_fck;
2065
2066 static struct clk_hw_omap dss_fck_hw = {
2067         .hw = {
2068                 .clk = &dss_fck,
2069         },
2070         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
2071         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2072         .clkdm_name     = "l3_dss_clkdm",
2073 };
2074
2075 static struct clk dss_fck = {
2076         .name           = "dss_fck",
2077         .ops            = &leaf_ck_ops,
2078         .hw             = &dss_fck_hw.hw,
2079         .parent_names   = dss_fck_parent_names,
2080         .num_parents    = ARRAY_SIZE(dss_fck_parent_names),
2081         };
2082
2083 static char *efuse_ctrl_cust_fck_parent_names[] = {
2084         "sys_clkin_ck",
2085 };
2086
2087 static struct clk efuse_ctrl_cust_fck;
2088
2089 static struct clk_hw_omap efuse_ctrl_cust_fck_hw = {
2090         .hw = {
2091                 .clk = &efuse_ctrl_cust_fck,
2092         },
2093         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
2094         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2095         .clkdm_name     = "l4_cefuse_clkdm",
2096 };
2097
2098 static struct clk efuse_ctrl_cust_fck = {
2099         .name           = "efuse_ctrl_cust_fck",
2100         .ops            = &leaf_ck_ops,
2101         .hw             = &efuse_ctrl_cust_fck_hw.hw,
2102         .parent_names   = efuse_ctrl_cust_fck_parent_names,
2103         .num_parents    = ARRAY_SIZE(efuse_ctrl_cust_fck_parent_names),
2104         };
2105
2106 static char *emif1_fck_parent_names[] = {
2107         "ddrphy_ck",
2108 };
2109
2110 static struct clk emif1_fck;
2111
2112 static struct clk_hw_omap emif1_fck_hw = {
2113         .hw = {
2114                 .clk = &emif1_fck,
2115         },
2116         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
2117         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2118         .flags          = ENABLE_ON_INIT,
2119         .clkdm_name     = "l3_emif_clkdm",
2120 };
2121
2122 static struct clk emif1_fck = {
2123         .name           = "emif1_fck",
2124         .ops            = &leaf_ck_ops,
2125         .hw             = &emif1_fck_hw.hw,
2126         .parent_names   = emif1_fck_parent_names,
2127         .num_parents    = ARRAY_SIZE(emif1_fck_parent_names),
2128         };
2129
2130 static char *emif2_fck_parent_names[] = {
2131         "ddrphy_ck",
2132 };
2133
2134 static struct clk emif2_fck;
2135
2136 static struct clk_hw_omap emif2_fck_hw = {
2137         .hw = {
2138                 .clk = &emif2_fck,
2139         },
2140         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
2141         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2142         .flags          = ENABLE_ON_INIT,
2143         .clkdm_name     = "l3_emif_clkdm",
2144 };
2145
2146 static struct clk emif2_fck = {
2147         .name           = "emif2_fck",
2148         .ops            = &leaf_ck_ops,
2149         .hw             = &emif2_fck_hw.hw,
2150         .parent_names   = emif2_fck_parent_names,
2151         .num_parents    = ARRAY_SIZE(emif2_fck_parent_names),
2152         };
2153
2154 static const struct clksel fdif_fclk_div[] = {
2155         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
2156         { .parent = NULL },
2157 };
2158
2159 static char *fdif_fck_parents[] = {
2160         "dpll_per_m4x2_ck",
2161 };
2162
2163 /* Merged fdif_fclk into fdif */
2164 static struct clk fdif_fck;
2165
2166 static const struct clk_ops fdif_fck_ops = {
2167         .enable         = &omap2_dflt_clk_enable,
2168         .disable        = &omap2_dflt_clk_disable,
2169         .recalc_rate    = &omap2_clksel_recalc,
2170         .round_rate     = &omap2_clksel_round_rate,
2171         .set_rate       = &omap2_clksel_set_rate,
2172         .init   = &omap2_init_clk_clkdm,
2173 };
2174
2175 static struct clk_hw_omap fdif_fck_hw = {
2176         .hw = {
2177                 .clk = &fdif_fck,
2178         },
2179         .clkdm_name     = "iss_clkdm",
2180         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
2181         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2182         .clksel         = fdif_fclk_div,
2183         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
2184         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
2185 };
2186
2187 static struct clk fdif_fck = {
2188         .name           = "fdif_fck",
2189         .ops            = &fdif_fck_ops,
2190         .hw             = &fdif_fck_hw.hw,
2191         .parent_names = fdif_fck_parents,
2192         .num_parents = ARRAY_SIZE(fdif_fck_parents),
2193 };
2194
2195 static char *fpka_fck_parent_names[] = {
2196         "l4_div_ck",
2197 };
2198
2199 static struct clk fpka_fck;
2200
2201 static struct clk_hw_omap fpka_fck_hw = {
2202         .hw = {
2203                 .clk = &fpka_fck,
2204         },
2205         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2206         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2207         .clkdm_name     = "l4_secure_clkdm",
2208 };
2209
2210 static struct clk fpka_fck = {
2211         .name           = "fpka_fck",
2212         .ops            = &leaf_ck_ops,
2213         .hw             = &fpka_fck_hw.hw,
2214         .parent_names   = fpka_fck_parent_names,
2215         .num_parents    = ARRAY_SIZE(fpka_fck_parent_names),
2216         };
2217
2218 static struct clk gpio1_dbclk;
2219
2220 static char *gpio1_dbclk_parent_names[] = {
2221         "sys_32k_ck",
2222 };
2223
2224 static struct clk_hw_omap gpio1_dbclk_hw = {
2225         .hw = {
2226                 .clk = &gpio1_dbclk,
2227         },
2228         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
2229         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2230         .clkdm_name     = "l4_wkup_clkdm",
2231 };
2232
2233 static struct clk gpio1_dbclk = {
2234         .name           = "gpio1_dbclk",
2235         .ops            = &leaf_ck_ops,
2236         .hw             = &gpio1_dbclk_hw.hw,
2237         .parent_names   = gpio1_dbclk_parent_names,
2238         .num_parents    = ARRAY_SIZE(gpio1_dbclk_parent_names),
2239 };
2240
2241 static char *gpio1_ick_parent_names[] = {
2242         "l4_wkup_clk_mux_ck",
2243 };
2244
2245 static struct clk gpio1_ick;
2246
2247 static struct clk_hw_omap gpio1_ick_hw = {
2248         .hw = {
2249                 .clk = &gpio1_ick,
2250         },
2251         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
2252         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2253         .clkdm_name     = "l4_wkup_clkdm",
2254 };
2255
2256 static struct clk gpio1_ick = {
2257         .name           = "gpio1_ick",
2258         .ops            = &leaf_ck_ops,
2259         .hw             = &gpio1_ick_hw.hw,
2260         .parent_names   = gpio1_ick_parent_names,
2261         .num_parents    = ARRAY_SIZE(gpio1_ick_parent_names),
2262         };
2263
2264 static struct clk gpio2_dbclk;
2265
2266 static char *gpio2_dbclk_parent_names[] = {
2267         "sys_32k_ck",
2268 };
2269
2270 static struct clk_hw_omap gpio2_dbclk_hw = {
2271         .hw = {
2272                 .clk = &gpio2_dbclk,
2273         },
2274         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
2275         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2276         .clkdm_name     = "l4_per_clkdm",
2277 };
2278
2279 static struct clk gpio2_dbclk = {
2280         .name           = "gpio2_dbclk",
2281         .ops            = &leaf_ck_ops,
2282         .hw             = &gpio2_dbclk_hw.hw,
2283         .parent_names   = gpio2_dbclk_parent_names,
2284         .num_parents    = ARRAY_SIZE(gpio2_dbclk_parent_names),
2285 };
2286
2287 static char *gpio2_ick_parent_names[] = {
2288         "l4_div_ck",
2289 };
2290
2291 static struct clk gpio2_ick;
2292
2293 static struct clk_hw_omap gpio2_ick_hw = {
2294         .hw = {
2295                 .clk = &gpio2_ick,
2296         },
2297         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
2298         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2299         .clkdm_name     = "l4_per_clkdm",
2300 };
2301
2302 static struct clk gpio2_ick = {
2303         .name           = "gpio2_ick",
2304         .ops            = &leaf_ck_ops,
2305         .hw             = &gpio2_ick_hw.hw,
2306         .parent_names   = gpio2_ick_parent_names,
2307         .num_parents    = ARRAY_SIZE(gpio2_ick_parent_names),
2308         };
2309
2310 static struct clk gpio3_dbclk;
2311
2312 static char *gpio3_dbclk_parent_names[] = {
2313         "sys_32k_ck",
2314 };
2315
2316 static struct clk_hw_omap gpio3_dbclk_hw = {
2317         .hw = {
2318                 .clk = &gpio3_dbclk,
2319         },
2320         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
2321         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2322         .clkdm_name     = "l4_per_clkdm",
2323 };
2324
2325 static struct clk gpio3_dbclk = {
2326         .name           = "gpio3_dbclk",
2327         .ops            = &leaf_ck_ops,
2328         .hw             = &gpio3_dbclk_hw.hw,
2329         .parent_names   = gpio3_dbclk_parent_names,
2330         .num_parents    = ARRAY_SIZE(gpio3_dbclk_parent_names),
2331 };
2332
2333 static char *gpio3_ick_parent_names[] = {
2334         "l4_div_ck",
2335 };
2336
2337 static struct clk gpio3_ick;
2338
2339 static struct clk_hw_omap gpio3_ick_hw = {
2340         .hw = {
2341                 .clk = &gpio3_ick,
2342         },
2343         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
2344         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2345         .clkdm_name     = "l4_per_clkdm",
2346 };
2347
2348 static struct clk gpio3_ick = {
2349         .name           = "gpio3_ick",
2350         .ops            = &leaf_ck_ops,
2351         .hw             = &gpio3_ick_hw.hw,
2352         .parent_names   = gpio3_ick_parent_names,
2353         .num_parents    = ARRAY_SIZE(gpio3_ick_parent_names),
2354         };
2355
2356 static struct clk gpio4_dbclk;
2357
2358 static char *gpio4_dbclk_parent_names[] = {
2359         "sys_32k_ck",
2360 };
2361
2362 static struct clk_hw_omap gpio4_dbclk_hw = {
2363         .hw = {
2364                 .clk = &gpio4_dbclk,
2365         },
2366         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
2367         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2368         .clkdm_name     = "l4_per_clkdm",
2369 };
2370
2371 static struct clk gpio4_dbclk = {
2372         .name           = "gpio4_dbclk",
2373         .ops            = &leaf_ck_ops,
2374         .hw             = &gpio4_dbclk_hw.hw,
2375         .parent_names   = gpio4_dbclk_parent_names,
2376         .num_parents    = ARRAY_SIZE(gpio4_dbclk_parent_names),
2377 };
2378
2379 static char *gpio4_ick_parent_names[] = {
2380         "l4_div_ck",
2381 };
2382
2383 static struct clk gpio4_ick;
2384
2385 static struct clk_hw_omap gpio4_ick_hw = {
2386         .hw = {
2387                 .clk = &gpio4_ick,
2388         },
2389         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
2390         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2391         .clkdm_name     = "l4_per_clkdm",
2392 };
2393
2394 static struct clk gpio4_ick = {
2395         .name           = "gpio4_ick",
2396         .ops            = &leaf_ck_ops,
2397         .hw             = &gpio4_ick_hw.hw,
2398         .parent_names   = gpio4_ick_parent_names,
2399         .num_parents    = ARRAY_SIZE(gpio4_ick_parent_names),
2400         };
2401
2402 static struct clk gpio5_dbclk;
2403
2404 static char *gpio5_dbclk_parent_names[] = {
2405         "sys_32k_ck",
2406 };
2407
2408 static struct clk_hw_omap gpio5_dbclk_hw = {
2409         .hw = {
2410                 .clk = &gpio5_dbclk,
2411         },
2412         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
2413         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2414         .clkdm_name     = "l4_per_clkdm",
2415 };
2416
2417 static struct clk gpio5_dbclk = {
2418         .name           = "gpio5_dbclk",
2419         .ops            = &leaf_ck_ops,
2420         .hw             = &gpio5_dbclk_hw.hw,
2421         .parent_names   = gpio5_dbclk_parent_names,
2422         .num_parents    = ARRAY_SIZE(gpio5_dbclk_parent_names),
2423 };
2424
2425 static char *gpio5_ick_parent_names[] = {
2426         "l4_div_ck",
2427 };
2428
2429 static struct clk gpio5_ick;
2430
2431 static struct clk_hw_omap gpio5_ick_hw = {
2432         .hw = {
2433                 .clk = &gpio5_ick,
2434         },
2435         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
2436         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2437         .clkdm_name     = "l4_per_clkdm",
2438 };
2439
2440 static struct clk gpio5_ick = {
2441         .name           = "gpio5_ick",
2442         .ops            = &leaf_ck_ops,
2443         .hw             = &gpio5_ick_hw.hw,
2444         .parent_names   = gpio5_ick_parent_names,
2445         .num_parents    = ARRAY_SIZE(gpio5_ick_parent_names),
2446         };
2447
2448 static struct clk gpio6_dbclk;
2449
2450 static char *gpio6_dbclk_parent_names[] = {
2451         "sys_32k_ck",
2452 };
2453
2454 static struct clk_hw_omap gpio6_dbclk_hw = {
2455         .hw = {
2456                 .clk = &gpio6_dbclk,
2457         },
2458         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2459         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
2460         .clkdm_name     = "l4_per_clkdm",
2461 };
2462
2463 static struct clk gpio6_dbclk = {
2464         .name           = "gpio6_dbclk",
2465         .ops            = &leaf_ck_ops,
2466         .hw             = &gpio6_dbclk_hw.hw,
2467         .parent_names   = gpio6_dbclk_parent_names,
2468         .num_parents    = ARRAY_SIZE(gpio6_dbclk_parent_names),
2469 };
2470
2471 static char *gpio6_ick_parent_names[] = {
2472         "l4_div_ck",
2473 };
2474
2475 static struct clk gpio6_ick;
2476
2477 static struct clk_hw_omap gpio6_ick_hw = {
2478         .hw = {
2479                 .clk = &gpio6_ick,
2480         },
2481         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2482         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2483         .clkdm_name     = "l4_per_clkdm",
2484 };
2485
2486 static struct clk gpio6_ick = {
2487         .name           = "gpio6_ick",
2488         .ops            = &leaf_ck_ops,
2489         .hw             = &gpio6_ick_hw.hw,
2490         .parent_names   = gpio6_ick_parent_names,
2491         .num_parents    = ARRAY_SIZE(gpio6_ick_parent_names),
2492         };
2493
2494 static char *gpmc_ick_parent_names[] = {
2495         "l3_div_ck",
2496 };
2497
2498 static struct clk gpmc_ick;
2499
2500 static struct clk_hw_omap gpmc_ick_hw = {
2501         .hw = {
2502                 .clk = &gpmc_ick,
2503         },
2504         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
2505         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2506         .flags          = ENABLE_ON_INIT,
2507         .clkdm_name     = "l3_2_clkdm",
2508 };
2509
2510 static struct clk gpmc_ick = {
2511         .name           = "gpmc_ick",
2512         .ops            = &leaf_ck_ops,
2513         .hw             = &gpmc_ick_hw.hw,
2514         .parent_names   = gpmc_ick_parent_names,
2515         .num_parents    = ARRAY_SIZE(gpmc_ick_parent_names),
2516         };
2517
2518 static const struct clksel sgx_clk_mux_sel[] = {
2519         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
2520         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
2521         { .parent = NULL },
2522 };
2523
2524 static char *gpu_fck_parents[] = {
2525         "dpll_core_m7x2_ck",
2526         "dpll_per_m7x2_ck",
2527 };
2528
2529 /* Merged sgx_clk_mux into gpu */
2530 static struct clk gpu_fck;
2531
2532 static const struct clk_ops gpu_fck_ops = {
2533         .enable         = &omap2_dflt_clk_enable,
2534         .disable        = &omap2_dflt_clk_disable,
2535         .recalc_rate    = &omap2_clksel_recalc,
2536         .get_parent     = &omap2_init_clksel_parent,
2537         .set_parent     = &omap2_clksel_set_parent,
2538         .init   = &omap2_init_clk_clkdm,
2539 };
2540
2541 static struct clk_hw_omap gpu_fck_hw = {
2542         .hw = {
2543                 .clk = &gpu_fck,
2544         },
2545         .clkdm_name     = "l3_gfx_clkdm",
2546         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
2547         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2548         .clksel         = sgx_clk_mux_sel,
2549         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
2550         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
2551 };
2552
2553 static struct clk gpu_fck = {
2554         .name           = "gpu_fck",
2555         .ops            = &gpu_fck_ops,
2556         .hw             = &gpu_fck_hw.hw,
2557         .parent_names = gpu_fck_parents,
2558         .num_parents = ARRAY_SIZE(gpu_fck_parents),
2559 };
2560
2561 static char *hdq1w_fck_parent_names[] = {
2562         "func_12m_fclk",
2563 };
2564
2565 static struct clk hdq1w_fck;
2566
2567 static struct clk_hw_omap hdq1w_fck_hw = {
2568         .hw = {
2569                 .clk = &hdq1w_fck,
2570         },
2571         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
2572         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2573         .clkdm_name     = "l4_per_clkdm",
2574 };
2575
2576 static struct clk hdq1w_fck = {
2577         .name           = "hdq1w_fck",
2578         .ops            = &leaf_ck_ops,
2579         .hw             = &hdq1w_fck_hw.hw,
2580         .parent_names   = hdq1w_fck_parent_names,
2581         .num_parents    = ARRAY_SIZE(hdq1w_fck_parent_names),
2582         };
2583
2584 static const struct clksel hsi_fclk_div[] = {
2585         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
2586         { .parent = NULL },
2587 };
2588
2589 static char *hsi_fck_parents[] = {
2590         "dpll_per_m2x2_ck",
2591 };
2592
2593 /* Merged hsi_fclk into hsi */
2594 static struct clk hsi_fck;
2595
2596 static const struct clk_ops hsi_fck_ops = {
2597         .enable         = &omap2_dflt_clk_enable,
2598         .disable        = &omap2_dflt_clk_disable,
2599         .recalc_rate    = &omap2_clksel_recalc,
2600         .round_rate     = &omap2_clksel_round_rate,
2601         .set_rate       = &omap2_clksel_set_rate,
2602         .init   = &omap2_init_clk_clkdm,
2603 };
2604
2605 static struct clk_hw_omap hsi_fck_hw = {
2606         .hw = {
2607                 .clk = &hsi_fck,
2608         },
2609         .clkdm_name     = "l3_init_clkdm",
2610         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2611         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2612         .clksel         = hsi_fclk_div,
2613         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2614         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
2615 };
2616
2617 static struct clk hsi_fck = {
2618         .name           = "hsi_fck",
2619         .ops            = &hsi_fck_ops,
2620         .hw             = &hsi_fck_hw.hw,
2621         .parent_names = hsi_fck_parents,
2622         .num_parents = ARRAY_SIZE(hsi_fck_parents),
2623 };
2624
2625 static char *i2c1_fck_parent_names[] = {
2626         "func_96m_fclk",
2627 };
2628
2629 static struct clk i2c1_fck;
2630
2631 static struct clk_hw_omap i2c1_fck_hw = {
2632         .hw = {
2633                 .clk = &i2c1_fck,
2634         },
2635         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2636         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2637         .clkdm_name     = "l4_per_clkdm",
2638 };
2639
2640 static struct clk i2c1_fck = {
2641         .name           = "i2c1_fck",
2642         .ops            = &leaf_ck_ops,
2643         .hw             = &i2c1_fck_hw.hw,
2644         .parent_names   = i2c1_fck_parent_names,
2645         .num_parents    = ARRAY_SIZE(i2c1_fck_parent_names),
2646         };
2647
2648 static char *i2c2_fck_parent_names[] = {
2649         "func_96m_fclk",
2650 };
2651
2652 static struct clk i2c2_fck;
2653
2654 static struct clk_hw_omap i2c2_fck_hw = {
2655         .hw = {
2656                 .clk = &i2c2_fck,
2657         },
2658         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2659         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2660         .clkdm_name     = "l4_per_clkdm",
2661 };
2662
2663 static struct clk i2c2_fck = {
2664         .name           = "i2c2_fck",
2665         .ops            = &leaf_ck_ops,
2666         .hw             = &i2c2_fck_hw.hw,
2667         .parent_names   = i2c2_fck_parent_names,
2668         .num_parents    = ARRAY_SIZE(i2c2_fck_parent_names),
2669         };
2670
2671 static char *i2c3_fck_parent_names[] = {
2672         "func_96m_fclk",
2673 };
2674
2675 static struct clk i2c3_fck;
2676
2677 static struct clk_hw_omap i2c3_fck_hw = {
2678         .hw = {
2679                 .clk = &i2c3_fck,
2680         },
2681         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2682         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2683         .clkdm_name     = "l4_per_clkdm",
2684 };
2685
2686 static struct clk i2c3_fck = {
2687         .name           = "i2c3_fck",
2688         .ops            = &leaf_ck_ops,
2689         .hw             = &i2c3_fck_hw.hw,
2690         .parent_names   = i2c3_fck_parent_names,
2691         .num_parents    = ARRAY_SIZE(i2c3_fck_parent_names),
2692         };
2693
2694 static char *i2c4_fck_parent_names[] = {
2695         "func_96m_fclk",
2696 };
2697
2698 static struct clk i2c4_fck;
2699
2700 static struct clk_hw_omap i2c4_fck_hw = {
2701         .hw = {
2702                 .clk = &i2c4_fck,
2703         },
2704         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2705         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2706         .clkdm_name     = "l4_per_clkdm",
2707 };
2708
2709 static struct clk i2c4_fck = {
2710         .name           = "i2c4_fck",
2711         .ops            = &leaf_ck_ops,
2712         .hw             = &i2c4_fck_hw.hw,
2713         .parent_names   = i2c4_fck_parent_names,
2714         .num_parents    = ARRAY_SIZE(i2c4_fck_parent_names),
2715         };
2716
2717 static char *ipu_fck_parent_names[] = {
2718         "ducati_clk_mux_ck",
2719 };
2720
2721 static struct clk ipu_fck;
2722
2723 static struct clk_hw_omap ipu_fck_hw = {
2724         .hw = {
2725                 .clk = &ipu_fck,
2726         },
2727         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2728         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2729         .clkdm_name     = "ducati_clkdm",
2730 };
2731
2732 static struct clk ipu_fck = {
2733         .name           = "ipu_fck",
2734         .ops            = &leaf_ck_ops,
2735         .hw             = &ipu_fck_hw.hw,
2736         .parent_names   = ipu_fck_parent_names,
2737         .num_parents    = ARRAY_SIZE(ipu_fck_parent_names),
2738         };
2739
2740 static struct clk iss_ctrlclk;
2741
2742 static char *iss_ctrlclk_parent_names[] = {
2743         "func_96m_fclk",
2744 };
2745
2746 static struct clk_hw_omap iss_ctrlclk_hw = {
2747         .hw = {
2748                 .clk = &iss_ctrlclk,
2749         },
2750         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
2751         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
2752         .clkdm_name     = "iss_clkdm",
2753 };
2754
2755 static struct clk iss_ctrlclk = {
2756         .name           = "iss_ctrlclk",
2757         .ops            = &leaf_ck_ops,
2758         .hw             = &iss_ctrlclk_hw.hw,
2759         .parent_names   = iss_ctrlclk_parent_names,
2760         .num_parents    = ARRAY_SIZE(iss_ctrlclk_parent_names),
2761 };
2762
2763 static char *iss_fck_parent_names[] = {
2764         "ducati_clk_mux_ck",
2765 };
2766
2767 static struct clk iss_fck;
2768
2769 static struct clk_hw_omap iss_fck_hw = {
2770         .hw = {
2771                 .clk = &iss_fck,
2772         },
2773         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
2774         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2775         .clkdm_name     = "iss_clkdm",
2776 };
2777
2778 static struct clk iss_fck = {
2779         .name           = "iss_fck",
2780         .ops            = &leaf_ck_ops,
2781         .hw             = &iss_fck_hw.hw,
2782         .parent_names   = iss_fck_parent_names,
2783         .num_parents    = ARRAY_SIZE(iss_fck_parent_names),
2784         };
2785
2786 static char *iva_fck_parent_names[] = {
2787         "dpll_iva_m5x2_ck",
2788 };
2789
2790 static struct clk iva_fck;
2791
2792 static struct clk_hw_omap iva_fck_hw = {
2793         .hw = {
2794                 .clk = &iva_fck,
2795         },
2796         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2797         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2798         .clkdm_name     = "ivahd_clkdm",
2799 };
2800
2801 static struct clk iva_fck = {
2802         .name           = "iva_fck",
2803         .ops            = &leaf_ck_ops,
2804         .hw             = &iva_fck_hw.hw,
2805         .parent_names   = iva_fck_parent_names,
2806         .num_parents    = ARRAY_SIZE(iva_fck_parent_names),
2807         };
2808
2809 static char *kbd_fck_parent_names[] = {
2810         "sys_32k_ck",
2811 };
2812
2813 static struct clk kbd_fck;
2814
2815 static struct clk_hw_omap kbd_fck_hw = {
2816         .hw = {
2817                 .clk = &kbd_fck,
2818         },
2819         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2820         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2821         .clkdm_name     = "l4_wkup_clkdm",
2822 };
2823
2824 static struct clk kbd_fck = {
2825         .name           = "kbd_fck",
2826         .ops            = &leaf_ck_ops,
2827         .hw             = &kbd_fck_hw.hw,
2828         .parent_names   = kbd_fck_parent_names,
2829         .num_parents    = ARRAY_SIZE(kbd_fck_parent_names),
2830         };
2831
2832 static char *l3_instr_ick_parent_names[] = {
2833         "l3_div_ck",
2834 };
2835
2836 static struct clk l3_instr_ick;
2837
2838 static struct clk_hw_omap l3_instr_ick_hw = {
2839         .hw = {
2840                 .clk = &l3_instr_ick,
2841         },
2842         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
2843         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2844         .flags          = ENABLE_ON_INIT,
2845         .clkdm_name     = "l3_instr_clkdm",
2846 };
2847
2848 static struct clk l3_instr_ick = {
2849         .name           = "l3_instr_ick",
2850         .ops            = &leaf_ck_ops,
2851         .hw             = &l3_instr_ick_hw.hw,
2852         .parent_names   = l3_instr_ick_parent_names,
2853         .num_parents    = ARRAY_SIZE(l3_instr_ick_parent_names),
2854         };
2855
2856 static char *l3_main_3_ick_parent_names[] = {
2857         "l3_div_ck",
2858 };
2859
2860 static struct clk l3_main_3_ick;
2861
2862 static struct clk_hw_omap l3_main_3_ick_hw = {
2863         .hw = {
2864                 .clk = &l3_main_3_ick,
2865         },
2866         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
2867         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
2868         .flags          = ENABLE_ON_INIT,
2869         .clkdm_name     = "l3_instr_clkdm",
2870 };
2871
2872 static struct clk l3_main_3_ick = {
2873         .name           = "l3_main_3_ick",
2874         .ops            = &leaf_ck_ops,
2875         .hw             = &l3_main_3_ick_hw.hw,
2876         .parent_names   = l3_main_3_ick_parent_names,
2877         .num_parents    = ARRAY_SIZE(l3_main_3_ick_parent_names),
2878         };
2879
2880 static char *mcasp_sync_mux_ck_parent_names[] = {
2881         "abe_24m_fclk",
2882         "syc_clk_div_ck",
2883         "func_24m_clk",
2884 };
2885
2886 static struct clk *mcasp_sync_mux_ck_parents[] = {
2887         &abe_24m_fclk,
2888         &syc_clk_div_ck,
2889         &func_24m_clk,
2890 };
2891
2892 DEFINE_CLK_MUX(mcasp_sync_mux_ck,
2893         mcasp_sync_mux_ck_parent_names,
2894         mcasp_sync_mux_ck_parents,
2895         0x0,
2896         OMAP4430_CM1_ABE_MCASP_CLKCTRL,
2897         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
2898         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
2899         0x0,
2900         NULL);
2901
2902 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
2903         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
2904         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2905         { .parent = &slimbus_clk, .rates = div_1_2_rates },
2906         { .parent = NULL },
2907 };
2908
2909 static char *mcasp_fck_parents[] = {
2910         "mcasp_sync_mux_ck",
2911         "pad_clks_ck",
2912         "slimbus_clk",
2913 };
2914
2915 /* Merged func_mcasp_abe_gfclk into mcasp */
2916 static struct clk mcasp_fck;
2917
2918 static const struct clk_ops mcasp_fck_ops = {
2919         .enable         = &omap2_dflt_clk_enable,
2920         .disable        = &omap2_dflt_clk_disable,
2921         .recalc_rate    = &omap2_clksel_recalc,
2922         .get_parent     = &omap2_init_clksel_parent,
2923         .set_parent     = &omap2_clksel_set_parent,
2924         .init   = &omap2_init_clk_clkdm,
2925 };
2926
2927 static struct clk_hw_omap mcasp_fck_hw = {
2928         .hw = {
2929                 .clk = &mcasp_fck,
2930         },
2931         .clkdm_name     = "abe_clkdm",
2932         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
2933         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
2934         .clksel         = func_mcasp_abe_gfclk_sel,
2935         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
2936         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
2937 };
2938
2939 static struct clk mcasp_fck = {
2940         .name           = "mcasp_fck",
2941         .ops            = &mcasp_fck_ops,
2942         .hw             = &mcasp_fck_hw.hw,
2943         .parent_names = mcasp_fck_parents,
2944         .num_parents = ARRAY_SIZE(mcasp_fck_parents),
2945 };
2946
2947 static char *mcbsp1_sync_mux_ck_parent_names[] = {
2948         "abe_24m_fclk",
2949         "syc_clk_div_ck",
2950         "func_24m_clk",
2951 };
2952
2953 static struct clk *mcbsp1_sync_mux_ck_parents[] = {
2954         &abe_24m_fclk,
2955         &syc_clk_div_ck,
2956         &func_24m_clk,
2957 };
2958
2959 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck,
2960         mcbsp1_sync_mux_ck_parent_names,
2961         mcbsp1_sync_mux_ck_parents,
2962         0x0,
2963         OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2964         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
2965         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
2966         0x0,
2967         NULL);
2968
2969 static const struct clksel func_mcbsp1_gfclk_sel[] = {
2970         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
2971         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2972         { .parent = &slimbus_clk, .rates = div_1_2_rates },
2973         { .parent = NULL },
2974 };
2975
2976 static char *mcbsp1_fck_parents[] = {
2977         "mcbsp1_sync_mux_ck",
2978         "pad_clks_ck",
2979         "slimbus_clk",
2980 };
2981
2982 /* Merged func_mcbsp1_gfclk into mcbsp1 */
2983 static struct clk mcbsp1_fck;
2984
2985 static const struct clk_ops mcbsp1_fck_ops = {
2986         .enable         = &omap2_dflt_clk_enable,
2987         .disable        = &omap2_dflt_clk_disable,
2988         .recalc_rate    = &omap2_clksel_recalc,
2989         .get_parent     = &omap2_init_clksel_parent,
2990         .set_parent     = &omap2_clksel_set_parent,
2991         .init   = &omap2_init_clk_clkdm,
2992 };
2993
2994 static struct clk_hw_omap mcbsp1_fck_hw = {
2995         .hw = {
2996                 .clk = &mcbsp1_fck,
2997         },
2998         .clkdm_name     = "abe_clkdm",
2999         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
3000         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3001         .clksel         = func_mcbsp1_gfclk_sel,
3002         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
3003         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
3004 };
3005
3006 static struct clk mcbsp1_fck = {
3007         .name           = "mcbsp1_fck",
3008         .ops            = &mcbsp1_fck_ops,
3009         .hw             = &mcbsp1_fck_hw.hw,
3010         .parent_names = mcbsp1_fck_parents,
3011         .num_parents = ARRAY_SIZE(mcbsp1_fck_parents),
3012 };
3013
3014 static char *mcbsp2_sync_mux_ck_parent_names[] = {
3015         "abe_24m_fclk",
3016         "syc_clk_div_ck",
3017         "func_24m_clk",
3018 };
3019
3020 static struct clk *mcbsp2_sync_mux_ck_parents[] = {
3021         &abe_24m_fclk,
3022         &syc_clk_div_ck,
3023         &func_24m_clk,
3024 };
3025
3026 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck,
3027         mcbsp2_sync_mux_ck_parent_names,
3028         mcbsp2_sync_mux_ck_parents,
3029         0x0,
3030         OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
3031         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
3032         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
3033         0x0,
3034         NULL);
3035
3036 static const struct clksel func_mcbsp2_gfclk_sel[] = {
3037         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
3038         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
3039         { .parent = &slimbus_clk, .rates = div_1_2_rates },
3040         { .parent = NULL },
3041 };
3042
3043 static char *mcbsp2_fck_parents[] = {
3044         "mcbsp2_sync_mux_ck",
3045         "pad_clks_ck",
3046         "slimbus_clk",
3047 };
3048
3049 /* Merged func_mcbsp2_gfclk into mcbsp2 */
3050 static struct clk mcbsp2_fck;
3051
3052 static const struct clk_ops mcbsp2_fck_ops = {
3053         .enable         = &omap2_dflt_clk_enable,
3054         .disable        = &omap2_dflt_clk_disable,
3055         .recalc_rate    = &omap2_clksel_recalc,
3056         .get_parent     = &omap2_init_clksel_parent,
3057         .set_parent     = &omap2_clksel_set_parent,
3058         .init   = &omap2_init_clk_clkdm,
3059 };
3060
3061 static struct clk_hw_omap mcbsp2_fck_hw = {
3062         .hw = {
3063                 .clk = &mcbsp2_fck,
3064         },
3065         .clkdm_name     = "abe_clkdm",
3066         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
3067         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3068         .clksel         = func_mcbsp2_gfclk_sel,
3069         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
3070         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
3071 };
3072
3073 static struct clk mcbsp2_fck = {
3074         .name           = "mcbsp2_fck",
3075         .ops            = &mcbsp2_fck_ops,
3076         .hw             = &mcbsp2_fck_hw.hw,
3077         .parent_names = mcbsp2_fck_parents,
3078         .num_parents = ARRAY_SIZE(mcbsp2_fck_parents),
3079 };
3080
3081 static char *mcbsp3_sync_mux_ck_parent_names[] = {
3082         "abe_24m_fclk",
3083         "syc_clk_div_ck",
3084         "func_24m_clk",
3085 };
3086
3087 static struct clk *mcbsp3_sync_mux_ck_parents[] = {
3088         &abe_24m_fclk,
3089         &syc_clk_div_ck,
3090         &func_24m_clk,
3091 };
3092
3093 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck,
3094         mcbsp3_sync_mux_ck_parent_names,
3095         mcbsp3_sync_mux_ck_parents,
3096         0x0,
3097         OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3098         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
3099         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
3100         0x0,
3101         NULL);
3102
3103 static const struct clksel func_mcbsp3_gfclk_sel[] = {
3104         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
3105         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
3106         { .parent = &slimbus_clk, .rates = div_1_2_rates },
3107         { .parent = NULL },
3108 };
3109
3110 static char *mcbsp3_fck_parents[] = {
3111         "mcbsp3_sync_mux_ck",
3112         "pad_clks_ck",
3113         "slimbus_clk",
3114 };
3115
3116 /* Merged func_mcbsp3_gfclk into mcbsp3 */
3117 static struct clk mcbsp3_fck;
3118
3119 static const struct clk_ops mcbsp3_fck_ops = {
3120         .enable         = &omap2_dflt_clk_enable,
3121         .disable        = &omap2_dflt_clk_disable,
3122         .recalc_rate    = &omap2_clksel_recalc,
3123         .get_parent     = &omap2_init_clksel_parent,
3124         .set_parent     = &omap2_clksel_set_parent,
3125         .init   = &omap2_init_clk_clkdm,
3126 };
3127
3128 static struct clk_hw_omap mcbsp3_fck_hw = {
3129         .hw = {
3130                 .clk = &mcbsp3_fck,
3131         },
3132         .clkdm_name     = "abe_clkdm",
3133         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3134         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3135         .clksel         = func_mcbsp3_gfclk_sel,
3136         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3137         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
3138 };
3139
3140 static struct clk mcbsp3_fck = {
3141         .name           = "mcbsp3_fck",
3142         .ops            = &mcbsp3_fck_ops,
3143         .hw             = &mcbsp3_fck_hw.hw,
3144         .parent_names = mcbsp3_fck_parents,
3145         .num_parents = ARRAY_SIZE(mcbsp3_fck_parents),
3146 };
3147
3148 static char *mcbsp4_sync_mux_ck_parent_names[] = {
3149         "func_96m_fclk",
3150         "per_abe_nc_fclk",
3151 };
3152
3153 static struct clk *mcbsp4_sync_mux_ck_parents[] = {
3154         &func_96m_fclk,
3155         &per_abe_nc_fclk,
3156 };
3157
3158 DEFINE_CLK_MUX(mcbsp4_sync_mux_ck,
3159         mcbsp4_sync_mux_ck_parent_names,
3160         mcbsp4_sync_mux_ck_parents,
3161         0x0,
3162         OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3163         OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
3164         OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH,
3165         0x0,
3166         NULL);
3167
3168 static const struct clksel per_mcbsp4_gfclk_sel[] = {
3169         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
3170         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
3171         { .parent = NULL },
3172 };
3173
3174 static char *mcbsp4_fck_parents[] = {
3175         "mcbsp4_sync_mux_ck",
3176         "pad_clks_ck",
3177 };
3178
3179 /* Merged per_mcbsp4_gfclk into mcbsp4 */
3180 static struct clk mcbsp4_fck;
3181
3182 static const struct clk_ops mcbsp4_fck_ops = {
3183         .enable         = &omap2_dflt_clk_enable,
3184         .disable        = &omap2_dflt_clk_disable,
3185         .recalc_rate    = &omap2_clksel_recalc,
3186         .get_parent     = &omap2_init_clksel_parent,
3187         .set_parent     = &omap2_clksel_set_parent,
3188         .init   = &omap2_init_clk_clkdm,
3189 };
3190
3191 static struct clk_hw_omap mcbsp4_fck_hw = {
3192         .hw = {
3193                 .clk = &mcbsp4_fck,
3194         },
3195         .clkdm_name     = "l4_per_clkdm",
3196         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3197         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3198         .clksel         = per_mcbsp4_gfclk_sel,
3199         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3200         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
3201 };
3202
3203 static struct clk mcbsp4_fck = {
3204         .name           = "mcbsp4_fck",
3205         .ops            = &mcbsp4_fck_ops,
3206         .hw             = &mcbsp4_fck_hw.hw,
3207         .parent_names = mcbsp4_fck_parents,
3208         .num_parents = ARRAY_SIZE(mcbsp4_fck_parents),
3209 };
3210
3211 static char *mcpdm_fck_parent_names[] = {
3212         "pad_clks_ck",
3213 };
3214
3215 static struct clk mcpdm_fck;
3216
3217 static struct clk_hw_omap mcpdm_fck_hw = {
3218         .hw = {
3219                 .clk = &mcpdm_fck,
3220         },
3221         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3222         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3223         .clkdm_name     = "abe_clkdm",
3224 };
3225
3226 static struct clk mcpdm_fck = {
3227         .name           = "mcpdm_fck",
3228         .ops            = &leaf_ck_ops,
3229         .hw             = &mcpdm_fck_hw.hw,
3230         .parent_names   = mcpdm_fck_parent_names,
3231         .num_parents    = ARRAY_SIZE(mcpdm_fck_parent_names),
3232         };
3233
3234 static char *mcspi1_fck_parent_names[] = {
3235         "func_48m_fclk",
3236 };
3237
3238 static struct clk mcspi1_fck;
3239
3240 static struct clk_hw_omap mcspi1_fck_hw = {
3241         .hw = {
3242                 .clk = &mcspi1_fck,
3243         },
3244         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3245         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3246         .clkdm_name     = "l4_per_clkdm",
3247 };
3248
3249 static struct clk mcspi1_fck = {
3250         .name           = "mcspi1_fck",
3251         .ops            = &leaf_ck_ops,
3252         .hw             = &mcspi1_fck_hw.hw,
3253         .parent_names   = mcspi1_fck_parent_names,
3254         .num_parents    = ARRAY_SIZE(mcspi1_fck_parent_names),
3255         };
3256
3257 static char *mcspi2_fck_parent_names[] = {
3258         "func_48m_fclk",
3259 };
3260
3261 static struct clk mcspi2_fck;
3262
3263 static struct clk_hw_omap mcspi2_fck_hw = {
3264         .hw = {
3265                 .clk = &mcspi2_fck,
3266         },
3267         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3268         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3269         .clkdm_name     = "l4_per_clkdm",
3270 };
3271
3272 static struct clk mcspi2_fck = {
3273         .name           = "mcspi2_fck",
3274         .ops            = &leaf_ck_ops,
3275         .hw             = &mcspi2_fck_hw.hw,
3276         .parent_names   = mcspi2_fck_parent_names,
3277         .num_parents    = ARRAY_SIZE(mcspi2_fck_parent_names),
3278         };
3279
3280 static char *mcspi3_fck_parent_names[] = {
3281         "func_48m_fclk",
3282 };
3283
3284 static struct clk mcspi3_fck;
3285
3286 static struct clk_hw_omap mcspi3_fck_hw = {
3287         .hw = {
3288                 .clk = &mcspi3_fck,
3289         },
3290         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3291         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3292         .clkdm_name     = "l4_per_clkdm",
3293 };
3294
3295 static struct clk mcspi3_fck = {
3296         .name           = "mcspi3_fck",
3297         .ops            = &leaf_ck_ops,
3298         .hw             = &mcspi3_fck_hw.hw,
3299         .parent_names   = mcspi3_fck_parent_names,
3300         .num_parents    = ARRAY_SIZE(mcspi3_fck_parent_names),
3301         };
3302
3303 static char *mcspi4_fck_parent_names[] = {
3304         "func_48m_fclk",
3305 };
3306
3307 static struct clk mcspi4_fck;
3308
3309 static struct clk_hw_omap mcspi4_fck_hw = {
3310         .hw = {
3311                 .clk = &mcspi4_fck,
3312         },
3313         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3314         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3315         .clkdm_name     = "l4_per_clkdm",
3316 };
3317
3318 static struct clk mcspi4_fck = {
3319         .name           = "mcspi4_fck",
3320         .ops            = &leaf_ck_ops,
3321         .hw             = &mcspi4_fck_hw.hw,
3322         .parent_names   = mcspi4_fck_parent_names,
3323         .num_parents    = ARRAY_SIZE(mcspi4_fck_parent_names),
3324         };
3325
3326 static const struct clksel hsmmc1_fclk_sel[] = {
3327         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
3328         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
3329         { .parent = NULL },
3330 };
3331
3332 static char *mmc1_fck_parents[] = {
3333         "func_64m_fclk",
3334         "func_96m_fclk",
3335 };
3336
3337 /* Merged hsmmc1_fclk into mmc1 */
3338 static struct clk mmc1_fck;
3339
3340 static const struct clk_ops mmc1_fck_ops = {
3341         .enable         = &omap2_dflt_clk_enable,
3342         .disable        = &omap2_dflt_clk_disable,
3343         .recalc_rate    = &omap2_clksel_recalc,
3344         .get_parent     = &omap2_init_clksel_parent,
3345         .set_parent     = &omap2_clksel_set_parent,
3346         .init   = &omap2_init_clk_clkdm,
3347 };
3348
3349 static struct clk_hw_omap mmc1_fck_hw = {
3350         .hw = {
3351                 .clk = &mmc1_fck,
3352         },
3353         .clkdm_name     = "l3_init_clkdm",
3354         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3355         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3356         .clksel         = hsmmc1_fclk_sel,
3357         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3358         .clksel_mask    = OMAP4430_CLKSEL_MASK,
3359 };
3360
3361 static struct clk mmc1_fck = {
3362         .name           = "mmc1_fck",
3363         .ops            = &mmc1_fck_ops,
3364         .hw             = &mmc1_fck_hw.hw,
3365         .parent_names = mmc1_fck_parents,
3366         .num_parents = ARRAY_SIZE(mmc1_fck_parents),
3367 };
3368
3369 static char *mmc2_fck_parents[] = {
3370         "func_64m_fclk",
3371         "func_96m_fclk",
3372 };
3373
3374 /* Merged hsmmc2_fclk into mmc2 */
3375 static struct clk mmc2_fck;
3376
3377 static const struct clk_ops mmc2_fck_ops = {
3378         .enable         = &omap2_dflt_clk_enable,
3379         .disable        = &omap2_dflt_clk_disable,
3380         .recalc_rate    = &omap2_clksel_recalc,
3381         .get_parent     = &omap2_init_clksel_parent,
3382         .set_parent     = &omap2_clksel_set_parent,
3383         .init   = &omap2_init_clk_clkdm,
3384 };
3385
3386 static struct clk_hw_omap mmc2_fck_hw = {
3387         .hw = {
3388                 .clk = &mmc2_fck,
3389         },
3390         .clkdm_name     = "l3_init_clkdm",
3391         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3392         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3393         .clksel         = hsmmc1_fclk_sel,
3394         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3395         .clksel_mask    = OMAP4430_CLKSEL_MASK,
3396 };
3397
3398 static struct clk mmc2_fck = {
3399         .name           = "mmc2_fck",
3400         .ops            = &mmc2_fck_ops,
3401         .hw             = &mmc2_fck_hw.hw,
3402         .parent_names = mmc2_fck_parents,
3403         .num_parents = ARRAY_SIZE(mmc2_fck_parents),
3404 };
3405
3406 static char *mmc3_fck_parent_names[] = {
3407         "func_48m_fclk",
3408 };
3409
3410 static struct clk mmc3_fck;
3411
3412 static struct clk_hw_omap mmc3_fck_hw = {
3413         .hw = {
3414                 .clk = &mmc3_fck,
3415         },
3416         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3417         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3418         .clkdm_name     = "l4_per_clkdm",
3419 };
3420
3421 static struct clk mmc3_fck = {
3422         .name           = "mmc3_fck",
3423         .ops            = &leaf_ck_ops,
3424         .hw             = &mmc3_fck_hw.hw,
3425         .parent_names   = mmc3_fck_parent_names,
3426         .num_parents    = ARRAY_SIZE(mmc3_fck_parent_names),
3427         };
3428
3429 static char *mmc4_fck_parent_names[] = {
3430         "func_48m_fclk",
3431 };
3432
3433 static struct clk mmc4_fck;
3434
3435 static struct clk_hw_omap mmc4_fck_hw = {
3436         .hw = {
3437                 .clk = &mmc4_fck,
3438         },
3439         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3440         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3441         .clkdm_name     = "l4_per_clkdm",
3442 };
3443
3444 static struct clk mmc4_fck = {
3445         .name           = "mmc4_fck",
3446         .ops            = &leaf_ck_ops,
3447         .hw             = &mmc4_fck_hw.hw,
3448         .parent_names   = mmc4_fck_parent_names,
3449         .num_parents    = ARRAY_SIZE(mmc4_fck_parent_names),
3450         };
3451
3452 static char *mmc5_fck_parent_names[] = {
3453         "func_48m_fclk",
3454 };
3455
3456 static struct clk mmc5_fck;
3457
3458 static struct clk_hw_omap mmc5_fck_hw = {
3459         .hw = {
3460                 .clk = &mmc5_fck,
3461         },
3462         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3463         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
3464         .clkdm_name     = "l4_per_clkdm",
3465 };
3466
3467 static struct clk mmc5_fck = {
3468         .name           = "mmc5_fck",
3469         .ops            = &leaf_ck_ops,
3470         .hw             = &mmc5_fck_hw.hw,
3471         .parent_names   = mmc5_fck_parent_names,
3472         .num_parents    = ARRAY_SIZE(mmc5_fck_parent_names),
3473         };
3474
3475 static struct clk ocp2scp_usb_phy_phy_48m;
3476
3477 static char *ocp2scp_usb_phy_phy_48m_parent_names[] = {
3478         "func_48m_fclk",
3479 };
3480
3481 static struct clk_hw_omap ocp2scp_usb_phy_phy_48m_hw = {
3482         .hw = {
3483                 .clk = &ocp2scp_usb_phy_phy_48m,
3484         },
3485         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
3486         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
3487         .clkdm_name     = "l3_init_clkdm",
3488 };
3489
3490 static struct clk ocp2scp_usb_phy_phy_48m = {
3491         .name           = "ocp2scp_usb_phy_phy_48m",
3492         .ops            = &leaf_ck_ops,
3493         .hw             = &ocp2scp_usb_phy_phy_48m_hw.hw,
3494         .parent_names   = ocp2scp_usb_phy_phy_48m_parent_names,
3495         .num_parents    = ARRAY_SIZE(ocp2scp_usb_phy_phy_48m_parent_names),
3496 };
3497
3498 static char *ocp2scp_usb_phy_ick_parent_names[] = {
3499         "l4_div_ck",
3500 };
3501
3502 static struct clk ocp2scp_usb_phy_ick;
3503
3504 static struct clk_hw_omap ocp2scp_usb_phy_ick_hw = {
3505         .hw = {
3506                 .clk = &ocp2scp_usb_phy_ick,
3507         },
3508         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
3509         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
3510         .clkdm_name     = "l3_init_clkdm",
3511 };
3512
3513 static struct clk ocp2scp_usb_phy_ick = {
3514         .name           = "ocp2scp_usb_phy_ick",
3515         .ops            = &leaf_ck_ops,
3516         .hw             = &ocp2scp_usb_phy_ick_hw.hw,
3517         .parent_names   = ocp2scp_usb_phy_ick_parent_names,
3518         .num_parents    = ARRAY_SIZE(ocp2scp_usb_phy_ick_parent_names),
3519         };
3520
3521 static char *ocp_wp_noc_ick_parent_names[] = {
3522         "l3_div_ck",
3523 };
3524
3525 static struct clk ocp_wp_noc_ick;
3526
3527 static struct clk_hw_omap ocp_wp_noc_ick_hw = {
3528         .hw = {
3529                 .clk = &ocp_wp_noc_ick,
3530         },