diff options
| author | WenHai Fang <wenhai.h.fang@stericsson.com> | 2011-04-04 13:05:19 +0200 |
|---|---|---|
| committer | Michael BRANDT <michael.brandt@stericsson.com> | 2011-04-04 15:54:54 +0200 |
| commit | a67c031d51b8881f1021275e46571fc4a34b1860 (patch) | |
| tree | 24abb8fec074ffc21b548f3eaacaa83890b1043c | |
| parent | 2f99a160060654d34c9914dd8b5a38a8c69e220d (diff) | |
db8500: Fix I2CCLK Info
Fix i2cclk information
ST-Ericsson ID: ER330102
Signed-off-by: WenHai Fang <wenhai.h.fang@stericsson.com>
Change-Id: Id0f2f872f49a0a44cbfcd574a828bc0b281d618d
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/19867
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Reviewed-by: QATOOLS
| -rw-r--r-- | cpu/arm_cortexa9/db8500/clock.c | 47 |
1 files changed, 26 insertions, 21 deletions
diff --git a/cpu/arm_cortexa9/db8500/clock.c b/cpu/arm_cortexa9/db8500/clock.c index 7e8be8e7a..073676130 100644 --- a/cpu/arm_cortexa9/db8500/clock.c +++ b/cpu/arm_cortexa9/db8500/clock.c @@ -51,29 +51,27 @@ static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */ static struct clk_mgt_regs { uint32_t addr; - uint32_t val; const char *descr; } clk_mgt_regs[] = { - /* register content taken from bootrom settings */ - {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */ - {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */ - {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */ - {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */ - {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */ - {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */ - {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */ - {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */ - {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */ - {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */ - {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */ - {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */ - {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */ - {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */ - {0, 0, NULL}, + {PRCM_ARMCLKFIX_MGT_REG, "ARMCLKFIX"}, + {PRCM_ACLK_MGT_REG, "ACLK"}, + {PRCM_SVAMMDSPCLK_MGT_REG, "SVA"}, + {PRCM_SIAMMDSPCLK_MGT_REG, "SIA"}, + {PRCM_SAAMMDSPCLK_MGT_REG, "SAA"}, + {PRCM_SGACLK_MGT_REG, "SGA"}, + {PRCM_UARTCLK_MGT_REG, "UART"}, + {PRCM_MSPCLK_MGT_REG, "MSP"}, + {PRCM_I2CCLK_MGT_REG, "I2C"}, + {PRCM_SDMMCCLK_MGT_REG, "SDMMC"}, + {PRCM_PER1CLK_MGT_REG, "PER1"}, + {PRCM_PER2CLK_MGT_REG, "PER2"}, + {PRCM_PER3CLK_MGT_REG, "PER3"}, + {PRCM_PER5CLK_MGT_REG, "PER5"}, + {PRCM_PER6CLK_MGT_REG, "PER6"}, + {PRCM_PER7CLK_MGT_REG, "PER7"}, + {PRCM_DMACLK_MGT_REG, "DMA"}, + {PRCM_B2R2CLK_MGT_REG, "B2R2"}, + {0, NULL}, }; struct clkrst { @@ -257,6 +255,13 @@ int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else if ((reg & 0x1f) == 0) /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */ clk_khz = 0; + else if ((clks->addr == PRCM_I2CCLK_MGT_REG) && + (clk_sel == PLLDDR)) + /* + * i2cclk, if clk source is pllddr, divide by 2 first + * because it is on a fixed clock + */ + clk_khz = (pll_khz[clk_sel] / 2) / (reg & 0x1f); else clk_khz = pll_khz[clk_sel] / (reg & 0x1f); printf(", %4d.%03d", clk_khz / 1000, clk_khz % 1000); |