diff options
| author | Mattias Nilsson <mattias.i.nilsson@stericsson.com> | 2011-05-06 13:02:36 +0200 |
|---|---|---|
| committer | Linus WALLEIJ <linus.walleij@stericsson.com> | 2011-05-07 17:27:25 +0200 |
| commit | 4181e3f1effdeeef6c204a9fc6c03684004567ab (patch) | |
| tree | a8108709b0c4c24ab4defe1566344d582e624812 | |
| parent | 12666e59ae22acb54a2ddf382d436112ce8a4e1f (diff) | |
arm: mach-ux500: add support for controlling soc1_pllu8500-android-2.3_v0.76
This patch adds support for enabling/disabling the soc1_pll
clock through the corresponding PRCMU FW service.
ST Ericsson ID: 336339
ST Ericsson FOSS-OUT ID: trivial
Change-Id: I1e478c042710a08ce4d5d1a2e48dac77f05e4a89
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/22510
Reviewed-by: QATEST
Reviewed-by: Linus WALLEIJ <linus.walleij@stericsson.com>
| -rw-r--r-- | arch/arm/mach-ux500/clock-db8500.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/prcmu-fw-api.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/prcmu-db8500.c | 34 |
3 files changed, 39 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c index 31e7022a47a..611a2d24276 100644 --- a/arch/arm/mach-ux500/clock-db8500.c +++ b/arch/arm/mach-ux500/clock-db8500.c @@ -37,6 +37,7 @@ #define SD_CLK_DIV_MASK 0x1F #define SD_CLK_DIV_VAL 8 +static DEFINE_MUTEX(soc1_pll_mutex); static DEFINE_MUTEX(sysclk_mutex); static DEFINE_MUTEX(ab_ulpclk_mutex); static DEFINE_MUTEX(audioclk_mutex); @@ -293,7 +294,9 @@ static struct clk soc0_pll = { static struct clk soc1_pll = { .name = "soc1_pll", - .ops = &pll_clk_ops, + .ops = &prcmu_clk_ops, + .cg_sel = PRCMU_PLLSOC1, + .mutex = &soc1_pll_mutex, }; static struct clk ddr_pll = { diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h index 8227717cc71..56402a115ed 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h @@ -212,6 +212,7 @@ enum prcmu_clock { PRCMU_UICCCLK, PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, + PRCMU_PLLSOC1, PRCMU_TIMCLK, }; diff --git a/arch/arm/mach-ux500/prcmu-db8500.c b/arch/arm/mach-ux500/prcmu-db8500.c index 17a349c786d..edb7003aaa0 100644 --- a/arch/arm/mach-ux500/prcmu-db8500.c +++ b/arch/arm/mach-ux500/prcmu-db8500.c @@ -136,12 +136,16 @@ #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 #define MB1H_RELEASE_USB_WAKEUP 0x5 +#define MB1H_PLL_ON_OFF 0x6 /* Mailbox 1 Requests */ #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) #define PRCM_REQ_MB1_APE_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x4) #define PRCM_REQ_MB1_ARM_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x8) +#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) +#define PLL_SOC1_OFF 0x4 +#define PLL_SOC1_ON 0x8 /* Mailbox 1 ACKs */ #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) @@ -1051,6 +1055,34 @@ int prcmu_release_usb_wakeup_state(void) return r; } +static int request_pll(u8 clock, bool enable) +{ + int r = 0; + + if (clock == PRCMU_PLLSOC1) + clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); + else + return -EINVAL; + + mutex_lock(&mb1_transfer.lock); + + while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) + cpu_relax(); + + writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); + writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); + + writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET)); + wait_for_completion(&mb1_transfer.work); + + if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) + r = -EIO; + + mutex_unlock(&mb1_transfer.lock); + + return r; +} + /** * prcmu_set_hwacc - set the power state of a h/w accelerator * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). @@ -1390,6 +1422,8 @@ int prcmu_request_clock(u8 clock, bool enable) return request_timclk(enable); else if (clock == PRCMU_SYSCLK) return request_sysclk(enable); + else if (clock == PRCMU_PLLSOC1) + return request_pll(clock, enable); else return -EINVAL; } |