diff options
| author | Stefan Roese <sr@denx.de> | 2007-12-21 15:39:38 +1100 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-12-23 13:19:03 -0600 |
| commit | accf5ef254b9dd4d3b53040dd73d80875c2cd39b (patch) | |
| tree | 93ef10f49c2b5d3b4f8874ea713bac93e0a1eeb8 /arch/powerpc/sysdev/ppc4xx_pci.c | |
| parent | 25c24f3dc7f01491ea0d92a1de2bb84094b27e21 (diff) | |
[POWERPC] 4xx: Add 440SPe revA runtime detection to PCIe
This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
| -rw-r--r-- | arch/powerpc/sysdev/ppc4xx_pci.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 0538980ef89..a656dc004b8 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -49,6 +49,15 @@ extern unsigned long total_memory; #define RES_TO_U32_HIGH(val) (0) #endif +static inline int ppc440spe_revA(void) +{ + /* Catch both 440SPe variants, with and without RAID6 support */ + if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) + return 1; + else + return 0; +} + static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) { struct pci_controller *hose; @@ -516,8 +525,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) * * We support 3 parts currently based on the compatible property: * - * ibm,plb-pciex-440speA - * ibm,plb-pciex-440speB + * ibm,plb-pciex-440spe * ibm,plb-pciex-405ex * * Anything else will be rejected for now as they are all subtly @@ -688,7 +696,7 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); - if (of_device_is_compatible(port->node, "ibm,plb-pciex-440speA")) + if (ppc440spe_revA()) mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); @@ -767,7 +775,6 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = .setup_utl = ppc440speB_pciex_init_utl, }; - #endif /* CONFIG_44x */ #ifdef CONFIG_40x @@ -881,10 +888,12 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np) return 0; #ifdef CONFIG_44x - if (of_device_is_compatible(np, "ibm,plb-pciex-440speA")) - ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; - else if (of_device_is_compatible(np, "ibm,plb-pciex-440speB")) - ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; + if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { + if (ppc440spe_revA()) + ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; + else + ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; + } #endif /* CONFIG_44x */ #ifdef CONFIG_40x if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) |