diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 03:55:41 +0000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-24 13:47:32 +1100 |
| commit | 2319f1239592d0de80414ad2338c2bd7384a2a41 (patch) | |
| tree | 805de041dfc84ae9ca767c9767d833977654dbe0 /arch/powerpc/kernel/cpu_setup_6xx.S | |
| parent | eb3436a0139a651a39dbb37a75b10a2cccd00ad5 (diff) | |
powerpc/mm: e300c2/c3/c4 TLB errata workaround
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Based on patch from David Jander <david@protonic.nl>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_6xx.S')
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_6xx.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S index 72d1d739525..54f767e31a1 100644 --- a/arch/powerpc/kernel/cpu_setup_6xx.S +++ b/arch/powerpc/kernel/cpu_setup_6xx.S @@ -15,9 +15,14 @@ #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> #include <asm/cache.h> +#include <asm/mmu.h> _GLOBAL(__setup_cpu_603) mflr r4 +BEGIN_MMU_FTR_SECTION + li r10,0 + mtspr SPRN_SPRG4,r10 /* init SW LRU tracking */ +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) BEGIN_FTR_SECTION bl __init_fpu_registers END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE) |