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authorRalf Baechle <ralf@linux-mips.org>2009-06-19 15:01:44 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-06-24 18:34:39 +0100
commit44eeab67416711db9b84610ef18c99a60415dff8 (patch)
treee9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 /arch/mips/power/hibernate.S
parent631330f5847b3f8a7ea67d689e9f7c56833ccaa6 (diff)
downloadlinux-2.6.38-lt-ux500-44eeab67416711db9b84610ef18c99a60415dff8.tar.gz
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because interrupts are disabled. A cross-CPU flush is unnecessary anyway because all but the local CPU have already been disabled. A local flush is not needed either because we didn't change any mappings. So just delete the code. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/power/hibernate.S')
-rw-r--r--arch/mips/power/hibernate.S9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 486bd3fd01a..4b8174b382d 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume)
bne t1, t3, 1b
PTR_L t0, PBE_NEXT(t0)
bnez t0, 0b
- /* flush caches to make sure context is in memory */
- PTR_L t0, __flush_cache_all
- jalr t0
- /* flush tlb entries */
-#ifdef CONFIG_SMP
- jal flush_tlb_all
-#else
- jal local_flush_tlb_all
-#endif
PTR_LA t0, saved_regs
PTR_L ra, PT_R31(t0)
PTR_L sp, PT_R29(t0)