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authorShinya Kuribayashi <shinya.kuribayashi@necel.com>2009-03-03 18:05:51 +0900
committerRalf Baechle <ralf@linux-mips.org>2009-03-11 21:11:07 +0100
commita644b2774d41409519bb33a16bd577cb41bb3095 (patch)
treea0a8a574ac53e318dbf72306d6b752224ebdbc64 /arch/mips/mm/tlbex.c
parentc189846ecf900cd6b3ad7d3cef5b45a746ce646b (diff)
downloadlinux-2.6.38-lt-ux500-a644b2774d41409519bb33a16bd577cb41bb3095.tar.gz
MIPS: NEC VR5500 processor support fixup
Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
-rw-r--r--arch/mips/mm/tlbex.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 42942038d0f..f335cf6cdd7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BCM4710:
case CPU_LOONGSON2:
case CPU_CAVIUM_OCTEON:
+ case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
tlbw(p);