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authorRalf Baechle <ralf@linux-mips.org>2008-01-29 10:14:54 +0000
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 10:14:54 +0000
commit161548bf3529d53398adb3451cdc781cc324fc1d (patch)
tree47495cee5b14706a2228f1fc9cfa53813851d6aa /arch/mips/mm/tlbex.c
parent6920df4025b426cb3c9756944a965fe9ccb30925 (diff)
downloadlinux-2.6.38-lt-ux500-161548bf3529d53398adb3451cdc781cc324fc1d.tar.gz
[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
-rw-r--r--arch/mips/mm/tlbex.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a61246d3533..511107f92d9 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -860,6 +860,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
case tlb_indexed: tlbw = i_tlbwi; break;
}
+ if (cpu_has_mips_r2) {
+ i_ehb(p);
+ tlbw(p);
+ return;
+ }
+
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
@@ -935,14 +941,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
tlbw(p);
break;
- case CPU_4KEC:
- case CPU_24K:
- case CPU_34K:
- case CPU_74K:
- i_ehb(p);
- tlbw(p);
- break;
-
case CPU_RM9000:
/*
* When the JTLB is updated by tlbwi or tlbwr, a subsequent