|author||Ralf Baechle <firstname.lastname@example.org>||2009-06-19 15:01:44 +0100|
|committer||Ralf Baechle <email@example.com>||2009-06-24 18:34:39 +0100|
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because interrupts are disabled. A cross-CPU flush is unnecessary anyway because all but the local CPU have already been disabled. A local flush is not needed either because we didn't change any mappings. So just delete the code. Signed-off-by: Ralf Baechle <firstname.lastname@example.org>
Diffstat (limited to 'arch/mips/mipssim/sim_time.c')
0 files changed, 0 insertions, 0 deletions