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authorJohn Ogness <john.ogness@linutronix.de>2011-02-22 20:00:47 -0700
committerPaul Walmsley <paul@pwsan.com>2011-02-22 20:00:47 -0700
commitea68c00e2623bb5b001c2117a4dcca4754781b4e (patch)
tree02c25b983a7735cd444a525a0b0946dc0be9004a /arch/arm
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
OMAP2/3: clock: fix fint calculation for DPLL_FREQSEL
In OMAP35X TRM Rev 2010-05 Figure 7-18 "DPLL With EMI Reduction Feature", it is shown that the internal frequency is calculated by CLK_IN/(N+1). However, the value passed to _dpll_test_fint() is already "N+1" since Linux is using the values to divide by. In the technical reference manual, "N" is referring to the divider's register value (0-127). During power management testing, it was observed that programming the wrong jitter correction value can cause the system to become unstable and eventually crash. Signed-off-by: John Ogness <john.ogness@linutronix.de> [paul@pwsan.com: added second paragraph to commit message] Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 337392c3f54..acb7ae5b0a2 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
- fint = clk->parent->rate / (n + 1);
+ fint = clk->parent->rate / n;
if (fint < DPLL_FINT_BAND1_MIN) {
pr_debug("rejecting n=%d due to Fint failure, "