aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/include
diff options
context:
space:
mode:
authorMikael Pettersson <mikpe@it.uu.se>2009-10-29 11:46:54 -0700
committerDan Williams <dan.j.williams@intel.com>2009-10-29 11:46:54 -0700
commita91549a8f27e63e0e537fe1c20d4845581de894f (patch)
tree6cf4a9ecf379cc4bdaa8d988c45702135aecdaa3 /arch/arm/include
parent012abeea669ea49636cf952d13298bb68654146a (diff)
iop: clocksource support
This updates the IOP platform to expose the free-running timer 1 as a clocksource object. This timer is now also properly initialised, which requires a new write_tcr1() function from the mach-specific code. Apart from the explicit initialisation, there is no functional change in how timer 1 is programmed. Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/hardware/iop3xx.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 8d60ad267e3..643b7b95b25 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -260,6 +260,11 @@ static inline u32 read_tcr1(void)
return val;
}
+static inline void write_tcr1(u32 val)
+{
+ asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
+}
+
static inline void write_trr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));