/* * Copyright (C) 2010 ST-Ericsson * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2, as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include "devices-db8500.h" #include "pins-db8500.h" #include "board-mop500.h" /* * SDI0 (SD/MMC card) */ #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg sdi0_dma_cfg_rx = { .dir = STEDMA40_PERIPH_TO_MEM, .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX, .dst_dev_type = STEDMA40_DEV_DST_MEMORY, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; static struct stedma40_chan_cfg sdi0_dma_cfg_tx = { .dir = STEDMA40_MEM_TO_PERIPH, .src_dev_type = STEDMA40_DEV_SRC_MEMORY, .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; #endif static void sdi0_configure(void) { int ret; int gpio[2]; if (machine_is_snowball()) { gpio[0] = SNOWBALL_SDMMC_EN_GPIO; gpio[1] = SNOWBALL_SDMMC_1V8_3V_GPIO; } else if (machine_is_hrefv60()) { gpio[0] = HREFV60_SDMMC_EN_GPIO; gpio[1] = HREFV60_SDMMC_1V8_3V_GPIO; } else { gpio[0] = EGPIO_PIN_17; gpio[1] = EGPIO_PIN_18; } ret = gpio_request(gpio[0], "level shifter enable"); if (!ret) ret = gpio_request(gpio[1], "level shifter select"); if (ret) { printk(KERN_WARNING "unable to config gpios for level shifter.\n"); return; } /* Select the default 2.9V and eanble level shifter */ gpio_direction_output(gpio[1], 0); gpio_direction_output(gpio[0], 1); } static void sdi0_vdd_handler(struct device *dev, unsigned int vdd, unsigned char power_mode) { int gpio[2]; if (machine_is_snowball()) { gpio[0] = SNOWBALL_SDMMC_EN_GPIO; gpio[1] = SNOWBALL_SDMMC_1V8_3V_GPIO; } else if (machine_is_hrefv60()) { gpio[0] = HREFV60_SDMMC_EN_GPIO; gpio[1] = HREFV60_SDMMC_1V8_3V_GPIO; } else { gpio[0] = EGPIO_PIN_17; gpio[1] = EGPIO_PIN_18; } switch (power_mode) { case MMC_POWER_UP: case MMC_POWER_ON: /* * Level shifter voltage should depend on vdd to when deciding * on either 1.8V or 2.9V. Once the decision has been made the * level shifter must be disabled and re-enabled with a changed * select signal in order to switch the voltage. Since there is * no framework support yet for indicating 1.8V in vdd, use the * default 2.9V. */ gpio_direction_output(gpio[1], 0); /* Enable level shifter */ gpio_direction_output(gpio[0], 1); break; case MMC_POWER_OFF: gpio_direction_output(gpio[1], 0); /* Disable level shifter */ gpio_direction_output(gpio[0], 0); break; } } static struct mmci_platform_data mop500_sdi0_data = { .vcc = "v-mmc", .vcard = "v-MMC-SD", .vdd_handler = sdi0_vdd_handler, .disable = 5000, .bus_resume_flags = MMC_NEEDS_UNSAFE_RESUME, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_DISABLE, .gpio_wp = -1, .sigdir = MMCI_ST_DIRFBCLK | MMCI_ST_DIRCMD | MMCI_ST_DIRDAT0 | MMCI_ST_DIRDAT2, #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &sdi0_dma_cfg_rx, .dma_tx_param = &sdi0_dma_cfg_tx, #endif }; /* * SDI1 (SDIO WLAN) */ #ifdef CONFIG_STE_DMA40 #ifdef MMC_WITH_DMA static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { .dir = STEDMA40_PERIPH_TO_MEM, .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, .dst_dev_type = STEDMA40_DEV_DST_MEMORY, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { .dir = STEDMA40_MEM_TO_PERIPH, .src_dev_type = STEDMA40_DEV_SRC_MEMORY, .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; #endif #endif /* * TODO 1: SDIO power management not fully supported. * bus_resume_flag should be 0. * TODO 2: SDIO with DMA not yet supported. */ static struct mmci_platform_data mop500_sdi1_data = { .vcc = "v-mmc", .disable = 500, .bus_resume_flags = MMC_NEEDS_UNSAFE_RESUME, .ocr_mask = MMC_VDD_29_30, .f_max = 15000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_DISABLE | MMC_CAP_SDIO_IRQ | MMC_CAP_BROKEN_SDIO_CMD53, .gpio_cd = -1, .gpio_wp = -1, #ifdef MMC_WITH_DMA /* To be verified. */ #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &sdi1_dma_cfg_rx, .dma_tx_param = &sdi1_dma_cfg_tx, #endif #endif }; /* * SDI2 (POPed eMMC) */ #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg sdi2_dma_cfg_rx = { .dir = STEDMA40_PERIPH_TO_MEM, .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX, .dst_dev_type = STEDMA40_DEV_DST_MEMORY, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; static struct stedma40_chan_cfg sdi2_dma_cfg_tx = { .dir = STEDMA40_MEM_TO_PERIPH, .src_dev_type = STEDMA40_DEV_SRC_MEMORY, .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; #endif static struct mmci_platform_data mop500_sdi2_data = { .vcc = "v-mmc", .disable = 5000, .bus_resume_flags = MMC_NEEDS_UNSAFE_RESUME, .ocr_mask = MMC_VDD_165_195, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DISABLE, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &sdi2_dma_cfg_rx, .dma_tx_param = &sdi2_dma_cfg_tx, #endif }; /* * SDI4 (On-board eMMC) */ #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg sdi4_dma_cfg_rx = { .dir = STEDMA40_PERIPH_TO_MEM, .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX, .dst_dev_type = STEDMA40_DEV_DST_MEMORY, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; static struct stedma40_chan_cfg sdi4_dma_cfg_tx = { .dir = STEDMA40_MEM_TO_PERIPH, .src_dev_type = STEDMA40_DEV_SRC_MEMORY, .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX, .src_info.data_width = STEDMA40_WORD_WIDTH, .dst_info.data_width = STEDMA40_WORD_WIDTH, }; #endif static struct mmci_platform_data mop500_sdi4_data = { .vcc = "v-mmc", .vcard = "v-eMMC", .disable = 5000, .bus_resume_flags = MMC_NEEDS_UNSAFE_RESUME, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_DISABLE, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &sdi4_dma_cfg_rx, .dma_tx_param = &sdi4_dma_cfg_tx, #endif }; static int __init mop500_sdi_init(void) { /* POP eMMC on v1.0 has problems with high speed */ if (!cpu_is_u8500v10()) mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */ if (!machine_is_snowball()) db8500_add_sdi2(&mop500_sdi2_data); db8500_add_sdi4(&mop500_sdi4_data); sdi0_configure(); if (machine_is_snowball()) { mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; mop500_sdi0_data.cd_invert = true; mop500_sdi0_data.sigdir = 0; } else if (machine_is_hrefv60()) mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; else mop500_sdi0_data.gpio_cd = EGPIO_PIN_3; db8500_add_sdi0(&mop500_sdi0_data); db8500_add_sdi1(&mop500_sdi1_data); return 0; } fs_initcall(mop500_sdi_init);