aboutsummaryrefslogtreecommitdiff
path: root/include/asm-arm/arch-ns9xxx/regs-mem.h
blob: 023f7be6f4c6b5262bbc70cc747f1d01932f176a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
/*
 * include/asm-arm/arch-ns9xxx/regs-mem.h
 *
 * Copyright (C) 2006 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */
#ifndef __ASM_ARCH_REGSMEM_H
#define __ASM_ARCH_REGSMEM_H

#include <asm/arch/hardware.h>

/* Memory Module */

/* Control register */
#define MEM_CTRL	__REG(0xa0700000)

/* Status register */
#define MEM_STAT	__REG(0xa0700004)

/* Configuration register */
#define MEM_CONF	__REG(0xa0700008)

/* Dynamic Memory Control register */
#define MEM_DMCTRL	__REG(0xa0700020)

/* Dynamic Memory Refresh Timer */
#define MEM_DMRT	__REG(0xa0700024)

/* Dynamic Memory Read Configuration register */
#define MEM_DMRC	__REG(0xa0700028)

/* Dynamic Memory Precharge Command Period (tRP) */
#define MEM_DMPCP	__REG(0xa0700030)

/* Dynamic Memory Active to Precharge Command Period (tRAS) */
#define MEM_DMAPCP	__REG(0xa0700034)

/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
#define MEM_DMSRET	__REG(0xa0700038)

/* Dynamic Memory Last Data Out to Active Time (tAPR) */
#define MEM_DMLDOAT	__REG(0xa070003c)

/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
#define MEM_DMDIACT	__REG(0xa0700040)

/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
#define MEM_DMWRT	__REG(0xa0700044)

/* Dynamic Memory Active to Active Command Period (tRC) */
#define MEM_DMAACP	__REG(0xa0700048)

/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
#define MEM_DMARP	__REG(0xa070004c)

/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
#define MEM_DMESRAC	__REG(0xa0700050)

/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
#define MEM_DMABAABT	__REG(0xa0700054)

/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
#define MEM_DMLMACT	__REG(0xa0700058)

/* Static Memory Extended Wait */
#define MEM_SMEW	__REG(0xa0700080)

/* Dynamic Memory Configuration Register x */
#define MEM_DMCONF(x) 	__REG2(0xa0700100, (x) << 3)

/* Dynamic Memory RAS and CAS Delay x */
#define MEM_DMRCD(x)	__REG2(0xa0700104, (x) << 3)

/* Static Memory Configuration Register x */
#define MEM_SMC(x)	__REG2(0xa0700200, (x) << 3)

/* Static Memory Configuration Register x: Write protect */
#define MEM_SMC_PSMC		__REGBIT(20)
#define MEM_SMC_PSMC_OFF		__REGVAL(MEM_SMC_PSMC, 0)
#define MEM_SMC_PSMC_ON			__REGVAL(MEM_SMC_PSMC, 1)

/* Static Memory Configuration Register x: Buffer enable */
#define MEM_SMC_BSMC		__REGBIT(19)
#define MEM_SMC_BSMC_OFF		__REGVAL(MEM_SMC_BSMC, 0)
#define MEM_SMC_BSMC_ON			__REGVAL(MEM_SMC_BSMC, 1)

/* Static Memory Configuration Register x: Extended Wait */
#define MEM_SMC_EW		__REGBIT(8)
#define MEM_SMC_EW_OFF			__REGVAL(MEM_SMC_EW, 0)
#define MEM_SMC_EW_ON			__REGVAL(MEM_SMC_EW, 1)

/* Static Memory Configuration Register x: Byte lane state */
#define MEM_SMC_PB		__REGBIT(7)
#define MEM_SMC_PB_0			__REGVAL(MEM_SMC_PB, 0)
#define MEM_SMC_PB_1			__REGVAL(MEM_SMC_PB, 1)

/* Static Memory Configuration Register x: Chip select polarity */
#define MEM_SMC_PC		__REGBIT(6)
#define MEM_SMC_PC_AL			__REGVAL(MEM_SMC_PC, 0)
#define MEM_SMC_PC_AH			__REGVAL(MEM_SMC_PC, 1)

/* static memory configuration register x: page mode*/
#define MEM_SMC_PM		__REGBIT(3)
#define MEM_SMC_PM_DIS			__REGVAL(MEM_SMC_PM, 0)
#define MEM_SMC_PM_ASYNC		__REGVAL(MEM_SMC_PM, 1)

/* static memory configuration register x: Memory width */
#define MEM_SMC_MW		__REGBITS(1, 0)
#define MEM_SMC_MW_8			__REGVAL(MEM_SMC_MW, 0)
#define MEM_SMC_MW_16			__REGVAL(MEM_SMC_MW, 1)
#define MEM_SMC_MW_32			__REGVAL(MEM_SMC_MW, 2)

/* Static Memory Write Enable Delay x */
#define MEM_SMWED(x)	__REG2(0xa0700204, (x) << 3)

/* Static Memory Output Enable Delay x */
#define MEM_SMOED(x)	__REG2(0xa0700208, (x) << 3)

/* Static Memory Read Delay x */
#define MEM_SMRD(x)	__REG2(0xa070020c, (x) << 3)

/* Static Memory Page Mode Read Delay 0 */
#define MEM_SMPMRD(x)	__REG2(0xa0700210, (x) << 3)

/* Static Memory Write Delay */
#define MEM_SMWD(x)	__REG2(0xa0700214, (x) << 3)

/* Static Memory Turn Round Delay x */
#define MEM_SWT(x)	__REG2(0xa0700218, (x) << 3)

#endif /* ifndef __ASM_ARCH_REGSMEM_H */