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/*
* Copyright (C) ST-Ericsson SA 2010
* Author: Deepak KARDA/ deepak.karda@stericsson.com for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2.
*/
#ifndef _AUDIOIO_REG_DEFS_H_
#define _AUDIOIO_REG_DEFS_H_
/* Registers */
#define POWER_UP_CONTROL_REG 0x0D00
#define SOFTWARE_RESET_REG 0x0D01
#define DIGITAL_AD_CHANNELS_ENABLE_REG 0x0D02
#define DIGITAL_DA_CHANNELS_ENABLE_REG 0x0D03
#define LOW_POWER_HS_EAR_CONF_REG 0x0D04
#define LINE_IN_MIC_CONF_REG 0x0D05
#define DMIC_ENABLE_REG 0x0D06
#define ADC_DAC_ENABLE_REG 0x0D07
#define ANALOG_OUTPUT_ENABLE_REG 0x0D08
#define DIGITAL_OUTPUT_ENABLE_REG 0x0D09
#define MUTE_HS_EAR_REG 0x0D0A
#define SHORT_CIRCUIT_DISABLE_REG 0x0D0B
#define NCP_ENABLE_HS_AUTOSTART_REG 0x0D0C
#define ENVELOPE_THRESHOLD_REG 0x0D0D
#define ENVELOPE_DECAY_TIME_REG 0x0D0E
#define VIB_DRIVER_CONF_REG 0x0D0F
#define PWM_VIBNL_CONF_REG 0x0D10
#define PWM_VIBPL_CONF_REG 0x0D11
#define PWM_VIBNR_CONF_REG 0x0D12
#define PWM_VIBPR_CONF_REG 0x0D13
#define ANALOG_MIC1_GAIN_REG 0x0D14
#define ANALOG_MIC2_GAIN_REG 0x0D15
#define ANALOG_HS_GAIN_REG 0x0D16
#define ANALOG_LINE_IN_GAIN_REG 0x0D17
#define LINE_IN_TO_HSL_GAIN_REG 0x0D18
#define LINE_IN_TO_HSR_GAIN_REG 0x0D19
#define AD_FILTER_CONF_REG 0x0D1A
#define IF0_IF1_MASTER_CONF_REG 0x0D1B
#define IF0_CONF_REG 0x0D1C
#define TDM_IF_BYPASS_B_FIFO_REG 0x0D1D
#define IF1_CONF_REG 0x0D1E
#define AD_ALLOCATION_TO_SLOT0_1_REG 0x0D1F
#define AD_ALLOCATION_TO_SLOT2_3_REG 0x0D20
#define AD_ALLOCATION_TO_SLOT4_5_REG 0x0D21
#define AD_ALLOCATION_TO_SLOT6_7_REG 0x0D22
#define AD_ALLOCATION_TO_SLOT8_9_REG 0x0D23
#define AD_ALLOCATION_TO_SLOT10_11_REG 0x0D24
#define AD_ALLOCATION_TO_SLOT12_13_REG 0x0D25
#define AD_ALLOCATION_TO_SLOT14_15_REG 0x0D26
#define AD_ALLOCATION_TO_SLOT16_17_REG 0x0D27
#define AD_ALLOCATION_TO_SLOT18_19_REG 0x0D28
#define AD_ALLOCATION_TO_SLOT20_21_REG 0x0D29
#define AD_ALLOCATION_TO_SLOT22_23_REG 0x0D2A
#define AD_ALLOCATION_TO_SLOT24_25_REG 0x0D2B
#define AD_ALLOCATION_TO_SLOT26_27_REG 0x0D2C
#define AD_ALLOCATION_TO_SLOT28_29_REG 0x0D2D
#define AD_ALLOCATION_TO_SLOT30_31_REG 0x0D2E
#define AD_SLOT_0_TO_7_TRISTATE_REG 0x0D2F
#define AD_SLOT_8_TO_15_TRISTATE_REG 0x0D30
#define AD_SLOT_16_TO_23_TRISTATE_REG 0x0D31
#define AD_SLOT_24_TO_31_TRISTATE_REG 0x0D32
#define SLOT_SELECTION_TO_DA1_REG 0x0D33
#define SLOT_SELECTION_TO_DA2_REG 0x0D34
#define SLOT_SELECTION_TO_DA3_REG 0x0D35
#define SLOT_SELECTION_TO_DA4_REG 0x0D36
#define SLOT_SELECTION_TO_DA5_REG 0x0D37
#define SLOT_SELECTION_TO_DA6_REG 0x0D38
#define SLOT_SELECTION_TO_DA7_REG 0x0D39
#define SLOT_SELECTION_TO_DA8_REG 0x0D3A
#define CLASS_D_EMI_PARALLEL_CONF_REG 0x0D3B
#define CLASS_D_PATH_CONTROL_REG 0x0D3C
#define CLASS_D_DITHER_CONTROL_REG 0x0D3D
#define DMIC_DECIMATOR_FILTER_REG 0x0D3E
#define DIGITAL_MUXES_REG1 0x0D3F
#define DIGITAL_MUXES_REG2 0x0D40
#define AD1_DIGITAL_GAIN_REG 0x0D41
#define AD2_DIGITAL_GAIN_REG 0x0D42
#define AD3_DIGITAL_GAIN_REG 0x0D43
#define AD4_DIGITAL_GAIN_REG 0x0D44
#define AD5_DIGITAL_GAIN_REG 0x0D45
#define AD6_DIGITAL_GAIN_REG 0x0D46
#define DA1_DIGITAL_GAIN_REG 0x0D47
#define DA2_DIGITAL_GAIN_REG 0x0D48
#define DA3_DIGITAL_GAIN_REG 0x0D49
#define DA4_DIGITAL_GAIN_REG 0x0D4A
#define DA5_DIGITAL_GAIN_REG 0x0D4B
#define DA6_DIGITAL_GAIN_REG 0x0D4C
#define AD1_TO_HFL_DIGITAL_GAIN_REG 0x0D4D
#define AD2_TO_HFR_DIGITAL_GAIN_REG 0x0D4E
#define HSL_EAR_DIGITAL_GAIN_REG 0x0D4F
#define HSR_DIGITAL_GAIN_REG 0x0D50
#define SIDETONE_FIR1_GAIN_REG 0x0D51
#define SIDETONE_FIR2_GAIN_REG 0x0D52
#define ANC_FILTER_CONTROL_REG 0x0D53
#define ANC_WARPED_GAIN_REG 0x0D54
#define ANC_FIR_OUTPUT_GAIN_REG 0x0D55
#define ANC_IIR_OUTPUT_GAIN_REG 0x0D56
#define ANC_FIR_COEFF_MSB_REG 0x0D57
#define ANC_FIR_COEFF_LSB_REG 0x0D58
#define ANC_IIR_COEFF_MSB_REG 0x0D59
#define ANC_IIR_COEFF_LSB_REG 0x0D5A
#define ANC_WARP_DELAY_MSB_REG 0x0D5B
#define ANC_WARP_DELAY_LSB_REG 0x0D5C
#define ANC_FIR_PEAK_MSB_REG 0x0D5D
#define ANC_FIR_PEAK_LSB_REG 0x0D5E
#define ANC_IIR_PEAK_MSB_REG 0x0D5F
#define ANC_IIR_PEAK_LSB_REG 0x0D60
#define SIDETONE_FIR_ADDR_REG 0x0D61
#define SIDETONE_FIR_COEFF_MSB_REG 0x0D62
#define SIDETONE_FIR_COEFF_LSB_REG 0x0D63
#define FILTERS_CONTROL_REG 0x0D64
#define IRQ_MASK_LSB_REG 0x0D65
#define IRQ_STATUS_LSB_REG 0x0D66
#define IRQ_MASK_MSB_REG 0x0D67
#define IRQ_STATUS_MSB_REG 0x0D68
#define BURST_FIFO_INT_CONTROL_REG 0x0D69
#define BURST_FIFO_LENGTH_REG 0x0D6A
#define BURST_FIFO_CONTROL_REG 0x0D6B
#define BURST_FIFO_SWITCH_FRAME_REG 0x0D6C
#define BURST_FIFO_WAKE_UP_DELAY_REG 0x0D6D
#define BURST_FIFO_SAMPLES_REG 0x0D6E
#define REVISION_REG 0x0D6F
/* POWER_UP_CONTROL_REG Masks */
#define DEVICE_POWER_UP 0x80
#define ANALOG_PARTS_POWER_UP 0x08
/* SOFTWARE_RESET_REG Masks */
#define SW_RESET 0x80
/* DIGITAL_AD_CHANNELS_ENABLE_REG Masks */
#define EN_AD1 0x80
#define EN_AD2 0x80
#define EN_AD3 0x20
#define EN_AD4 0x20
#define EN_AD5 0x08
#define EN_AD6 0x04
/* DIGITAL_DA_CHANNELS_ENABLE_REG Masks */
#define EN_DA1 0x80
#define EN_DA2 0x40
#define EN_DA3 0x20
#define EN_DA4 0x10
#define EN_DA5 0x08
#define EN_DA6 0x04
/* LOW_POWER_HS_EAR_CONF_REG Masks */
#define LOW_POWER_HS 0x80
#define HS_DAC_DRIVER_LP 0x40
#define HS_DAC_LP 0x20
#define EAR_DAC_LP 0x10
/* LINE_IN_MIC_CONF_REG Masks */
#define EN_MIC1 0x80
#define EN_MIC2 0x40
#define EN_LIN_IN_L 0x20
#define EN_LIN_IN_R 0x10
#define MUT_MIC1 0x08
#define MUT_MIC2 0x04
#define MUT_LIN_IN_L 0x02
#define MUT_LIN_IN_R 0x01
/* DMIC_ENABLE_REG Masks */
#define EN_DMIC1 0x80
#define EN_DMIC2 0x40
#define EN_DMIC3 0x20
#define EN_DMIC4 0x10
#define EN_DMIC5 0x08
#define EN_DMIC6 0x04
/* ADC_DAC_ENABLE_REG Masks */
#define SEL_MIC1B_CLR_MIC1A 0x80
#define SEL_LINR_CLR_MIC2 0x40
#define POWER_UP_HSL_DAC 0x20
#define POWER_UP_HSR_DAC 0x10
#define POWER_UP_ADC1 0x04
#define POWER_UP_ADC3 0x02
#define POWER_UP_ADC2 0x01
/* ANALOG_OUTPUT_ENABLE_REG and DIGITAL_OUTPUT_ENABLE_REG and
MUTE_HS_EAR_REG Masks */
#define EN_EAR_MASK 0x40
#define EN_HSL_MASK 0x20
#define EN_HSR_MASK 0x10
#define EN_HFL_MASK 0x08
#define EN_HFR_MASK 0x04
#define EN_VIBL_MASK 0x02
#define EN_VIBR_MASK 0x01
/* SHORT_CIRCUIT_DISABLE_REG Masks */
#define HS_SHORT_DIS 0x20
#define HS_PULL_DOWN_EN 0x10
#define HS_OSC_EN 0x04
#define DIS_HS_FAD 0x02
#define HS_ZCD_DIS 0x01
/* NCP_ENABLE_HS_AUTOSTART_REG Masks */
#define EN_NEG_CP 0x80
#define HS_AUTO_EN 0x01
/* ANALOG_MIC1_GAIN_REG and ANALOG_MIC1_GAIN_REG Masks */
#define MIC_ANALOG_GAIN_MASK 0x1F
/*ANALOG_HS_GAIN_REG and ANALOG_LINE_IN_GAIN_REG Masks*/
#define L_ANALOG_GAIN_MASK 0xF0
#define R_ANALOG_GAIN_MASK 0x0F
/* IF0_IF1_MASTER_CONF_REG Masks */
#define EN_MASTGEN 0x80
#define BITCLK_OSR_N_64 0x02
#define BITCLK_OSR_N_128 0x04
#define BITCLK_OSR_N_256 0x06
#define EN_FSYNC_BITCLK 0x01
#define EN_FSYNC_BITCLK1 0x10
/* IF0_CONF_REG and IF1_CONF_REG Masks */
#define FSYNC_FALLING_EDGE 0x40
#define BITCLK_FALLING_EDGE 0x20
#define IF_DELAYED 0x10
#define I2S_LEFT_ALIGNED_FORMAT 0x08
#define TDM_FORMAT 0x04
#define WORD_LENGTH_32 0x03
#define WORD_LENGTH_24 0x02
#define WORD_LENGTH_20 0x01
#define WORD_LENGTH_16 0x00
/* TDM_IF_BYPASS_B_FIFO_REG Masks */
#define IF0_BFifoEn 0x01
#define IF0_MASTER 0x02
#define IF1_MASTER 0x20
/*
* AD_ALLOCATION_TO_SLOT0_1_REG and AD_ALLOCATION_TO_SLOT2_3_REG and
* AD_ALLOCATION_TO_SLOT4_5_REG and AD_ALLOCATION_TO_SLOT6_7_REG Masks
*/
#define DATA_FROM_AD_OUT1 0x00
#define DATA_FROM_AD_OUT2 0x01
#define DATA_FROM_AD_OUT3 0x02
#define DATA_FROM_AD_OUT4 0x03
#define DATA_FROM_AD_OUT5 0x04
#define DATA_FROM_AD_OUT6 0x05
#define DATA_FROM_AD_OUT7 0x06
#define DATA_FROM_AD_OUT8 0x07
#define TRISTATE 0x0C
/*
* SLOT_SELECTION_TO_DA1_REG and SLOT_SELECTION_TO_DA2_REG and
* SLOT_SELECTION_TO_DA3_REG and SLOT_SELECTION_TO_DA4_REG Masks
* SLOT_SELECTION_TO_DA5_REG and SLOT_SELECTION_TO_DA6_REG Masks
*/
#define SLOT08_FOR_DA_PATH 0x08
#define SLOT09_FOR_DA_PATH 0x09
#define SLOT10_FOR_DA_PATH 0x0A
#define SLOT11_FOR_DA_PATH 0x0B
#define SLOT12_FOR_DA_PATH 0x0C
#define SLOT13_FOR_DA_PATH 0x0D
#define SLOT14_FOR_DA_PATH 0x0E
#define SLOT15_FOR_DA_PATH 0x0F
/* DIGITAL_MUXES_REG1 Masks */
#define DA1_TO_HSL 0x80
#define DA2_TO_HSR 0x40
#define SEL_DMIC1_FOR_AD_OUT1 0x20
#define SEL_DMIC2_FOR_AD_OUT2 0x10
#define SEL_DMIC3_FOR_AD_OUT3 0x08
/*#define SEL_DMIC5_FOR_AD_OUT5 0x04*/
/*#define SEL_DMIC6_FOR_AD_OUT6 0x02*/
/*#define SEL_DMIC1_FOR_AD_OUT1 0x01*/
/*
* AD1_DIGITAL_GAIN_REG and AD2_DIGITAL_GAIN_REG & AD3_DIGITAL_GAIN_REG Masks
* AD4_DIGITAL_GAIN_REG and AD5_DIGITAL_GAIN_REG & AD6_DIGITAL_GAIN_REG Masks
* DA1_DIGITAL_GAIN_REG and DA2_DIGITAL_GAIN_REG & DA3_DIGITAL_GAIN_REG Masks
* DA4_DIGITAL_GAIN_REG and DA5_DIGITAL_GAIN_REG & DA6_DIGITAL_GAIN_REG Masks
*/
#define DIS_FADING 0x40
#define DIGITAL_GAIN_MASK 0x3F
/*
* HSL_EAR_DIGITAL_GAIN_REG and HSR_DIGITAL_GAIN_REG Masks
*/
#define FADE_SPEED_MASK 0xC0
#define DIS_DIG_GAIN_FADING 0x10
#define HS_DIGITAL_GAIN_MASK 0x0F
/* FMRx/FMTx Masks */
#define SLOT24_FOR_DA_PATH 0x18
#define SEL_AD_OUT8_FROM_DAIN7 0x20
#define SLOT25_FOR_DA_PATH 0x19
#define SEL_AD_OUT6_FROM_DAIN8 0x20
#define SEL_IF8_FROM_AD_OUT7 0x60
#define SEL_IF17_FROM_AD_OUT7 0x60
#define SEL_IF16_FROM_AD_OUT8 0x07
#define SEL_IF6_FROM_AD_OUT5 0x04
#define SEL_IF7_FROM_AD_OUT6 0x50
#define SEL_IF17_FROM_AD_OUT6 0x50
#define SEL_AD_OUT5_FROM_DAIN7 0x20
/* Burst FIFO Control Masks */
#define WAKEUP_SIGNAL_SAMPLE_COUNT 0x1B
#define BURST_FIFO_TRANSFER_LENGTH 0xC0
#define BURST_FIFO_INF_RUNNING 0x01
#define BURST_FIFO_INF_IN_MASTER_MODE 0x02
#define PRE_BIT_CLK0_COUNT 0x1C
#define BURST_FIFO_WAKUP_DEALAY 0x70
/* AB8500 power control Masks */
#define AB8500_VER_1_0 0x10
#define AB8500_VER_1_1 0x11
#define CLK_32K_OUT2_DISABLE 0x01
#define INACTIVE_RESET_AUDIO 0x02
#define AB8500_REQ_SYS_CLK 0x08
#define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
#define ENABLE_VINTCORE12_SUPPLY 0x04
#define VAMIC2_ENABLE 0x10
#define VAMIC1_ENABLE 0x08
#define VDMIC_ENABLE 0x04
#define VAUDIO_ENABLE 0x02
#define GPIO27_DIR_OUTPUT 0x04
#define GPIO29_DIR_OUTPUT 0x10
#define GPIO31_DIR_OUTPUT 0x40
#endif
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