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-rwxr-xr-xarch/arm/mach-ux500/clock.c8
-rwxr-xr-xarch/arm/mach-ux500/clock.h3
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mmc.h4
3 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 43d6b9e2062..b89be262e03 100755
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -773,9 +773,13 @@ int __init clk_init(void)
+ PRCM_SDMMCCLK_MGT;
unsigned int val;
- /* Switch SDMMCCLK to 52Mhz instead of 104Mhz */
+ /* Set SDMMCCLK at 100Mhz */
val = readl(sdmmclkmgt);
- val = (val & ~0x1f) | 16;
+ /*
+ * set the clock divider
+ * to configure the MCLK at 100MHZ
+ */
+ val = (val & ~SD_CLK_DIV_MASK) | SD_CLK_DIV_VAL;
writel(val, sdmmclkmgt);
} else if (cpu_is_u5500()) {
clk_prcmu_ops.enable = NULL;
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index 5a454b95886..db5fc107dde 100755
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -40,6 +40,9 @@ void update_clk_tree(void);
/* Clock enable bit */
#define ENABLE_BIT 0x100
+#define SD_CLK_DIV_MASK 0x1F
+#define SD_CLK_DIV_VAL 8
+
struct clkops {
void (*enable) (struct clk *);
void (*disable) (struct clk *);
diff --git a/arch/arm/mach-ux500/include/mach/mmc.h b/arch/arm/mach-ux500/include/mach/mmc.h
index a3bdcc35d61..1fa18b8b06d 100755
--- a/arch/arm/mach-ux500/include/mach/mmc.h
+++ b/arch/arm/mach-ux500/include/mach/mmc.h
@@ -327,8 +327,8 @@ struct u8500_mmci_host {
#define MCI_MAXVOLTTRIAL (200) /* 200 times */
#define MAX_FREQ (24000000)
#define MAX_DATA (64*512)
-#define CLK_MAX 50000000
-#define CLK_DIV 0xFF
+#define MMC_HOST_CLK_MAX 100000000
+#define MMC_CLK_DIV 0xFF
/*
* different card states
*/