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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-05-27 20:43:04 +0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-06 00:15:16 +0100
commit6ebba0e2f56ee77270a9ef8e92c1b4ec38e5f419 (patch)
treea4b4808d0f55eddc41d96cec95a68054e4380b55 /include
parent79e0bc37255a4b934291b4d3ea5a4561fbd78da4 (diff)
downloadlinux-2.6.34-ux500-6ebba0e2f56ee77270a9ef8e92c1b4ec38e5f419.tar.gz
[MIPS] Fix swap entry for MIPS32 36-bit physical address
With 64-bit physical address enabled, 'swapon' was causing kernel oops on Alchemy CPUs (MIPS32) because of the swap entry type field corrupting the _PAGE_FILE bit in 'pte_low' field. So, switch to storing the swap entry in 'pte_high' field using all its bits except _PAGE_GLOBAL and _PAGE_VALID which gives 25 bits for the swap entry offset. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/pgtable-32.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 4d6bc45df59..a5ce3f17a98 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -191,10 +191,17 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#else
/* Swap entries must have VALID and GLOBAL bits cleared. */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __swp_type(x) (((x).val >> 2) & 0x1f)
+#define __swp_offset(x) ((x).val >> 7)
+#define __swp_entry(type,offset) \
+ ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
+#else
#define __swp_type(x) (((x).val >> 8) & 0x1f)
-#define __swp_offset(x) ((x).val >> 13)
+#define __swp_offset(x) ((x).val >> 13)
#define __swp_entry(type,offset) \
- ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+ ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
/*
* Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
@@ -218,7 +225,12 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#endif
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
+#else
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+#endif
#endif /* _ASM_PGTABLE_32_H */