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authorCarlos O'Donell <carlos@codesourcery.com>2010-02-22 23:25:59 +0000
committerKyle McMartin <kyle@redhat.com>2010-02-24 17:30:36 +0000
commit5fd4514bb351b5ecb0da3692fff70741e5ed200c (patch)
tree5322338af64ac728c763f34cf5c2c18633fbf545 /arch/parisc
parent75ef7cdda2daa35be9e070ac8e5258759ac03d06 (diff)
downloadlinux-2.6.34-ux500-5fd4514bb351b5ecb0da3692fff70741e5ed200c.tar.gz
parisc: Set PCI CLS early in boot.
Set the PCI CLS early in the boot process to prevent device failures. In pcibios_set_master use the new pci_cache_line_size instead of a hard-coded value. Signed-off-by: Carlos O'Donell <carlos@codesourcery.com> Reviewed-by: Grant Grundler <grundler@google.com> Signed-off-by: Kyle McMartin <kyle@redhat.com>
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/kernel/pci.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index f7064abc3bb..9e74bfe071d 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -18,7 +18,6 @@
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/cache.h> /* for L1_CACHE_BYTES */
#include <asm/superio.h>
#define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@ static int __init pcibios_init(void)
} else {
printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
}
+
+ /* Set the CLS for PCI as early as possible. */
+ pci_cache_line_size = pci_dfl_cache_line_size;
+
return 0;
}
@@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev)
** upper byte is PCI_LATENCY_TIMER.
*/
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
- (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
+ (0x80 << 8) | pci_cache_line_size);
}