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authorJason Chen <b02280@freescale.com>2012-01-12 15:36:26 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-17 12:17:42 +0800
commit0df5a4fe9bce4eb0afdaea2ef2d3729f56176805 (patch)
tree3879e4d59daa1ad9d2effae94ffda920268a19e8
parent02f39f5c863389db921b93739b5ba001334f1348 (diff)
downloadu-boot-linaro-0df5a4fe9bce4eb0afdaea2ef2d3729f56176805.tar.gz
arm: imx6q: add axi cache and qos setting
Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Eric Miao <eric.miao@linaro.org>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index dff5e4efd..7cf7ef16a 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -54,10 +54,21 @@ void init_aips(void)
writel(0x77777777, reg + 0x04);
}
+void init_axi_cache_qos(void)
+{
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xf00000ff, IOMUXC_BASE_ADDR + 0x010);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007f007f, IOMUXC_BASE_ADDR + 0x018);
+ writel(0x007f007f, IOMUXC_BASE_ADDR + 0x01c);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ init_axi_cache_qos();
+
return 0;
}
#endif