diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2011-12-22 08:42:06 +0100 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2012-01-17 12:19:57 +0800 |
| commit | 7d0bd8e81c0e7bf6b69f4bc235e5a8d8bd456448 (patch) | |
| tree | 5dd3c92944619d0a3664b3f18ad9629801690722 | |
| parent | b585ddf16fdbae1cae51c03550cc36eee8838af1 (diff) | |
mx6qsabrelite: enet: force master, maximize tx clock delay
Register 0x106 is tx data delay register.
With this patch, gigabit mode still does not work reliably.
Ping shows about a 10% packet loss on large packets.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| -rw-r--r-- | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 5c811dec6..b76146d6c 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis) int fecmxc_mii_postcall(int phy) { - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); + /* force master mode */ + miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00); /* min rx data delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + /* min tx data delay */ + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106); + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + /* max rx/tx clock delay, min rx/tx control delay */ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); |