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authorEric Miao <eric.miao@linaro.org>2012-01-17 21:11:54 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-17 21:11:54 +0800
commitc493c61a212aa7599d619ae9d19b9f6af73ff663 (patch)
tree6739705276cde364703736ac78f21c0c6af679f2
parent5878df1b7162cea6b65436b5dedb5f37fc1cc8f3 (diff)
parentdda3e196c5317dfeddd4cc089512c2327b05ff23 (diff)
downloadu-boot-linaro-lt-imx6.tar.gz
Merge branch 'dirkbehme/master_imx6' into lt-imx6lt-imx6
* dirkbehme/master_imx6: (22 commits) imximage: Sort bootops alphabetically imximage: Add support for i.MX6 imximage: Add MX53 to the documentation common/image.c: align usage of fdt_high with initrd_high mx6q: Add fdt_high and initrd_high variables mx6x_pins: fix uart txd definitions mx6qsabrelite: setup uart1 pinmux mx6qsabrelite: add SPI NOR support mx6q: add ECSPI pad settings add imx_ecspi driver fec_mxc: move autonegoatiate restart after mii_postcall fsl_esdhc: fix PIO mode transfers mx6qsabrelite: enet: force master, maximize tx clock delay mx6qsabrelite: add CONFIG_PHY_MICREL_KSZ9021 miiphyutil: add Micrel KSZ9021 support to miiphy_speed fec_mxc: increase autonegotiation timeout fec_mxc: add 1000 Mbps selection mx6qsabrelite: use IMX_GPIO_NR macro i.mx6:imx6q: allign MAC address with burned-in ordering i.mx6q: mx6qarm2: Enable the usboh3 clock ...
-rw-r--r--README8
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c43
-rw-r--r--arch/arm/include/asm/arch-mx6/gpio.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h13
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6x_pins.h50
-rw-r--r--board/freescale/mx6qarm2/imximage.cfg2
-rw-r--r--board/freescale/mx6qsabrelite/imximage.cfg4
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c86
-rw-r--r--common/image.c12
-rw-r--r--common/miiphyutil.c18
-rw-r--r--doc/README.imximage13
-rw-r--r--drivers/mmc/fsl_esdhc.c3
-rw-r--r--drivers/net/fec_mxc.c24
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/imx_ecspi.c334
-rw-r--r--include/configs/mx6qarm2.h2
-rw-r--r--include/configs/mx6qsabrelite.h18
-rw-r--r--include/imx_spi.h97
-rw-r--r--tools/imximage.c8
-rw-r--r--tools/imximage.h2
20 files changed, 658 insertions, 82 deletions
diff --git a/README b/README
index 6fe1e0fc2..f6ab85c5c 100644
--- a/README
+++ b/README
@@ -3627,6 +3627,14 @@ List of environment variables (most likely not complete):
fdt_high - if set this restricts the maximum address that the
flattened device tree will be copied into upon boot.
+ For example, if you have a system with 1 GB memory
+ at physical address 0x10000000, while Linux kernel
+ only recognizes the first 704 MB as low memory, you
+ may need to set fdt_high as 0x3C000000 to have the
+ device tree blob be copied to the maximum address
+ of the 704 MB low memory, so that Linux kernel can
+ access it during the boot procedure.
+
If this is set to the special value 0xFFFFFFFF then
the fdt will not be copied at all on boot. For this
to work it must reside in writable memory, have
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index f9cfefb14..6bb38c85b 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -40,18 +40,35 @@ u32 get_cpu_rev(void)
#ifdef CONFIG_ARCH_CPU_INIT
void init_aips(void)
{
- u32 reg = AIPS1_BASE_ADDR;
+ struct aipstz_regs *aips1, *aips2;
+
+ aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+ aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
- writel(0x77777777, reg + 0x00);
- writel(0x77777777, reg + 0x04);
+ writel(0x77777777, &aips1->mprot0);
+ writel(0x77777777, &aips1->mprot1);
+ writel(0x77777777, &aips2->mprot0);
+ writel(0x77777777, &aips2->mprot1);
- reg = AIPS2_BASE_ADDR;
- writel(0x77777777, reg + 0x00);
- writel(0x77777777, reg + 0x04);
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips1->opacr0);
+ writel(0x00000000, &aips1->opacr1);
+ writel(0x00000000, &aips1->opacr2);
+ writel(0x00000000, &aips1->opacr3);
+ writel(0x00000000, &aips1->opacr4);
+ writel(0x00000000, &aips2->opacr0);
+ writel(0x00000000, &aips2->opacr1);
+ writel(0x00000000, &aips2->opacr2);
+ writel(0x00000000, &aips2->opacr3);
+ writel(0x00000000, &aips2->opacr4);
}
void init_axi_cache_qos(void)
@@ -94,13 +111,15 @@ void imx_get_mac_from_fuse(unsigned char *mac)
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- u32 mac_lo = readl(&fuse->mac_addr_low);
- u32 mac_hi = readl(&fuse->mac_addr_high);
-
- *(u32 *)mac = mac_lo;
+ u32 value = readl(&fuse->mac_addr_high);
+ mac[0] = (value >> 8);
+ mac[1] = value ;
- mac[4] = mac_hi & 0xff;
- mac[5] = (mac_hi >> 8) & 0xff;
+ value = readl(&fuse->mac_addr_low);
+ mac[2] = value >> 24 ;
+ mac[3] = value >> 16 ;
+ mac[4] = value >> 8 ;
+ mac[5] = value ;
}
#endif
diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h
index 20c4e5748..8cfad28fd 100644
--- a/arch/arm/include/asm/arch-mx6/gpio.h
+++ b/arch/arm/include/asm/arch-mx6/gpio.h
@@ -25,6 +25,8 @@
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
+#define IMX_GPIO_NR(port, offset) (((port - 1) << 5) | offset)
+
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 85d55b751..7650cb96b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -214,7 +214,7 @@ struct iim_regs {
u32 crc_value;
u32 rsvd6[3];
u32 version;
- u32 rsvd7[0xd8];
+ u32 rsvd7[0xdb];
struct fuse_bank {
u32 fuse_regs[0x20];
@@ -232,5 +232,16 @@ struct fuse_bank4_regs {
u32 rsvd3[0x13];
};
+struct aipstz_regs {
+ u32 mprot0;
+ u32 mprot1;
+ u32 rsvd[0xe];
+ u32 opacr0;
+ u32 opacr1;
+ u32 opacr2;
+ u32 opacr3;
+ u32 opacr4;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
index b3f613c52..563b77e9c 100644
--- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h
@@ -51,6 +51,12 @@
#define NO_MUX_I 0x3FF
#define NO_PAD_I 0x7FF
+#define SPI_PAD_CTRL (PAD_CTL_HYS \
+ |PAD_CTL_PUS_100K_DOWN \
+ |PAD_CTL_SPEED_MED \
+ |PAD_CTL_DSE_40ohm \
+ |PAD_CTL_SRE_FAST)
+
enum {
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
@@ -146,14 +152,14 @@ enum {
MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, SPI_PAD_CTRL),
MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
+ MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, SPI_PAD_CTRL),
MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
@@ -161,7 +167,7 @@ enum {
MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
+ MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, SPI_PAD_CTRL),
MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
@@ -173,7 +179,7 @@ enum {
MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
- MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
+ MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, SPI_PAD_CTRL),
MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
@@ -220,7 +226,7 @@ enum {
MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
+ MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
@@ -228,7 +234,6 @@ enum {
MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__UART3_TXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
@@ -240,7 +245,7 @@ enum {
MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
+ MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
@@ -248,7 +253,6 @@ enum {
MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
- MX6Q_PAD_EIM_D27__UART2_TXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
@@ -938,7 +942,7 @@ enum {
MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
+ MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
@@ -946,7 +950,6 @@ enum {
MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__UART4_TXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
@@ -956,7 +959,7 @@ enum {
MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
+ MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
@@ -964,7 +967,6 @@ enum {
MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__UART5_TXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
@@ -1085,7 +1087,7 @@ enum {
MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
+ MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
@@ -1093,7 +1095,6 @@ enum {
MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
- MX6Q_PAD_GPIO_8__UART2_TXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0),
MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
@@ -1208,7 +1209,7 @@ enum {
MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
+ MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
@@ -1216,7 +1217,6 @@ enum {
MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
- MX6Q_PAD_CSI0_DAT11__UART1_TXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
@@ -1226,7 +1226,7 @@ enum {
MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
+ MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
@@ -1234,7 +1234,6 @@ enum {
MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__UART4_TXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
@@ -1244,7 +1243,7 @@ enum {
MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
+ MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
@@ -1252,7 +1251,6 @@ enum {
MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__UART5_TXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
@@ -1318,7 +1316,7 @@ enum {
MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
+ MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
@@ -1326,7 +1324,6 @@ enum {
MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__UART1_TXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
@@ -1336,7 +1333,7 @@ enum {
MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
+ MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
@@ -1344,7 +1341,6 @@ enum {
MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__UART2_TXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
@@ -1471,13 +1467,12 @@ enum {
MX6Q_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
MX6Q_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
MX6Q_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__UART3_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
+ MX6Q_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
MX6Q_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
MX6Q_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
MX6Q_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__UART3_TXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0),
MX6Q_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
MX6Q_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
@@ -1578,7 +1573,6 @@ enum {
MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__UART2_TXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
@@ -1605,7 +1599,7 @@ enum {
MX6Q_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__UART2_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
+ MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
MX6Q_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index ffac1b424..5f0ee0d19 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -164,4 +164,4 @@ DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FC
+DATA 4 0x020c4080 0x000003FF
diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
index 8d3848fd2..fa40bff00 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,12 +156,12 @@ DATA 4 0x021b0404 0x00011006
# set the default clock gate to save power
DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FC
+DATA 4 0x020c4080 0x000003FF
# enable AXI cache for VDOA/VPU/IPU
DATA 4 0x020e0010 0xF00000FF
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index e6c12a502..4473b6b60 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -31,6 +31,10 @@
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
+#ifdef CONFIG_IMX_ECSPI
+#include <spi.h>
+#include <imx_spi.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -53,6 +57,11 @@ int dram_init(void)
return 0;
}
+iomux_v3_cfg_t uart1_pads[] = {
+ MX6Q_PAD_SD3_DAT6__UART1_RXD,
+ MX6Q_PAD_SD3_DAT7__UART1_TXD,
+};
+
iomux_v3_cfg_t uart2_pads[] = {
MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -117,22 +126,23 @@ iomux_v3_cfg_t enet_pads2[] = {
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static void setup_iomux_enet(void)
{
- gpio_direction_output(87, 0); /* GPIO 3-23 */
- gpio_direction_output(190, 1); /* GPIO 6-30 */
- gpio_direction_output(185, 1); /* GPIO 6-25 */
- gpio_direction_output(187, 1); /* GPIO 6-27 */
- gpio_direction_output(188, 1); /* GPIO 6-28*/
- gpio_direction_output(189, 1); /* GPIO 6-29 */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
- gpio_direction_output(184, 1); /* GPIO 6-24 */
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
udelay(1000 * 10);
- gpio_direction_output(87, 1); /* GPIO 3-23 */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}
@@ -148,11 +158,11 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
- gpio_direction_input(192); /*GPIO7_0*/
- *cd = gpio_get_value(192);
+ gpio_direction_input(IMX_GPIO_NR(7, 0));
+ *cd = gpio_get_value(IMX_GPIO_NR(7, 0));
} else {
- gpio_direction_input(38); /*GPIO2_6*/
- *cd = gpio_get_value(38);
+ gpio_direction_input(IMX_GPIO_NR(2, 6));
+ *cd = gpio_get_value(IMX_GPIO_NR(2, 6));
}
return 0;
@@ -187,19 +197,63 @@ int board_mmc_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_IMX_ECSPI
+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
+{
+ int rval = 0 ;
+ if (1 == dev->slave.cs) {
+ dev->base = ECSPI1_BASE_ADDR;
+ dev->ss = 1 ;
+ dev->ss_pol = IMX_SPI_ACTIVE_LOW; /* SPI NOR */
+ dev->freq = 25000000;
+ dev->fifo_sz = 64 * 4;
+ dev->us_delay = 0;
+ } else {
+ printf("%s: invalid chip select %d\n", __func__, dev->slave.cs);
+ rval = -EINVAL ;
+ }
+ return rval;
+}
+
+void spi_io_init(struct imx_spi_dev_t *dev, int active)
+{
+ if (dev->ss == 1)
+ gpio_set_value(IMX_GPIO_NR(3, 19), active ? 0 : 1);
+}
+
+iomux_v3_cfg_t mx6q_ecspi1_pads[] = {
+ /* SS1 */
+ MX6Q_PAD_EIM_D19__GPIO_3_19,
+ MX6Q_PAD_EIM_D17__ECSPI1_MISO,
+ MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
+ MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
+};
+
+void setup_spi(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+ imx_iomux_v3_setup_multiple_pads(mx6q_ecspi1_pads,
+ ARRAY_SIZE(mx6q_ecspi1_pads));
+}
+#endif
+
#define MII_1000BASET_CTRL 0x9
#define MII_EXTENDED_CTRL 0xb
#define MII_EXTENDED_DATAW 0xc
int fecmxc_mii_postcall(int phy)
{
- /* prefer master mode */
- miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
+ /* force master mode */
+ miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
/* min rx data delay */
miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+ /* min tx data delay */
+ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
+ miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+
/* max rx/tx clock delay, min rx/tx control delay */
miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);
@@ -247,7 +301,9 @@ int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
+#ifdef CONFIG_IMX_ECSPI
+ setup_spi();
+#endif
return 0;
}
diff --git a/common/image.c b/common/image.c
index 77ca6e470..8c4137c60 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1288,16 +1288,14 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
if (((ulong) desired_addr) == ~0UL) {
/* All ones means use fdt in place */
- desired_addr = fdt_blob;
+ of_start = fdt_blob;
+ lmb_reserve(lmb, (ulong)of_start, of_len);
disable_relocation = 1;
- }
- if (desired_addr) {
+ } else if (desired_addr) {
of_start =
(void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
- ((ulong)
- desired_addr)
- + of_len);
- if (desired_addr && of_start != desired_addr) {
+ (ulong)desired_addr);
+ if (of_start == 0) {
puts("Failed using fdt_high value for Device Tree");
goto error;
}
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 2cc23b410..8cb474814 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr)
(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
return _1000BASET;
#endif /* CONFIG_PHY_GIGE */
-
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+#define MII_PHY_CTL 0x1f
+#define MII_PHY_CTL_1000 (1 << 6)
+#define MII_PHY_CTL_100 (1 << 5)
+#define MII_PHY_CTL_10 (1 << 4)
+ u16 btsr;
+ if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
+ printf("PHY 1000BT status");
+ goto miiphy_read_failed;
+ }
+ if (btsr & MII_PHY_CTL_1000)
+ return _1000BASET;
+ if (btsr & MII_PHY_CTL_100)
+ return _100BASET;
+ if (btsr & MII_PHY_CTL_10)
+ return _10BASET;
+#endif
/* Check Basic Management Control Register first. */
if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
printf("PHY speed");
diff --git a/doc/README.imximage b/doc/README.imximage
index c74239d2a..073e3fcb3 100644
--- a/doc/README.imximage
+++ b/doc/README.imximage
@@ -2,12 +2,13 @@
Imximage Boot Image generation using mkimage
---------------------------------------------
-This document describes how to set up a U-Boot image
-that can be booted by Freescale MX25, MX35 and MX51
-processors via internal boot mode.
+This document describes how to set up a U-Boot image that can be booted
+by Freescale MX25, MX35, MX51, MX53 and MX6 processors via internal boot
+mode.
These processors can boot directly from NAND, SPI flash and SD card flash
-using its internal boot ROM support. They can boot from an internal
+using its internal boot ROM support. MX6 processors additionally support
+boot from NOR flash and SATA disks. All processors can boot from an internal
UART, if booting from device media fails.
Booting from NOR flash does not require to use this image type.
@@ -59,12 +60,12 @@ Configuration command line syntax:
-------------- -----------
IMXIMAGE_VERSION 1/2
1 is for mx25/mx35/mx51 compatible,
- 2 is for mx53 compatible,
+ 2 is for mx53/mx6 compatible,
others is invalid and error is generated.
This command need appear the fist before
other valid commands in configuration file.
- BOOT_FROM nand/spi/sd/onenand
+ BOOT_FROM nand/spi/sd/onenand/nor/sata
Example:
BOOT_FROM spi
DATA type address value
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ddd1b4c6f..30db030b7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -114,7 +114,8 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
- struct fsl_esdhc *regs = mmc->priv;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
uint blocks;
char *buffer;
uint databuf;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3affda8fa..24ef418a3 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
LPA_100FULL | LPA_100HALF | LPA_10FULL |
LPA_10HALF | PHY_ANLPAR_PSB_802_3);
- miiphy_write(dev->name, fec->phy_id, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-
if (fec->mii_postcall)
ret = fec->mii_postcall(fec->phy_id);
+ miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+
return ret;
}
@@ -226,7 +226,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
*/
start = get_timer(0);
do {
- if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+ if (get_timer(start) > (CONFIG_SYS_HZ * 10)) {
printf("%s: Autonegotiation timeout\n", dev->name);
return -1;
}
@@ -378,6 +378,7 @@ static int fec_set_hwaddr(struct eth_device *dev)
static int fec_open(struct eth_device *edev)
{
struct fec_priv *fec = (struct fec_priv *)edev->priv;
+ int speed;
debug("fec_open: fec_open(dev)\n");
/* full-duplex, heartbeat disabled */
@@ -427,8 +428,21 @@ static int fec_open(struct eth_device *edev)
#endif
miiphy_wait_aneg(edev);
- miiphy_speed(edev->name, fec->phy_id);
+ speed = miiphy_speed(edev->name, fec->phy_id);
miiphy_duplex(edev->name, fec->phy_id);
+#ifdef CONFIG_MX6Q
+ {
+ u32 ecr = readl(&fec->eth->ecntrl) & ~(0x1 << 5);
+ u32 rcr = (readl(&fec->eth->r_cntrl) & ~0x300) | 0x44;
+ if (speed == _1000BASET)
+ ecr |= (0x1 << 5);
+ else if (speed != _100BASET)
+ rcr |= (0x1 << 9);
+ writel(ecr, &fec->eth->ecntrl);
+ writel(rcr, &fec->eth->r_cntrl);
+ }
+#endif
+ printf("%s:Speed=%i\n", __func__, speed);
/*
* Enable SmartDMA receive task
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6f389f093..b2c310b31 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_IMX_ECSPI) += imx_ecspi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/imx_ecspi.c b/drivers/spi/imx_ecspi.c
new file mode 100644
index 000000000..146820873
--- /dev/null
+++ b/drivers/spi/imx_ecspi.c
@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/clock.h>
+#include <imx_spi.h>
+
+static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct imx_spi_dev_t, slave);
+}
+
+static s32 spi_reset(struct spi_slave *slave)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ u32 pre_div = 0, post_div = 0, reg_ctrl, reg_config;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *reg = &(dev->reg);
+
+ if (dev->freq == 0) {
+ printf("Error: desired clock is 0\n");
+ return 1;
+ }
+
+ reg_ctrl = readl(dev->base + SPI_CON_REG);
+ reg_config = readl(dev->base + SPI_CFG_REG);
+ /* Reset spi */
+ writel(0, dev->base + SPI_CON_REG);
+ writel((reg_ctrl | 0x1), dev->base + SPI_CON_REG);
+
+ /* Control register setup */
+ pre_div = (clk_src + dev->freq - 1) / dev->freq;
+ while (pre_div > 16) {
+ pre_div = (pre_div + 1) >> 1;
+ post_div++;
+ }
+ if (post_div > 0x0f) {
+ printf("Error: no divider can meet the freq: %d\n", dev->freq);
+ return -1;
+ }
+ if (pre_div)
+ pre_div--;
+
+ debug("pre_div = %d, post_div=%d, clk_src=%d, spi_freq=%d\n", pre_div,
+ post_div, clk_src, (clk_src/(pre_div + 1)) >> post_div);
+ reg_ctrl &= ~((3 << 18) | (0xF << 12) | (0xF << 8));
+ reg_ctrl |= (dev->ss << 18);
+ reg_ctrl |= (pre_div << 12);
+ reg_ctrl |= (post_div << 8);
+ reg_ctrl |= (1 << (dev->ss + 4)); /* always set to master mode */
+ reg_ctrl |= 1;
+
+ /* configuration register setup */
+ reg_config &= ~(0x111111 << dev->ss);
+ reg_config |= (dev->in_sctl << (dev->ss + 20));
+ reg_config |= (dev->in_dctl << (dev->ss + 16));
+ reg_config |= (dev->ss_pol << (dev->ss + 12));
+ reg_config |= (dev->ssctl << (dev->ss + 8));
+ reg_config |= (dev->sclkpol << (dev->ss + 4));
+ reg_config |= (dev->sclkpha << (dev->ss));
+
+ reg_config &= 0x0f << 12 ;
+ reg_config |= (dev->ss_pol)<<(12+dev->ss);
+ debug("ss%x, reg_config = 0x%x\n", dev->ss, reg_config);
+ writel(reg_config, dev->base + SPI_CFG_REG);
+ debug("ss%x, reg_ctrl = 0x%x\n", dev->ss, reg_ctrl);
+ writel(reg_ctrl & ~1, dev->base + SPI_CON_REG);
+
+ /* save config register and control register */
+ reg->cfg_reg = reg_config;
+ reg->ctrl_reg = reg_ctrl;
+
+ /* clear interrupt reg */
+ writel(0, dev->base + SPI_INT_REG);
+ writel(3 << 6, dev->base + SPI_STAT_REG);
+ return 0;
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct imx_spi_dev_t *imx_spi_slave = NULL;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ imx_spi_slave = (struct imx_spi_dev_t *)
+ calloc(sizeof(struct imx_spi_dev_t), 1);
+ if (!imx_spi_slave)
+ return NULL;
+
+ imx_spi_slave->slave.bus = bus;
+ imx_spi_slave->slave.cs = cs;
+
+ spi_get_cfg(imx_spi_slave);
+
+ if (max_hz < imx_spi_slave->freq)
+ imx_spi_slave->freq = max_hz ;
+ spi_io_init(imx_spi_slave, 0);
+
+ spi_reset(&(imx_spi_slave->slave));
+
+ return &(imx_spi_slave->slave);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *imx_spi_slave;
+
+ if (slave) {
+ imx_spi_slave = to_imx_spi_slave(slave);
+ free(imx_spi_slave);
+ }
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+
+}
+
+/*
+ * SPI xchg
+ */
+
+int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
+ const u8 *dout, u8 *din, unsigned long flags)
+{
+ int nbytes = (bitlen + 7) / 8;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *spi_reg = &(dev->reg);
+ u32 loop_cnt ;
+ if (!slave)
+ return -1;
+
+ if (spi_reg->ctrl_reg == 0) {
+ printf("Error: spi(base=0x%x) has not been initialized yet\n",
+ dev->base);
+ return -1;
+ }
+ spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~0xFFF00000) | \
+ ((bitlen - 1) << 20);
+
+ writel(spi_reg->ctrl_reg, dev->base + SPI_CON_REG);
+ writel(spi_reg->cfg_reg, dev->base + SPI_CFG_REG);
+
+ /* move data to the tx fifo */
+ debug("dout=0x%p, bitlen=%x\n", dout, bitlen);
+
+ /*
+ * The SPI controller works only with words,
+ * check if less than a word is sent.
+ * Access to the FIFO is only 32 bit
+ */
+ if (bitlen % 32) {
+ u32 data = 0;
+ u32 cnt = (bitlen % 32) / 8;
+ if (dout) {
+ int i ;
+ for (i = 0; i < cnt; i++)
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ debug("Sending SPI 0x%x\n", data);
+
+ writel(data, dev->base + SPI_TX_DATA);
+ nbytes -= cnt;
+ }
+
+ while (nbytes > 0) {
+ u32 data = 0;
+ if (dout) {
+ /* Buffer is not 32-bit aligned */
+ if ((unsigned long)dout & 0x03) {
+ int i ;
+ data = 0;
+ for (i = 0; i < 4; i++)
+ data = (data << 8) | (*dout++ & 0xFF);
+ } else {
+ data = *(u32 *)dout;
+ data = cpu_to_be32(data);
+ }
+ dout += 4;
+ }
+ debug("Sending SPI 0x%x\n", data);
+ writel(data, dev->base + SPI_TX_DATA);
+ nbytes -= 4;
+ }
+
+ writel(spi_reg->ctrl_reg | (1 << 2), dev->base + SPI_CON_REG);
+
+ loop_cnt = SPI_RETRY_TIMES ;
+ /* poll on the TC bit (transfer complete) */
+ while ((readl(dev->base + SPI_STAT_REG) & (1 << 7)) == 0) {
+ loop_cnt--;
+ if (loop_cnt <= 0) {
+ printf("%s: Error: re-tried %d times\n",
+ __func__, SPI_RETRY_TIMES);
+ bitlen = 0 ;
+ spi_cs_deactivate(slave);
+ return -1;
+ }
+ udelay(100);
+ }
+
+ /* clear the TC bit */
+ writel(3 << 6, dev->base + SPI_STAT_REG);
+
+ nbytes = (bitlen + 7) / 8;
+
+ if (bitlen % 32) {
+ u32 data = readl(dev->base + SPI_RX_DATA);
+ u32 cnt = (bitlen % 32) / 8;
+ data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
+ debug("SPI Rx unaligned: 0x%x\n", data);
+ if (din) {
+ memcpy(din, &data, cnt);
+ din += cnt;
+ }
+ nbytes -= cnt;
+ }
+
+ while (nbytes > 0) {
+ u32 tmp = readl(dev->base + SPI_RX_DATA);
+ u32 data = cpu_to_be32(tmp);
+ u32 cnt = min(nbytes, sizeof(data));
+ debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
+ if (din) {
+ memcpy(din, &data, cnt);
+ din += cnt;
+ }
+ nbytes -= cnt;
+ }
+
+ return 0;
+}
+
+/*
+ * SPI transfer:
+ *
+ * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
+ * for more informations.
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ int n_bytes = (bitlen + 7) / 8;
+ int n_bits;
+ int ret;
+ u32 blk_size;
+ u8 *p_outbuf = (u8 *)dout;
+ u8 *p_inbuf = (u8 *)din;
+
+ if (!slave)
+ return -1;
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ while (n_bytes > 0) {
+ if (n_bytes < MAX_SPI_BYTES)
+ blk_size = n_bytes;
+ else
+ blk_size = MAX_SPI_BYTES;
+
+ n_bits = blk_size * 8;
+
+ ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
+
+ if (ret)
+ return ret;
+ if (dout)
+ p_outbuf += blk_size;
+ if (din)
+ p_inbuf += blk_size;
+ n_bytes -= blk_size;
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+
+ spi_io_init(dev, 1);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ spi_io_init(dev, 0);
+ writel(0, dev->base + SPI_CON_REG);
+}
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 3a3067993..835218e77 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -87,6 +87,8 @@
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"mmcdev=1\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 86b25d94f..fa14d6cb0 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,21 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CMD_SF
+/*
+ * SPI Configs
+ */
+#ifdef CONFIG_CMD_SF
+ #define CONFIG_FSL_SF 1
+ #define CONFIG_SPI_FLASH 1
+ #define CONFIG_SPI_FLASH_SST 1
+ #define CONFIG_SPI_FLASH_CS 1
+ #define CONFIG_IMX_ECSPI
+ #define IMX_CSPI_VER_2_3 1
+
+ #define MAX_SPI_BYTES (64 * 4)
+#endif
+
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
@@ -66,6 +81,7 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHY_MICREL_KSZ9021
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@@ -87,6 +103,8 @@
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttymxc3\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
diff --git a/include/imx_spi.h b/include/imx_spi.h
new file mode 100644
index 000000000..32544d9f5
--- /dev/null
+++ b/include/imx_spi.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX_SPI_H__
+#define __IMX_SPI_H__
+
+#include <spi.h>
+
+#undef IMX_SPI_DEBUG
+
+#define IMX_SPI_ACTIVE_HIGH 1
+#define IMX_SPI_ACTIVE_LOW 0
+#define SPI_RETRY_TIMES 100
+
+#if defined(IMX_CSPI_VER_0_7)
+ #define SPI_RX_DATA 0x0
+ #define SPI_TX_DATA 0x4
+ #define SPI_CON_REG 0x8
+ #define SPI_INT_REG 0xC
+ #define SPI_DMA_REG 0x10
+ #define SPI_STAT_REG 0x14
+ #define SPI_PERIOD_REG 0x18
+
+ #define SPI_CTRL_EN (1 << 0)
+ #define SPI_CTRL_MODE (1 << 1)
+ #define SPI_CTRL_REG_XCH_BIT (1 << 2)
+ #define SPI_CTRL_SSPOL (1 << 7)
+ #define SPI_CTRL_SSPOL_OFF (7)
+ #define SPI_CTRL_SSCTL (1 << 6)
+ #define SPI_CTRL_SSCTL_OFF (6)
+ #define SPI_CTRL_SCLK_POL (1 << 4)
+ #define SPI_CTRL_SCLK_POL_OFF (4)
+ #define SPI_CTRL_SCLK_PHA (1 << 5)
+ #define SPI_CTRL_SCLK_PHA_OFF (5)
+ #define SPI_CTRL_SS_OFF (12)
+ #define SPI_CTRL_SS_MASK (3 << 12)
+ #define SPI_CTRL_DATA_OFF (16)
+ #define SPI_CTRL_DATA_MASK (7 << 16)
+ #define SPI_CTRL_BURST_OFF (20)
+ #define SPI_CTRL_BURST_MASK (0xFFF << 20)
+ #define SPI_INT_STAT_TC (1 << 7)
+
+#elif defined(IMX_CSPI_VER_2_3)
+ #define SPI_RX_DATA 0x0
+ #define SPI_TX_DATA 0x4
+ #define SPI_CON_REG 0x8
+ #define SPI_CFG_REG 0xC
+ #define SPI_INT_REG 0x10
+ #define SPI_DMA_REG 0x14
+ #define SPI_STAT_REG 0x18
+ #define SPI_PERIOD_REG 0x1C
+#endif
+
+struct spi_reg_t {
+ u32 ctrl_reg;
+ u32 cfg_reg;
+};
+
+struct imx_spi_dev_t {
+ struct spi_slave slave;
+ u32 base; /* base address of SPI module */
+ u32 freq; /* desired clock freq in Hz for this device */
+ u32 ss_pol; /* ss polarity: 1=active high; 0=active low */
+ u32 ss; /* slave select */
+ u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */
+ u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */
+ u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */
+ u32 sclkpol; /* sclk polarity: active high=0; active low=1 */
+ u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */
+ u32 fifo_sz; /* fifo size in bytes for either tx or rx. */
+ u32 us_delay; /* us delay in each xfer */
+ struct spi_reg_t reg; /* pointer to a set of SPI registers */
+};
+
+extern void spi_io_init(struct imx_spi_dev_t *dev, int active);
+extern s32 spi_get_cfg(struct imx_spi_dev_t *dev);
+
+#endif /* __IMX_SPI_H__ */
diff --git a/tools/imximage.c b/tools/imximage.c
index 8e81bdb9c..1e0f5d4e5 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -47,10 +47,12 @@ static table_entry_t imximage_cmds[] = {
* this is needed to set the correct flash offset
*/
static table_entry_t imximage_bootops[] = {
- {FLASH_OFFSET_SPI, "spi", "SPI Flash", },
+ {FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",},
{FLASH_OFFSET_NAND, "nand", "NAND Flash", },
+ {FLASH_OFFSET_NOR, "nor", "NOR Flash", },
+ {FLASH_OFFSET_SATA, "sata", "SATA Disk", },
{FLASH_OFFSET_SD, "sd", "SD Card", },
- {FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",},
+ {FLASH_OFFSET_SPI, "spi", "SPI Flash", },
{-1, "", "Invalid", },
};
@@ -59,7 +61,7 @@ static table_entry_t imximage_bootops[] = {
*/
static table_entry_t imximage_versions[] = {
{IMXIMAGE_V1, "", " (i.MX25/35/51 compatible)", },
- {IMXIMAGE_V2, "", " (i.MX53 compatible)", },
+ {IMXIMAGE_V2, "", " (i.MX53/6 compatible)", },
{-1, "", " (Invalid)", },
};
diff --git a/tools/imximage.h b/tools/imximage.h
index d126a46a7..d784a8d2e 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -37,6 +37,8 @@
#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_ONENAND 0x100
+#define FLASH_OFFSET_NOR 0x1000
+#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40