From c15f3120eca5359ed7ec1a359085312bbafca169 Mon Sep 17 00:00:00 2001 From: wdenk Date: Sun, 10 Oct 2004 22:44:24 +0000 Subject: * Patch by Michael Bendzick, 30 Aug 2004: - Improve platform.S code for omap1510inn that detects whether code is running from SDRAM or not. Patch allows SDRAM to be configured if code is running out of SRAM at 0x20000000. * Patch by Frederick Klatt, 30 Aug 2004: Add support for the Wind River SBC8540/SBC8560 boards --- doc/README.SBC8560 | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 doc/README.SBC8560 (limited to 'doc/README.SBC8560') diff --git a/doc/README.SBC8560 b/doc/README.SBC8560 new file mode 100644 index 000000000..83f2640ba --- /dev/null +++ b/doc/README.SBC8560 @@ -0,0 +1,55 @@ +The port was tested on Wind River System Sbc8560 board . U-Boot was +installed on the flash memory of the CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and setup the +appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. Refer +to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which select +the on-board FLASH device (Intel 28F128Jx); 2) The settings for the Clock SW9 (33 MHz +or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the + target JTAG port. This includes running the SBC8560 register script. + Make sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler. Further, it seems the ppc_8xx compiler is + required for the 85xx (no 85xx designated compiler in ELDK3.0) + +3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter). + The bin file should be converted from fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Do a "dc clr" [visionClick] to load the default register settings + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program + -- cgit v1.2.3