From 71665ebf88408ff2acb762af47989fd4365b321a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 3 Mar 2008 17:27:02 +0100 Subject: ppc4xx: Add Canyonlands NAND booting support 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese --- board/amcc/canyonlands/init.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board/amcc/canyonlands/init.S') diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 5d4884727..b7cac23cc 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -46,7 +46,12 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ +#ifndef CONFIG_NAND_SPL tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ +#else + tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) +#endif /* * TLB entries for SDRAM are not needed on this platform. @@ -78,7 +83,7 @@ tlbtab: tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) /* TLB-entry for OCM */ - tlbentry(CFG_OCM_BASE, SZ_4K, 0x00040000, 4, AC_R|AC_W|AC_X) + tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) /* TLB-entry for Local Configuration registers => peripherals */ tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) -- cgit v1.2.3