diff options
Diffstat (limited to 'board/eNET/eNET.c')
| -rw-r--r-- | board/eNET/eNET.c | 192 |
1 files changed, 107 insertions, 85 deletions
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 7f0e2577f..dd0ce5451 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -35,76 +35,52 @@ DECLARE_GLOBAL_DATA_PTR; -#undef SC520_CDP_DEBUG - -#ifdef SC520_CDP_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; - static void enet_timer_isr(void); static void enet_toggle_run_led(void); - -void init_sc520_enet (void) -{ - /* Set CPU Speed to 100MHz */ - writeb(0x01, &sc520_mmcr->cpuctl); - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "0: pushl %%ecx\n" - "popl %%ecx\n" - "loop 0b\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} +static void enet_setup_pars(void); /* * Miscellaneous platform dependent initializations */ int board_early_init_f(void) { - init_sc520_enet(); - - writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ - writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ - writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ - writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ - writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ - writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ - writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ - - writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ - writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ - writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ - writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ - writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ - writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ - writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ - - writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ - writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ - writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ - writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ - writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ -/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ -/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + u16 pio_out_cfg = 0x0000; + + /* Configure General Purpose Bus timing */ + writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt); + writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw); + writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff); + writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw); + writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff); + writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw); + writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff); + + /* Configure Programmable Input/Output Pins */ + writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0); + writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16); + writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16); + writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0); + writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs); + writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel); + + /* + * Turn off top board + * Set StrataFlash chips to 16-bit width + * Set StrataFlash chips to normal (non reset/power down) mode + */ + pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR; + pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH; + pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE; + pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE; + writew(pio_out_cfg, &sc520_mmcr->pioset15_0); + + /* Turn off auxiliary power output */ + writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0); + + /* Clear FPGA program mode */ + writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16); + + enet_setup_pars(); /* Disable Watchdog */ writew(0x3333, &sc520_mmcr->wdtmrctl); @@ -112,19 +88,67 @@ int board_early_init_f(void) writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ - writew(0x0033, &sc520_mmcr->bootcsctl); - writew(0x0615, &sc520_mmcr->romcs1ctl); - writew(0x0615, &sc520_mmcr->romcs2ctl); + writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl); + writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl); + writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl); + + writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl); + writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl); + writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl); + + writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl); + writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb); - writeb(0x00, &sc520_mmcr->adddecctl); - writeb(0x07, &sc520_mmcr->uart1ctl); - writeb(0x07, &sc520_mmcr->uart2ctl); - writeb(0x06, &sc520_mmcr->sysarbctl); - writew(0x0003, &sc520_mmcr->sysarbmenb); + /* enable posted-writes */ + writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl); return 0; } +static void enet_setup_pars(void) +{ + /* + * PARs 11 and 12 are 2MB SRAM @ 0x19000000 + * + * These are setup now because older version of U-Boot have them + * mapped to a different PAR which gets clobbered which prevents + * using SRAM for warm-booting a new image + */ + writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]); + writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]); + + /* PARs 0 and 1 are Compact Flash slots (4kB each) */ + writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]); + writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]); + + /* PAR 2 is used for Cache-As-RAM */ + + /* + * PARs 5 through 8 are additional NS16550 UARTS + * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8 + */ + writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]); + writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]); + writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]); + writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]); + + /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */ + writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]); + writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]); + + /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */ + writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]); + + /* + * PAR 14 is Low Level I/O (LEDs, Hex Switches etc) + * Already configured in board_init16 (eNET_start16.S) + * + * PAR 15 is Boot ROM + * Already configured in board_init16 (eNET_start16.S) + */ +} + + int board_early_init_r(void) { /* CPU Speed to 100MHz */ @@ -136,12 +160,6 @@ int board_early_init_r(void) return 0; } -int dram_init(void) -{ - init_sc520_dram(); - return 0; -} - void show_boot_progress(int val) { uchar led_mask; @@ -165,22 +183,23 @@ int last_stage_init(void) outb(0x00, LED_LATCH_ADDRESS); - register_timer_isr (enet_timer_isr); + register_timer_isr(enet_timer_isr); printf("Serck Controls eNET\n"); return 0; } -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) { if (banknum == 0) { /* non-CFI boot flash */ info->portwidth = FLASH_CFI_8BIT; info->chipwidth = FLASH_CFI_BY8; info->interface = FLASH_CFI_X8; return 1; - } else + } else { return 0; + } } int board_eth_init(bd_t *bis) @@ -204,10 +223,18 @@ void setup_pcat_compatibility() */ writew(0x0000,&sc520_mmcr->intpinpol); - /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + /* + * PIT 0 -> IRQ0 + * RTC -> IRQ8 + * FP error -> IRQ13 + * UART1 -> IRQ4 + * UART2 -> IRQ3 + */ writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]); + writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]); /* Disable all other interrupt sources */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); @@ -215,11 +242,6 @@ void setup_pcat_compatibility() writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ - writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); |