diff options
| author | Wolfram Sang <w.sang@pengutronix.de> | 2010-09-09 13:54:41 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2010-09-13 14:43:05 -0500 |
| commit | 1075b07e2c67c1f504d9f3a6f1b9aaa8f81393b2 (patch) | |
| tree | daa80f7b0e2bb3c73c5d69fb5c028462d357675e /drivers | |
| parent | 150f723665674100876c53e0492cd6d2191fe865 (diff) | |
nand/davinci: make sure ECC calculation has really started
Due to a register glitch (result code <4 might show up right after the
start-calculation-bit was set), make sure the ECC has really started.
See 1c3275b656045aff9a75bb2c9f3251af1043ebb3 in the kernel.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/davinci_nand.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 4ca738e45..c5a86d6c0 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -484,7 +484,20 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, __raw_writel(1 << 13, &davinci_emif_regs->nandfcr); /* - * Wait for the corr_state field (bits 8 to 11)in the + * Wait for the corr_state field (bits 8 to 11) in the + * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3. + * Otherwise ECC calculation has not even begun and the next loop might + * fail because of a false positive! + */ + i = NAND_TIMEOUT; + do { + val = __raw_readl(&davinci_emif_regs->nandfsr); + val &= 0xc00; + i--; + } while ((i > 0) && !val); + + /* + * Wait for the corr_state field (bits 8 to 11) in the * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3. */ i = NAND_TIMEOUT; |