fsl/85xx, 86xx: Sync up DMA code

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 331fcc09a..d88c56462 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -269,9 +269,9 @@ void dma_init(void) {
 	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr = 0x02c40000;
-	dma->datr = 0x02c40000;
-	dma->sr = 0xfffffff; /* clear any errors */
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
@@ -286,7 +286,7 @@ uint dma_check(void) {
 		status = dma->sr;
 	}
 
-	/* clear MR0[CS] channel start bit */
+	/* clear MR[CS] channel start bit */
 	dma->mr &= 0x00000001;
 	asm("sync;isync;msync");