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authorStefan Roese <sr@denx.de>2010-11-26 15:45:22 +0100
committerStefan Roese <sr@denx.de>2010-11-28 11:06:47 +0100
commit28e94bb2f7b796f58587752ab018b7d23fdc9061 (patch)
treed753ad2372c254ea98e9c53ddc97fbe0a429e7ea
parent844f07d8a1f1330c97631b23fbf6425db2dc1508 (diff)
downloadu-boot-linaro-natty-28e94bb2f7b796f58587752ab018b7d23fdc9061.tar.gz
ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST
This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test. When cache is enabled in the SDRAM area, the values written to SDRAM need to be flushed from cache to SDRAM using the dcfb instruction. Without this patch the POST ECC test failed. Now its working again on platforms with cache enabled in SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--post/cpu/ppc4xx/denali_ecc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 50ae7fb8f..6d1463559 100644
--- a/post/cpu/ppc4xx/denali_ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -174,6 +174,7 @@ static int test_ecc(uint32_t ecc_addr)
clear_and_enable_ecc();
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
/* Verify no ECC error reading back */
value = in_be32(ecc_mem);
@@ -193,6 +194,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Test for correctable error by creating a one-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
@@ -212,6 +214,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Test for uncorrectable error by creating a two-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
@@ -232,6 +235,7 @@ static int test_ecc(uint32_t ecc_addr)
/* Remove error from SDRAM and enable ECC. */
out_be32(ecc_mem, ECC_PATTERN);
+ ppcDcbf((u32)ecc_mem);
clear_and_enable_ecc();
return ret;