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authorJohn Rigby <john.rigby@linaro.org>2011-02-24 09:11:11 -0700
committerJohn Rigby <john.rigby@linaro.org>2011-02-24 09:33:57 -0700
commitaf329cc89a5466a686e81d87d5507b25526b9155 (patch)
treed29f479474462d914700e41f6b793fe7048b7b3d
parentd68c7335baa78d015171c6387ce330d9fa17f1f8 (diff)
parentc7977858dcf1f656cbe91ea0dc3cb9139c6a8cc8 (diff)
downloadu-boot-linaro-natty-af329cc89a5466a686e81d87d5507b25526b9155.tar.gz
Merge current upstream
Signed-off-by: John Rigby <john.rigby@linaro.org>
-rw-r--r--MAINTAINERS11
-rw-r--r--Makefile90
-rw-r--r--README22
-rw-r--r--arch/arm/cpu/arm1136/start.S18
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/Makefile46
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/cpu.c78
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/dram.c132
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/timer.c214
-rw-r--r--arch/arm/cpu/arm926ejs/start.S2
-rw-r--r--arch/arm/cpu/armv7/tegra2/Makefile (renamed from board/ms7720se/config.mk)42
-rw-r--r--arch/arm/cpu/armv7/tegra2/board.c88
-rw-r--r--arch/arm/cpu/armv7/tegra2/config.mk (renamed from board/ms7750se/config.mk)17
-rw-r--r--arch/arm/cpu/armv7/tegra2/lowlevel_init.S65
-rw-r--r--arch/arm/cpu/armv7/tegra2/sys_info.c (renamed from board/dbau1x00/flash.c)26
-rw-r--r--arch/arm/cpu/armv7/tegra2/timer.c122
-rw-r--r--arch/arm/include/asm/arch-armada100/config.h44
-rw-r--r--arch/arm/include/asm/arch-kirkwood/config.h145
-rw-r--r--arch/arm/include/asm/arch-pantheon/config.h38
-rw-r--r--arch/arm/include/asm/arch-pantheon/cpu.h79
-rw-r--r--arch/arm/include/asm/arch-pantheon/mfp.h41
-rw-r--r--arch/arm/include/asm/arch-pantheon/pantheon.h54
-rw-r--r--arch/arm/include/asm/arch-tegra2/clk_rst.h165
-rw-r--r--arch/arm/include/asm/arch-tegra2/pinmux.h55
-rw-r--r--arch/arm/include/asm/arch-tegra2/pmc.h124
-rw-r--r--arch/arm/include/asm/arch-tegra2/sys_proto.h (renamed from board/gdsys/common/fpga.h)22
-rw-r--r--arch/arm/include/asm/arch-tegra2/tegra2.h49
-rw-r--r--arch/arm/include/asm/arch-tegra2/uart.h47
-rw-r--r--arch/arm/include/asm/io.h6
-rw-r--r--arch/arm/include/asm/mach-types.h1291
-rw-r--r--arch/arm/lib/bootm.c4
-rw-r--r--arch/i386/config.mk15
-rw-r--r--arch/i386/cpu/config.mk10
-rw-r--r--arch/i386/cpu/cpu.c35
-rw-r--r--arch/i386/cpu/interrupts.c19
-rw-r--r--arch/i386/cpu/sc520/Makefile5
-rw-r--r--arch/i386/cpu/sc520/sc520.c148
-rw-r--r--arch/i386/cpu/sc520/sc520_asm.S615
-rw-r--r--arch/i386/cpu/sc520/sc520_car.S94
-rw-r--r--arch/i386/cpu/sc520/sc520_sdram.c532
-rw-r--r--arch/i386/cpu/start.S107
-rw-r--r--arch/i386/cpu/start16.S5
-rw-r--r--arch/i386/cpu/u-boot.lds (renamed from board/eNET/u-boot.lds)24
-rw-r--r--arch/i386/include/asm/global_data.h21
-rw-r--r--arch/i386/include/asm/ic/sc520.h93
-rw-r--r--arch/i386/include/asm/processor-flags.h100
-rw-r--r--arch/i386/include/asm/processor.h9
-rw-r--r--arch/i386/include/asm/u-boot-i386.h3
-rw-r--r--arch/i386/lib/board.c146
-rw-r--r--arch/i386/lib/realmode.c8
-rw-r--r--arch/microblaze/cpu/irq.S19
-rw-r--r--arch/microblaze/include/asm/asm.h2
-rw-r--r--arch/nios2/include/asm/gpio.h12
-rw-r--r--arch/nios2/include/asm/posix_types.h2
-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c19
-rw-r--r--arch/powerpc/cpu/mpc83xx/speed.c15
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c11
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c111
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c3
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr.h2
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h6
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h5
-rw-r--r--arch/powerpc/include/asm/global_data.h3
-rw-r--r--arch/sh/config.mk6
-rw-r--r--arch/sh/include/asm/cpu_sh4.h2
-rw-r--r--arch/sh/include/asm/cpu_sh7757.h218
-rw-r--r--board/Marvell/dkb/Makefile51
-rw-r--r--board/Marvell/dkb/dkb.c54
-rw-r--r--board/altera/nios2-generic/custom_fpga.h1
-rw-r--r--board/altera/nios2-generic/gpio.c11
-rw-r--r--board/dbau1x00/Makefile2
-rw-r--r--board/eNET/config.mk6
-rw-r--r--board/eNET/eNET.c192
-rw-r--r--board/eNET/eNET_start.S7
-rw-r--r--board/eNET/eNET_start16.S15
-rw-r--r--board/espt/config.mk9
-rw-r--r--board/freescale/common/sys_eeprom.c1
-rw-r--r--board/freescale/mx31pdk/mx31pdk.c17
-rw-r--r--board/gdsys/405ep/405ep.c66
-rw-r--r--board/gdsys/405ep/Makefile1
-rw-r--r--board/gdsys/405ep/dlvision-10g.c239
-rw-r--r--board/gdsys/405ep/io.c19
-rw-r--r--board/gdsys/405ep/iocon.c24
-rw-r--r--board/gdsys/common/Makefile1
-rw-r--r--board/gdsys/common/osd.c309
-rw-r--r--board/gdsys/common/osd.h2
-rw-r--r--board/incaip/lowlevel_init.S2
-rw-r--r--board/mpr2/config.mk37
-rw-r--r--board/ms7722se/config.mk31
-rw-r--r--board/nvidia/common/board.c193
-rw-r--r--board/nvidia/harmony/Makefile50
-rw-r--r--board/nvidia/seaboard/Makefile50
-rw-r--r--board/purple/u-boot.lds5
-rw-r--r--board/renesas/ap325rxa/config.mk26
-rw-r--r--board/renesas/r2dplus/config.mk23
-rw-r--r--board/renesas/r7780mp/config.mk27
-rw-r--r--board/renesas/rsk7203/config.mk28
-rw-r--r--board/renesas/sh7757lcr/Makefile (renamed from board/renesas/MigoR/config.mk)38
-rw-r--r--board/renesas/sh7757lcr/lowlevel_init.S558
-rw-r--r--board/renesas/sh7757lcr/sh7757lcr.c454
-rw-r--r--board/renesas/sh7757lcr/spi-boot.c109
-rw-r--r--board/renesas/sh7757lcr/u-boot.lds101
-rw-r--r--board/renesas/sh7763rdp/config.mk11
-rw-r--r--board/renesas/sh7785lcr/Makefile8
-rw-r--r--board/renesas/sh7785lcr/config.mk31
-rw-r--r--board/shmin/config.mk27
-rw-r--r--boards.cfg58
-rw-r--r--common/cmd_bmp.c2
-rw-r--r--common/cmd_flash.c8
-rw-r--r--common/cmd_ide.c3
-rw-r--r--common/cmd_itest.c7
-rw-r--r--common/cmd_mem.c10
-rw-r--r--common/cmd_usb.c12
-rw-r--r--common/env_nand.c6
-rw-r--r--common/serial.c3
-rw-r--r--common/usb.c15
-rw-r--r--doc/README.sh7757lcr64
-rw-r--r--doc/README.usb4
-rw-r--r--drivers/gpio/mvmfp.c2
-rw-r--r--drivers/mmc/fsl_esdhc.c5
-rw-r--r--drivers/net/ne2000.c3
-rw-r--r--drivers/net/sh_eth.c9
-rw-r--r--drivers/rtc/mc146818.c6
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial.c2
-rw-r--r--drivers/serial/serial_tegra2.c77
-rw-r--r--drivers/serial/serial_tegra2.h29
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/altera_spi.c5
-rw-r--r--drivers/spi/sh_spi.c261
-rw-r--r--drivers/spi/sh_spi.h79
-rw-r--r--drivers/usb/eth/Makefile48
-rw-r--r--drivers/usb/eth/asix.c635
-rw-r--r--drivers/usb/eth/usb_ether.c150
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/ether.c775
-rw-r--r--drivers/usb/gadget/ndis.h217
-rw-r--r--drivers/usb/gadget/rndis.c1317
-rw-r--r--drivers/usb/gadget/rndis.h260
-rw-r--r--drivers/usb/host/ehci-hcd.c10
-rw-r--r--drivers/usb/host/ohci-hcd.c7
-rw-r--r--include/configs/MPC8572DS.h3
-rw-r--r--include/configs/MigoR.h1
-rw-r--r--include/configs/P1_P2_RDB.h3
-rw-r--r--include/configs/ap325rxa.h2
-rw-r--r--include/configs/aspenite.h8
-rw-r--r--include/configs/dkb.h65
-rw-r--r--include/configs/dlvision-10g.h316
-rw-r--r--include/configs/eNET.h679
-rw-r--r--include/configs/espt.h1
-rw-r--r--include/configs/harmony.h49
-rw-r--r--include/configs/incaip.h9
-rw-r--r--include/configs/io.h8
-rw-r--r--include/configs/iocon.h25
-rw-r--r--include/configs/mpr2.h2
-rw-r--r--include/configs/ms7720se.h1
-rw-r--r--include/configs/ms7722se.h1
-rw-r--r--include/configs/ms7750se.h1
-rw-r--r--include/configs/mv-common.h147
-rw-r--r--include/configs/mx31pdk.h7
-rw-r--r--include/configs/r2dplus.h1
-rw-r--r--include/configs/r7780mp.h1
-rw-r--r--include/configs/rsk7203.h1
-rw-r--r--include/configs/seaboard.h43
-rw-r--r--include/configs/sh7757lcr.h146
-rw-r--r--include/configs/sh7763rdp.h1
-rw-r--r--include/configs/sh7785lcr.h2
-rw-r--r--include/configs/shmin.h1
-rw-r--r--include/configs/tegra2-common.h160
-rw-r--r--include/configs/vct.h7
-rw-r--r--include/environment.h3
-rw-r--r--include/gdsys_fpga.h108
-rw-r--r--include/linux/netdevice.h65
-rw-r--r--include/linux/usb/cdc.h6
-rw-r--r--include/mpc83xx.h7
-rw-r--r--include/pci.h2
-rw-r--r--include/serial.h3
-rw-r--r--include/usb.h15
-rw-r--r--include/usb_ether.h68
-rw-r--r--nand_spl/board/freescale/mx31pdk/u-boot.lds59
-rw-r--r--net/eth.c43
181 files changed, 12452 insertions, 2110 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index b37ed0ce9..4756f14d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -146,6 +146,7 @@ Dirk Eibach <eibach@gdsys.de>
devconcenter PPC460EX
dlvision PPC405EP
+ dlvision-10g PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
@@ -857,6 +858,15 @@ Prafulla Wadaskar <prafulla@marvell.com>
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
+Tom Warren <twarren@nvidia.com>
+
+ harmony Tegra2 (ARM7 & A9 Dual Core)
+ seaboard Tegra2 (ARM7 & A9 Dual Core)
+
+Lei Wen <leiwen@marvell.com>
+
+ dkb ARM926EJS (PANTHEON 88AP920 SOC)
+
Matthias Weisser <weisserm@arcor.de>
jadecpu ARM926EJS (MB86R01 SoC)
@@ -1036,6 +1046,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
MS7720SE SH7720
+ R0P77570030RL SH7757
R0P77850011RL SH7785
#########################################################################
diff --git a/Makefile b/Makefile
index 05b404df0..dc2e3d8b3 100644
--- a/Makefile
+++ b/Makefile
@@ -235,6 +235,7 @@ endif
LIBS += drivers/rtc/librtc.o
LIBS += drivers/serial/libserial.o
LIBS += drivers/twserial/libtws.o
+LIBS += drivers/usb/eth/libusb_eth.a
LIBS += drivers/usb/gadget/libusb_gadget.o
LIBS += drivers/usb/host/libusb_host.o
LIBS += drivers/usb/musb/libusb_musb.o
@@ -1092,95 +1093,6 @@ smdk6400_config : unconfig
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
#========================================================================
-# MIPS
-#========================================================================
-#########################################################################
-## MIPS32 4Kc
-#########################################################################
-
-incaip_100MHz_config \
-incaip_133MHz_config \
-incaip_150MHz_config \
-incaip_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _100MHz,$@)" ] || \
- echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h
- @[ -z "$(findstring _133MHz,$@)" ] || \
- echo "#define CPU_CLOCK_RATE 133000000" >>$(obj)include/config.h
- @[ -z "$(findstring _150MHz,$@)" ] || \
- echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a incaip mips mips incaip
-
-vct_premium_config \
-vct_premium_small_config \
-vct_premium_onenand_config \
-vct_premium_onenand_small_config \
-vct_platinum_config \
-vct_platinum_small_config \
-vct_platinum_onenand_config \
-vct_platinum_onenand_small_config \
-vct_platinumavc_config \
-vct_platinumavc_small_config \
-vct_platinumavc_onenand_config \
-vct_platinumavc_onenand_small_config: unconfig
- @mkdir -p $(obj)include
- @[ -z "$(findstring _premium,$@)" ] || \
- echo "#define CONFIG_VCT_PREMIUM" > $(obj)include/config.h
- @[ -z "$(findstring _platinum_,$@)" ] || \
- echo "#define CONFIG_VCT_PLATINUM" > $(obj)include/config.h
- @[ -z "$(findstring _platinumavc,$@)" ] || \
- echo "#define CONFIG_VCT_PLATINUMAVC" > $(obj)include/config.h
- @[ -z "$(findstring _onenand,$@)" ] || \
- echo "#define CONFIG_VCT_ONENAND" >> $(obj)include/config.h
- @[ -z "$(findstring _small,$@)" ] || \
- echo "#define CONFIG_VCT_SMALL_IMAGE" >> $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a vct mips mips vct micronas
-
-#########################################################################
-## MIPS32 AU1X00
-#########################################################################
-
-dbau1000_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_DBAU1000 1" >$(obj)include/config.h
- @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1100_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_DBAU1100 1" >$(obj)include/config.h
- @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1500_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_DBAU1500 1" >$(obj)include/config.h
- @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1550_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
- @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-dbau1550_el_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h
- @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
-
-gth2_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_GTH2 1" >$(obj)include/config.h
- @$(MKCONFIG) -a $@ mips mips gth2
-
-pb1000_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_PB1000 1" >$(obj)include/config.h
- @$(MKCONFIG) -a pb1x00 mips mips pb1x00
-
-qemu_mips_config : unconfig
- @mkdir -p $(obj)include
- @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h
- @$(MKCONFIG) -a qemu-mips mips mips qemu-mips
-
-#========================================================================
# Nios
#========================================================================
diff --git a/README b/README
index 755d17cc3..21cd71b29 100644
--- a/README
+++ b/README
@@ -319,6 +319,11 @@ The following options need to be configured:
CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
CONFIG_SYS_8272ADS - MPC8272ADS
+- Marvell Family Member
+ CONFIG_SYS_MVFS - define it if you want to enable
+ multiple fs option at one time
+ for marvell soc family
+
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
@@ -892,6 +897,18 @@ The following options need to be configured:
automatically converts one 32 bit word to two 16 bit
words you may also try CONFIG_SMC911X_32_BIT.
+ CONFIG_SH_ETHER
+ Support for Renesas on-chip Ethernet controller
+
+ CONFIG_SH_ETHER_USE_PORT
+ Define the number of ports to be used
+
+ CONFIG_SH_ETHER_PHY_ADDR
+ Define the ETH PHY's address
+
+ CONFIG_SH_ETHER_CACHE_WRITEBACK
+ If this option is set, the driver enables cache flush.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
@@ -1648,6 +1665,11 @@ The following options need to be configured:
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
+ CONFIG_SH_SPI
+
+ Enables the driver for SPI controller on SuperH. Currently
+ only SH7757 is supported.
+
CONFIG_SPI_X
Enables extended (16-bit) SPI EEPROM addressing.
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index b771d316e..a05d36d72 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -163,15 +163,7 @@ call_board_init_f:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
-#ifdef CONFIG_NAND_SPL
- bl nand_boot
-#else
-#ifdef CONFIG_ONENAND_IPL
- bl start_oneboot
-#else
bl board_init_f
-#endif /* CONFIG_ONENAND_IPL */
-#endif /* CONFIG_NAND_SPL */
/*------------------------------------------------------------------------------*/
@@ -267,14 +259,14 @@ clbss_l:str r2, [r0] /* clear loop... */
*/
#ifdef CONFIG_NAND_SPL
ldr r0, _nand_boot_ofs
- adr r1, _start
- add pc, r0, r1
-_nand_boot_ofs
- : .word nand_boot - _start
+ mov pc, r0
+
+_nand_boot_ofs:
+ .word nand_boot
#else
jump_2_ram:
ldr r0, _board_init_r_ofs
- adr r1, _start
+ ldr r1, _TEXT_BASE
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
new file mode 100644
index 000000000..ab94985ba
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y = cpu.o timer.o dram.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
new file mode 100644
index 000000000..9ddc77c07
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID (1<<8)
+#define L2C_RAM_SEL (1<<4)
+
+int arch_cpu_init(void)
+{
+ u32 val;
+ struct panthcpu_registers *cpuregs =
+ (struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+ struct panthapb_registers *apbclkres =
+ (struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+ struct panthmpmu_registers *mpmu =
+ (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+ /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+ val = readl(&cpuregs->cpu_conf);
+ val = val | SET_MRVL_ID;
+ writel(val, &cpuregs->cpu_conf);
+
+ /* Turn on clock gating (PMUM_CCGR) */
+ writel(0xFFFFFFFF, &mpmu->ccgr);
+
+ /* Turn on clock gating (PMUM_ACGR) */
+ writel(0xFFFFFFFF, &mpmu->acgr);
+
+ /* Turn on uart2 clock */
+ writel(UARTCLK14745KHZ, &apbclkres->uart0);
+
+ /* Enable GPIO clock */
+ writel(APBC_APBCLK, &apbclkres->gpio);
+
+ icache_enable();
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 id;
+ struct panthcpu_registers *cpuregs =
+ (struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+ id = readl(&cpuregs->chip_id);
+ printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
new file mode 100644
index 000000000..bbca7eef1
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/dram.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Pantheon DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct panthddr_map_registers {
+ u32 cs; /* Memory Address Map Register -CS */
+ u32 pad[3];
+};
+
+struct panthddr_registers {
+ u8 pad[0x100 - 0x000];
+ struct panthddr_map_registers mmap[2];
+};
+
+/*
+ * panth_sdram_base - reads SDRAM Base Address Register
+ */
+u32 panth_sdram_base(int chip_sel)
+{
+ struct panthddr_registers *ddr_regs =
+ (struct panthddr_registers *)PANTHEON_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+ return result;
+}
+
+/*
+ * panth_sdram_size - reads SDRAM size
+ */
+u32 panth_sdram_size(int chip_sel)
+{
+ struct panthddr_registers *ddr_regs =
+ (struct panthddr_registers *)PANTHEON_DRAM_BASE;
+ u32 result = 0;
+ u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+ if (!CS_valid)
+ return 0;
+
+ result = readl(&ddr_regs->mmap[chip_sel].cs);
+ result = (result >> 16) & 0xF;
+ if (result < 0x7) {
+ printf("Unknown DRAM Size\n");
+ return -1;
+ } else {
+ return ((0x8 << (result - 0x7)) * 1024 * 1024);
+ }
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = panth_sdram_base(i);
+ gd->bd->bi_dram[i].size = panth_sdram_size(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /*
+ * If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash
+ */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
new file mode 100644
index 000000000..ca7f7f071
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct panthtmr_registers {
+ u32 clk_ctrl; /* Timer clk control reg */
+ u32 match[9]; /* Timer match registers */
+ u32 count[3]; /* Timer count registers */
+ u32 status[3];
+ u32 ie[3];
+ u32 preload[3]; /* Timer preload value */
+ u32 preload_ctrl[3];
+ u32 wdt_match_en;
+ u32 wdt_match_r;
+ u32 wdt_val;
+ u32 wdt_sts;
+ u32 icr[3];
+ u32 wdt_icr;
+ u32 cer; /* Timer count enable reg */
+ u32 cmr;
+ u32 ilr[3];
+ u32 wcr;
+ u32 wfar;
+ u32 wsar;
+ u32 cvwr[3];
+};
+
+#define TIMER 0 /* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x) ((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 0xffffffff
+#define COUNT_RD_REQ 0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/*
+ * For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+ struct panthtmr_registers *panthtimers =
+ (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+ volatile int loop=100;
+ ulong val;
+
+ writel(COUNT_RD_REQ, &panthtimers->cvwr);
+ while (loop--)
+ val = readl(&panthtimers->cvwr);
+
+ /*
+ * This stop gcc complain and prevent loop mistake init to 0
+ */
+ val = readl(&panthtimers->cvwr);
+
+ return val;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ gd->tbl = read_timer();
+ gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (now >= gd->tbl) {
+ /* normal mode */
+ gd->tbu += now - gd->tbl;
+ } else {
+ /* we have an overflow ... */
+ gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ }
+ gd->tbl = now;
+
+ return gd->tbu;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+ base);
+}
+
+void set_timer(ulong t)
+{
+ gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong delayticks;
+ ulong endtime;
+
+ delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+ endtime = get_timer_masked() + delayticks;
+
+ while (get_timer_masked() < endtime)
+ ;
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+ struct panthapb_registers *apb1clkres =
+ (struct panthapb_registers *) PANTHEON_APBC_BASE;
+ struct panthtmr_registers *panthtimers =
+ (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+
+ /* Enable Timer clock at 3.25 MHZ */
+ writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+ /* load value into timer */
+ writel(0x0, &panthtimers->clk_ctrl);
+ /* Use Timer 0 Match Resiger 0 */
+ writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
+ /* Preload value is 0 */
+ writel(0x0, &panthtimers->preload[TIMER]);
+ /* Enable match comparator 0 for Timer 0 */
+ writel(0x1, &panthtimers->preload_ctrl[TIMER]);
+
+ /* Enable timer 0 */
+ writel(0x1, &panthtimers->cer);
+ /* init the gd->tbu and gd->tbl value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+#define MPMU_APRR_WDTR (1<<4)
+#define TMR_WFAR 0xbaba /* WDT Register First key */
+#define TMP_WSAR 0xeb10 /* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+ struct panthmpmu_registers *mpmu =
+ (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
+ struct panthtmr_registers *panthtimers =
+ (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
+ u32 val;
+
+ /* negate hardware reset to the WDT after system reset */
+ val = readl(&mpmu->aprr);
+ val = val | MPMU_APRR_WDTR;
+ writel(val, &mpmu->aprr);
+
+ /* reset/enable WDT clock */
+ writel(APBC_APBCLK, &mpmu->wdtpcr);
+
+ /* clear previous WDT status */
+ writel(TMR_WFAR, &panthtimers->wfar);
+ writel(TMP_WSAR, &panthtimers->wsar);
+ writel(0, &panthtimers->wdt_sts);
+
+ /* set match counter */
+ writel(TMR_WFAR, &panthtimers->wfar);
+ writel(TMP_WSAR, &panthtimers->wsar);
+ writel(0xf, &panthtimers->wdt_match_r);
+
+ /* enable WDT reset */
+ writel(TMR_WFAR, &panthtimers->wfar);
+ writel(TMP_WSAR, &panthtimers->wsar);
+ writel(0x3, &panthtimers->wdt_match_en);
+
+ /*enable functional WDT clock */
+ writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index eb93ac9db..f4c177e52 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -281,7 +281,7 @@ _nand_boot_ofs:
.word nand_boot
#else
ldr r0, _board_init_r_ofs
- adr r1, _start
+ ldr r1, _TEXT_BASE
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
diff --git a/board/ms7720se/config.mk b/arch/arm/cpu/armv7/tegra2/Makefile
index d2944a6b2..687c8871c 100644
--- a/board/ms7720se/config.mk
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -1,14 +1,11 @@
#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+# (C) Copyright 2010,2011 Nvidia Corporation.
#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7720se/config.mk
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -24,11 +21,28 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
#
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+COBJS := board.o sys_info.o timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
new file mode 100644
index 000000000..9061d181d
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
+ * so we are using this value to identify memory size.
+ */
+
+unsigned int query_sdram_size(void)
+{
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ reg = readl(&pmc->pmc_scratch20);
+ debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
+
+ /* bits 31:28 in OdmData are used for RAM size */
+ switch ((reg) >> 28) {
+ case 1:
+ return 0x10000000; /* 256 MB */
+ case 2:
+ return 0x20000000; /* 512 MB */
+ case 3:
+ default:
+ return 0x40000000; /* 1GB */
+ }
+}
+
+void s_init(void)
+{
+#ifndef CONFIG_ICACHE_OFF
+ icache_enable();
+#endif
+ invalidate_dcache();
+}
+
+int dram_init(void)
+{
+ unsigned long rs;
+
+ /* We do not initialise DRAM here. We just query the size */
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
+
+ /* Now check it dynamically */
+ rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
+ if (rs) {
+ printf("dynamic ram_size = %lu\n", rs);
+ gd->bd->bi_dram[0].size = gd->ram_size = rs;
+ }
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board: %s\n", sysinfo.board_string);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff --git a/board/ms7750se/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
index ba4d15591..96c07955a 100644
--- a/board/ms7750se/config.mk
+++ b/arch/arm/cpu/armv7/tegra2/config.mk
@@ -1,6 +1,12 @@
#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -17,7 +23,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
+
+# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
+PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
new file mode 100644
index 000000000..7f1574686
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
@@ -0,0 +1,65 @@
+/*
+ * SoC-specific setup info
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+ mov pc, lr
+
+ .align 5
+.global reset_cpu
+reset_cpu:
+ ldr r1, rstctl @ get addr for global reset
+ @ reg
+ ldr r3, [r1]
+ orr r3, r3, #0x10
+ str r3, [r1] @ force reset
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PRM_RSTCTRL
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp]
+ mov ip, lr
+ bl s_init @ go setup pll, mux & memory
+ ldr ip, [sp]
+ mov lr, ip
+
+ mov pc, lr @ back to arch calling code
+
+ @ the literal pools origin
+ .ltorg
+
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
diff --git a/board/dbau1x00/flash.c b/arch/arm/cpu/armv7/tegra2/sys_info.c
index a2fed1d71..6d11dc16b 100644
--- a/board/dbau1x00/flash.c
+++ b/arch/arm/cpu/armv7/tegra2/sys_info.c
@@ -1,6 +1,6 @@
/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,21 +23,13 @@
#include <common.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
{
- printf ("Skipping flash_init\n");
- return (0);
-}
+ puts("TEGRA2\n");
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- printf ("write_buff not implemented\n");
- return (-1);
+ /* TBD: Add printf of major/minor rev info, stepping, etc. */
+ return 0;
}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c
new file mode 100644
index 000000000..fb061d091
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/timer.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
+
+/* counter runs at 1MHz */
+#define TIMER_CLK (1000000)
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* timer without interrupts */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ gd->tbl = t;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ long tmo = usec * (TIMER_CLK / 1000) / 1000;
+ unsigned long now, last = readl(&timer_base->cntr_1us);
+
+ while (tmo > 0) {
+ now = readl(&timer_base->cntr_1us);
+ if (last > now) /* count up timer overflow */
+ tmo -= TIMER_LOAD_VAL - last + now;
+ else
+ tmo -= now - last;
+ last = now;
+ }
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time, capture current incrementer value time */
+ gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
+ gd->tbl = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now;
+
+ /* current tick value */
+ now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
+
+ if (now >= gd->lastinc) /* normal mode (non roll) */
+ /* move stamp forward with absolute diff ticks */
+ gd->tbl += (now - gd->lastinc);
+ else /* we have rollover of incrementer */
+ gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+ - gd->lastinc) + now;
+ gd->lastinc = now;
+ return gd->tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
new file mode 100644
index 000000000..d8040025e
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Armada100 platform
+ */
+
+#ifndef _ARMD1_CONFIG_H
+#define _ARMD1_CONFIG_H
+
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+
+#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
+#define MV_MFPR_BASE ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
+ represents UART Unit Enable */
+
+#endif /* _ARMD1_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
new file mode 100644
index 000000000..71ba46412
--- /dev/null
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Kirkwood platform
+ */
+
+#ifndef _KW_CONFIG_H
+#define _KW_CONFIG_H
+
+#if defined (CONFIG_KW88F6281)
+#include <asm/arch/kw88f6281.h>
+#elif defined (CONFIG_KW88F6192)
+#include <asm/arch/kw88f6192.h>
+#else
+#error "SOC Name not defined"
+#endif /* CONFIG_KW88F6281 */
+
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
+#define MV_UART_CONSOLE_BASE KW_UART0_BASE
+#define MV_SATA_BASE KW_SATA_BASE
+#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
+#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL 1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#endif /* _KW_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
new file mode 100644
index 000000000..710b3862c
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CONFIG_H
+#define _PANTHEON_CONFIG_H
+
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+
+#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
+#define MV_MFPR_BASE PANTHEON_MFPR_BASE
+#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
+#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
+ represents UART Unit Enable */
+
+#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
new file mode 100644
index 000000000..30f439305
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CPU_H
+#define _PANTHEON_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct panthmpmu_registers {
+ u8 pad0[0x0024];
+ u32 ccgr; /*0x0024*/
+ u8 pad1[0x0200 - 0x024 - 4];
+ u32 wdtpcr; /*0x0200*/
+ u8 pad2[0x1020 - 0x200 - 4];
+ u32 aprr; /*0x1020*/
+ u32 acgr; /*0x1024*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct panthapb_registers {
+ u32 uart0; /*0x000*/
+ u32 uart1; /*0x004*/
+ u32 gpio; /*0x008*/
+ u8 pad0[0x034 - 0x08 - 4];
+ u32 timers; /*0x034*/
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Register Datasheet 4.3
+ */
+struct panthcpu_registers {
+ u32 chip_id; /* Chip Id Reg */
+ u32 pad;
+ u32 cpu_conf; /* CPU Conf Reg */
+ u32 pad1;
+ u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
+ u32 pad2;
+ u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
+ u32 mcb_conf; /* MCB Conf Reg */
+ u32 sys_boot_ctl; /* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 panth_sdram_base(int);
+u32 panth_sdram_size(int);
+
+#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
new file mode 100644
index 000000000..fb291cf55
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -0,0 +1,41 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PANTHEON_MFP_H
+#define __PANTHEON_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART2 */
+#define MFP47_UART2_RXD MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX 117
+#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
new file mode 100644
index 000000000..e4ed087b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/pantheon.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_H
+#define _PANTHEON_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
+#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
+#define APBC_RST (1<<2) /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define PANTHEON_DRAM_BASE 0xB0000000
+#define PANTHEON_TIMER_BASE 0xD4014000
+#define PANTHEON_WD_TIMER_BASE 0xD4080000
+#define PANTHEON_APBC_BASE 0xD4015000
+#define PANTHEON_UART1_BASE 0xD4017000
+#define PANTHEON_UART2_BASE 0xD4018000
+#define PANTHEON_GPIO_BASE 0xD4019000
+#define PANTHEON_MFPR_BASE 0xD401E000
+#define PANTHEON_MPMU_BASE 0xD4050000
+#define PANTHEON_CPU_BASE 0xD4282C00
+
+#endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
new file mode 100644
index 000000000..6d573bf46
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CLK_RST_H_
+#define _CLK_RST_H_
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+struct clk_rst_ctlr {
+ uint crc_rst_src; /* _RST_SOURCE_0, 0x00 */
+ uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04 */
+ uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08 */
+ uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C */
+ uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10 */
+ uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14 */
+ uint crc_clk_out_enb_u; /* _CLK_OUT_ENB_U_0, 0x18 */
+ uint crc_reserved0; /* reserved_0, 0x1C */
+ uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
+ uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
+ uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
+ uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
+ uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
+ uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
+ uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
+ uint crc_reserved1; /* reserved_1, 0x3C */
+ uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
+ uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
+ uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
+ uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
+ uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
+ uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
+ uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
+ uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
+ uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
+
+ uint crc_pllc_base; /* _PLLC_BASE_0, 0x80 */
+ uint crc_pllc_out; /* _PLLC_OUT_0, 0x84 */
+ uint crc_reserved3; /* reserved_3, 0x88 */
+ uint crc_pllc_misc; /* _PLLC_MISC_0, 0x8C */
+
+ uint crc_pllm_base; /* _PLLM_BASE_0, 0x90 */
+ uint crc_pllm_out; /* _PLLM_OUT_0, 0x94 */
+ uint crc_reserved4; /* reserved_4, 0x98 */
+ uint crc_pllm_misc; /* _PLLM_MISC_0, 0x9C */
+
+ uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0 */
+ uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4 */
+ uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8 */
+ uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC */
+
+ uint crc_plla_base; /* _PLLA_BASE_0, 0xB0 */
+ uint crc_plla_out; /* _PLLA_OUT_0, 0xB4 */
+ uint crc_reserved5; /* reserved_5, 0xB8 */
+ uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC */
+
+ uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0 */
+ uint crc_reserved6; /* _reserved_6, 0xC4 */
+ uint crc_reserved7; /* _reserved_7, 0xC8 */
+ uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC */
+
+ uint crc_plld_base; /* _PLLD_BASE_0, 0xD0 */
+ uint crc_reserved8; /* _reserved_8, 0xD4 */
+ uint crc_reserved9; /* _reserved_9, 0xD8 */
+ uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC */
+
+ uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0 */
+ uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4 */
+
+ uint crc_plle_base; /* _PLLE_BASE_0, 0xE8 */
+ uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC */
+
+ uint crc_plls_base; /* _PLLS_BASE_0, 0xF0 */
+ uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4 */
+ uint crc_reserved10; /* _reserved_10, 0xF8 */
+ uint crc_reserved11; /* _reserved_11, 0xFC */
+
+ uint crc_clk_src_i2s1; /*_I2S1_0, 0x100 */
+ uint crc_clk_src_i2s2; /*_I2S2_0, 0x104 */
+ uint crc_clk_src_spdif_out; /*_SPDIF_OUT_0, 0x108 */
+ uint crc_clk_src_spdif_in; /*_SPDIF_IN_0, 0x10C */
+ uint crc_clk_src_pwm; /*_PWM_0, 0x110 */
+ uint crc_clk_src_spi1; /*_SPI1_0, 0x114 */
+ uint crc_clk_src_sbc2; /*_SBC2_0, 0x118 */
+ uint crc_clk_src_sbc3; /*_SBC3_0, 0x11C */
+ uint crc_clk_src_xio; /*_XIO_0, 0x120 */
+ uint crc_clk_src_i2c1; /*_I2C1_0, 0x124 */
+ uint crc_clk_src_dvc_i2c; /*_DVC_I2C_0, 0x128 */
+ uint crc_clk_src_twc; /*_TWC_0, 0x12C */
+ uint crc_reserved12; /* 0x130 */
+ uint crc_clk_src_sbc1; /*_SBC1_0, 0x134 */
+ uint crc_clk_src_disp1; /*_DISP1_0, 0x138 */
+ uint crc_clk_src_disp2; /*_DISP2_0, 0x13C */
+ uint crc_clk_src_cve; /*_CVE_0, 0x140 */
+ uint crc_clk_src_ide; /*_IDE_0, 0x144 */
+ uint crc_clk_src_vi; /*_VI_0, 0x148 */
+ uint crc_reserved13; /* 0x14C */
+ uint crc_clk_src_sdmmc1; /*_SDMMC1_0, 0x150 */
+ uint crc_clk_src_sdmmc2; /*_SDMMC2_0, 0x154 */
+ uint crc_clk_src_g3d; /*_G3D_0, 0x158 */
+ uint crc_clk_src_g2d; /*_G2D_0, 0x15C */
+ uint crc_clk_src_ndflash; /*_NDFLASH_0, 0x160 */
+ uint crc_clk_src_sdmmc4; /*_SDMMC4_0, 0x164 */
+ uint crc_clk_src_vfir; /*_VFIR_0, 0x168 */
+ uint crc_clk_src_epp; /*_EPP_0, 0x16C */
+ uint crc_clk_src_mp3; /*_MPE_0, 0x170 */
+ uint crc_clk_src_mipi; /*_MIPI_0, 0x174 */
+ uint crc_clk_src_uarta; /*_UARTA_0, 0x178 */
+ uint crc_clk_src_uartb; /*_UARTB_0, 0x17C */
+ uint crc_clk_src_host1x; /*_HOST1X_0, 0x180 */
+ uint crc_reserved14; /* 0x184 */
+ uint crc_clk_src_tvo; /*_TVO_0, 0x188 */
+ uint crc_clk_src_hdmi; /*_HDMI_0, 0x18C */
+ uint crc_reserved15; /* 0x190 */
+ uint crc_clk_src_tvdac; /*_TVDAC_0, 0x194 */
+ uint crc_clk_src_i2c2; /*_I2C2_0, 0x198 */
+ uint crc_clk_src_emc; /*_EMC_0, 0x19C */
+ uint crc_clk_src_uartc; /*_UARTC_0, 0x1A0 */
+ uint crc_reserved16; /* 0x1A4 */
+ uint crc_clk_src_vi_sensor; /*_VI_SENSOR_0, 0x1A8 */
+ uint crc_reserved17; /* 0x1AC */
+ uint crc_reserved18; /* 0x1B0 */
+ uint crc_clk_src_sbc4; /*_SBC4_0, 0x1B4 */
+ uint crc_clk_src_i2c3; /*_I2C3_0, 0x1B8 */
+ uint crc_clk_src_sdmmc3; /*_SDMMC3_0, 0x1BC */
+ uint crc_clk_src_uartd; /*_UARTD_0, 0x1C0 */
+ uint crc_clk_src_uarte; /*_UARTE_0, 0x1C4 */
+ uint crc_clk_src_vde; /*_VDE_0, 0x1C8 */
+ uint crc_clk_src_owr; /*_OWR_0, 0x1CC */
+ uint crc_clk_src_nor; /*_NOR_0, 0x1D0 */
+ uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */
+ uint crc_reserved19[9]; /* 0x1D8-1F8 */
+ uint crc_clk_src_osc; /*_OSC_0, 0x1FC */
+};
+
+#define PLL_BYPASS (1 << 31)
+#define PLL_ENABLE (1 << 30)
+#define PLL_BASE_OVRRIDE (1 << 28)
+#define PLL_DIVP (1 << 20) /* post divider, b22:20 */
+#define PLL_DIVM 0x0C /* input divider, b4:0 */
+
+#define SWR_UARTD_RST (1 << 2)
+#define CLK_ENB_UARTD (1 << 2)
+#define SWR_UARTA_RST (1 << 6)
+#define CLK_ENB_UARTA (1 << 6)
+
+#endif /* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h
new file mode 100644
index 000000000..8b4bd8d88
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pinmux.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
+struct pmux_tri_ctlr {
+ uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
+ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
+ uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+ uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
+ uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
+ uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */
+ uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */
+ uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */
+ uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
+
+ uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */
+ uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */
+ uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */
+ uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */
+ uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */
+ uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */
+ uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
+};
+
+#define Z_GMC (1 << 29)
+#define Z_IRRX (1 << 20)
+#define Z_IRTX (1 << 19)
+
+#endif /* PINMUX_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h
new file mode 100644
index 000000000..7ec9eeba1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pmc.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+struct pmc_ctlr {
+ uint pmc_cntrl; /* _CNTRL_0, offset 00 */
+ uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
+ uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
+ uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
+ uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
+ uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
+ uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
+ uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
+ uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
+ uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
+ uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
+ uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
+ uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
+ uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
+ uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
+ uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */
+ uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */
+ uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */
+ uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */
+ uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */
+
+ uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */
+ uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */
+ uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */
+ uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */
+ uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */
+ uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */
+ uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */
+ uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */
+ uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */
+ uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */
+ uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */
+ uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */
+ uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */
+ uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */
+ uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */
+ uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */
+ uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */
+ uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */
+ uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */
+ uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */
+ uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */
+ uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */
+ uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */
+ uint pmc_scratch23; /* _SCRATCH23_0, offset AC */
+
+ uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */
+ uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */
+ uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */
+ uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */
+ uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */
+ uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */
+
+ uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */
+ uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */
+ uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */
+ uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */
+ uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */
+ uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */
+ uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */
+ uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */
+ uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */
+ uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */
+ uint pmc_usb_ao; /* _USB_AO_0, offset F0 */
+ uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */
+ uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */
+
+ uint pmc_scratch24; /* _SCRATCH24_0, offset FC */
+ uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */
+ uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */
+ uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */
+ uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */
+ uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */
+ uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */
+ uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */
+ uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */
+ uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */
+ uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */
+ uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */
+ uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */
+ uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */
+ uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */
+ uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */
+ uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */
+ uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */
+ uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */
+
+ uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */
+ uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */
+ uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */
+ uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
+ uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
+ uint pmc_gate; /* _GATE_0, offset 15C */
+};
+
+#endif /* PMC_H */
diff --git a/board/gdsys/common/fpga.h b/arch/arm/include/asm/arch-tegra2/sys_proto.h
index c1434e7ab..c11534e58 100644
--- a/board/gdsys/common/fpga.h
+++ b/arch/arm/include/asm/arch-tegra2/sys_proto.h
@@ -1,6 +1,6 @@
/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -21,17 +21,15 @@
* MA 02111-1307 USA
*/
-#ifndef _FPGA_H_
-#define _FPGA_H_
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
-static inline u16 fpga_get_reg(unsigned reg)
-{
- return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
-}
+struct tegra2_sysinfo {
+ char *board_string;
+};
-static inline void fpga_set_reg(unsigned reg, u16 val)
-{
- return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
-}
+void invalidate_dcache(void);
+
+extern const struct tegra2_sysinfo sysinfo;
#endif
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
new file mode 100644
index 000000000..9001b6899
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_H_
+#define _TEGRA2_H_
+
+#define NV_PA_SDRAM_BASE 0x00000000
+#define NV_PA_TMRUS_BASE 0x60005010
+#define NV_PA_CLK_RST_BASE 0x60006000
+#define NV_PA_APB_MISC_BASE 0x70000000
+#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
+#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
+#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
+#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
+#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
+#define NV_PA_PMC_BASE 0x7000E400
+
+#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
+#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
+
+#ifndef __ASSEMBLY__
+struct timerus {
+ unsigned int cntr_1us;
+};
+#else /* __ASSEMBLY__ */
+#define PRM_RSTCTRL NV_PA_PMC_BASE
+#endif
+
+#endif /* TEGRA2_H */
diff --git a/arch/arm/include/asm/arch-tegra2/uart.h b/arch/arm/include/asm/arch-tegra2/uart.h
new file mode 100644
index 000000000..aea29a758
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/uart.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/* UART registers */
+struct uart_ctlr {
+ uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
+ uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
+ uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
+ uint uart_lcr; /* UART_LCR_0, offset 0C */
+ uint uart_mcr; /* UART_MCR_0, offset 10 */
+ uint uart_lsr; /* UART_LSR_0, offset 14 */
+ uint uart_msr; /* UART_MSR_0, offset 18 */
+ uint uart_spr; /* UART_SPR_0, offset 1C */
+ uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
+ uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
+ uint uart_asr; /* UART_ASR_0, offset 3C */
+};
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ 216000
+#define NV_DEFAULT_DEBUG_BAUD 115200
+
+#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */
+
+#endif /* UART_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 3886f1589..1fbc531a0 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -133,9 +133,9 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
#define __iormb() dmb()
#define __iowmb() dmb()
-#define writeb(v,c) ({ __iowmb(); __arch_putb(v,c); v; })
-#define writew(v,c) ({ __iowmb(); __arch_putw(v,c); v; })
-#define writel(v,c) ({ __iowmb(); __arch_putl(v,c); v; })
+#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
+#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
+#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index d95e6d67c..a1fd03a1c 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -2236,7 +2236,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_VS_V210 2252
#define MACH_TYPE_VS_V212 2253
#define MACH_TYPE_HMT 2254
-#define MACH_TYPE_SUEN3 2255
+#define MACH_TYPE_KM_KIRKWOOD 2255
#define MACH_TYPE_VESPER 2256
#define MACH_TYPE_STR9 2257
#define MACH_TYPE_OMAP3_WL_FF 2258
@@ -2983,7 +2983,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_EA20 3002
#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
-#define MACH_TYPE_TEGRA_SEABOARD 3005
+#define MACH_TYPE_SEABOARD 3005
#define MACH_TYPE_LINKSTATION_CHLV2 3006
#define MACH_TYPE_TERA_PRO2_RACK 3007
#define MACH_TYPE_RUBYS 3008
@@ -3186,7 +3186,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_ICS_IF_VOIP 3206
#define MACH_TYPE_WLF_CRAGG_6410 3207
#define MACH_TYPE_PUNICA 3208
-#define MACH_TYPE_SBC_NT250 3209
+#define MACH_TYPE_TRIMSLICE 3209
#define MACH_TYPE_MX27_WMULTRA 3210
#define MACH_TYPE_MACKEREL 3211
#define MACH_TYPE_FA9X27 3213
@@ -3215,6 +3215,103 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_PCM048 3236
#define MACH_TYPE_DDS 3237
#define MACH_TYPE_CHALTEN_XA1 3238
+#define MACH_TYPE_TS48XX 3239
+#define MACH_TYPE_TONGA2_TFTTIMER 3240
+#define MACH_TYPE_WHISTLER 3241
+#define MACH_TYPE_ASL_PHOENIX 3242
+#define MACH_TYPE_AT91SAM9263OTLITE 3243
+#define MACH_TYPE_DDPLUG 3244
+#define MACH_TYPE_D2PLUG 3245
+#define MACH_TYPE_KZM9D 3246
+#define MACH_TYPE_VERDI_LTE 3247
+#define MACH_TYPE_NANOZOOM 3248
+#define MACH_TYPE_DM3730_SOM_LV 3249
+#define MACH_TYPE_DM3730_TORPEDO 3250
+#define MACH_TYPE_ANCHOVY 3251
+#define MACH_TYPE_RE2REV20 3253
+#define MACH_TYPE_RE2REV21 3254
+#define MACH_TYPE_CNS21XX 3255
+#define MACH_TYPE_RIDER 3257
+#define MACH_TYPE_NSK330 3258
+#define MACH_TYPE_CNS2133EVB 3259
+#define MACH_TYPE_Z3_816X_MOD 3260
+#define MACH_TYPE_Z3_814X_MOD 3261
+#define MACH_TYPE_BEECT 3262
+#define MACH_TYPE_DMA_THUNDERBUG 3263
+#define MACH_TYPE_OMN_AT91SAM9G20 3264
+#define MACH_TYPE_MX25_E2S_UC 3265
+#define MACH_TYPE_MIONE 3266
+#define MACH_TYPE_TOP9000_TCU 3267
+#define MACH_TYPE_TOP9000_BSL 3268
+#define MACH_TYPE_KINGDOM 3269
+#define MACH_TYPE_ARMADILLO460 3270
+#define MACH_TYPE_LQ2 3271
+#define MACH_TYPE_SWEDA_TMS2 3272
+#define MACH_TYPE_MX53_LOCO 3273
+#define MACH_TYPE_ACER_A8 3275
+#define MACH_TYPE_ACER_GAUGUIN 3276
+#define MACH_TYPE_GUPPY 3277
+#define MACH_TYPE_MX61_ARD 3278
+#define MACH_TYPE_TX53 3279
+#define MACH_TYPE_OMAPL138_CASE_A3 3280
+#define MACH_TYPE_UEMD 3281
+#define MACH_TYPE_CCWMX51MUT 3282
+#define MACH_TYPE_ROCKHOPPER 3283
+#define MACH_TYPE_NOOKCOLOR 3284
+#define MACH_TYPE_HKDKC100 3285
+#define MACH_TYPE_TS42XX 3286
+#define MACH_TYPE_AEBL 3287
+#define MACH_TYPE_WARIO 3288
+#define MACH_TYPE_GFS_SPM 3289
+#define MACH_TYPE_CM_T3730 3290
+#define MACH_TYPE_ISC3 3291
+#define MACH_TYPE_RASCAL 3292
+#define MACH_TYPE_HREFV60 3293
+#define MACH_TYPE_TPT_2_0 3294
+#define MACH_TYPE_PYRAMID_TD 3295
+#define MACH_TYPE_SPLENDOR 3296
+#define MACH_TYPE_GUF_PLANET 3297
+#define MACH_TYPE_MSM8X60_QT 3298
+#define MACH_TYPE_HTC_HD_MINI 3299
+#define MACH_TYPE_ATHENE 3300
+#define MACH_TYPE_DEEP_R_EK_1 3301
+#define MACH_TYPE_VIVOW_CT 3302
+#define MACH_TYPE_NERY_1000 3303
+#define MACH_TYPE_RFL109145_SSRV 3304
+#define MACH_TYPE_NMH 3305
+#define MACH_TYPE_WN802T 3306
+#define MACH_TYPE_DRAGONET 3307
+#define MACH_TYPE_GENEVA_B 3308
+#define MACH_TYPE_AT91SAM9263DESK16L 3309
+#define MACH_TYPE_BCMHANA_SV 3310
+#define MACH_TYPE_BCMHANA_TABLET 3311
+#define MACH_TYPE_KOI 3312
+#define MACH_TYPE_TS4800 3313
+#define MACH_TYPE_TQMA9263 3314
+#define MACH_TYPE_HOLIDAY 3315
+#define MACH_TYPE_DMA6410 3316
+#define MACH_TYPE_PCATS_OVERLAY 3317
+#define MACH_TYPE_HWGW6410 3318
+#define MACH_TYPE_SHENZHOU 3319
+#define MACH_TYPE_CWME9210 3320
+#define MACH_TYPE_CWME9210JS 3321
+#define MACH_TYPE_PGS_SITARA 3322
+#define MACH_TYPE_COLIBRI_TEGRA2 3323
+#define MACH_TYPE_W21 3324
+#define MACH_TYPE_POLYSAT1 3325
+#define MACH_TYPE_DATAWAY 3326
+#define MACH_TYPE_COBRAL138 3327
+#define MACH_TYPE_ROVERPCS8 3328
+#define MACH_TYPE_MARVELC 3329
+#define MACH_TYPE_NAVEFIHID 3330
+#define MACH_TYPE_DM365_CV100 3331
+#define MACH_TYPE_ABLE 3332
+#define MACH_TYPE_LEGACY 3333
+#define MACH_TYPE_ICONG 3334
+#define MACH_TYPE_ROVER_G8 3335
+#define MACH_TYPE_T5388P 3336
+#define MACH_TYPE_DINGO 3337
+#define MACH_TYPE_GOFLEXHOME 3338
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -29904,16 +30001,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_hmt() (0)
#endif
-#ifdef CONFIG_MACH_SUEN3
+#ifdef CONFIG_MACH_KM_KIRKWOOD
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_SUEN3
+# define machine_arch_type MACH_TYPE_KM_KIRKWOOD
# endif
-# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3)
+# define machine_is_km_kirkwood() (machine_arch_type == MACH_TYPE_KM_KIRKWOOD)
#else
-# define machine_is_suen3() (0)
+# define machine_is_km_kirkwood() (0)
#endif
#ifdef CONFIG_MACH_VESPER
@@ -38868,16 +38965,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_ti8148evm() (0)
#endif
-#ifdef CONFIG_MACH_TEGRA_SEABOARD
+#ifdef CONFIG_MACH_SEABOARD
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_TEGRA_SEABOARD
+# define machine_arch_type MACH_TYPE_SEABOARD
# endif
-# define machine_is_tegra_seaboard() (machine_arch_type == MACH_TYPE_TEGRA_SEABOARD)
+# define machine_is_seaboard() (machine_arch_type == MACH_TYPE_SEABOARD)
#else
-# define machine_is_tegra_seaboard() (0)
+# define machine_is_seaboard() (0)
#endif
#ifdef CONFIG_MACH_LINKSTATION_CHLV2
@@ -41304,16 +41401,16 @@ extern unsigned int __machine_arch_type;
# define machine_is_punica() (0)
#endif
-#ifdef CONFIG_MACH_SBC_NT250
+#ifdef CONFIG_MACH_TRIMSLICE
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_SBC_NT250
+# define machine_arch_type MACH_TYPE_TRIMSLICE
# endif
-# define machine_is_sbc_nt250() (machine_arch_type == MACH_TYPE_SBC_NT250)
+# define machine_is_trimslice() (machine_arch_type == MACH_TYPE_TRIMSLICE)
#else
-# define machine_is_sbc_nt250() (0)
+# define machine_is_trimslice() (0)
#endif
#ifdef CONFIG_MACH_MX27_WMULTRA
@@ -41652,6 +41749,1170 @@ extern unsigned int __machine_arch_type;
# define machine_is_chalten_xa1() (0)
#endif
+#ifdef CONFIG_MACH_TS48XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS48XX
+# endif
+# define machine_is_ts48xx() (machine_arch_type == MACH_TYPE_TS48XX)
+#else
+# define machine_is_ts48xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_TONGA2_TFTTIMER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TONGA2_TFTTIMER
+# endif
+# define machine_is_tonga2_tfttimer() (machine_arch_type == MACH_TYPE_TONGA2_TFTTIMER)
+#else
+# define machine_is_tonga2_tfttimer() (0)
+#endif
+
+#ifdef CONFIG_MACH_WHISTLER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WHISTLER
+# endif
+# define machine_is_whistler() (machine_arch_type == MACH_TYPE_WHISTLER)
+#else
+# define machine_is_whistler() (0)
+#endif
+
+#ifdef CONFIG_MACH_ASL_PHOENIX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ASL_PHOENIX
+# endif
+# define machine_is_asl_phoenix() (machine_arch_type == MACH_TYPE_ASL_PHOENIX)
+#else
+# define machine_is_asl_phoenix() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263OTLITE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263OTLITE
+# endif
+# define machine_is_at91sam9263otlite() (machine_arch_type == MACH_TYPE_AT91SAM9263OTLITE)
+#else
+# define machine_is_at91sam9263otlite() (0)
+#endif
+
+#ifdef CONFIG_MACH_DDPLUG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DDPLUG
+# endif
+# define machine_is_ddplug() (machine_arch_type == MACH_TYPE_DDPLUG)
+#else
+# define machine_is_ddplug() (0)
+#endif
+
+#ifdef CONFIG_MACH_D2PLUG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_D2PLUG
+# endif
+# define machine_is_d2plug() (machine_arch_type == MACH_TYPE_D2PLUG)
+#else
+# define machine_is_d2plug() (0)
+#endif
+
+#ifdef CONFIG_MACH_KZM9D
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KZM9D
+# endif
+# define machine_is_kzm9d() (machine_arch_type == MACH_TYPE_KZM9D)
+#else
+# define machine_is_kzm9d() (0)
+#endif
+
+#ifdef CONFIG_MACH_VERDI_LTE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VERDI_LTE
+# endif
+# define machine_is_verdi_lte() (machine_arch_type == MACH_TYPE_VERDI_LTE)
+#else
+# define machine_is_verdi_lte() (0)
+#endif
+
+#ifdef CONFIG_MACH_NANOZOOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NANOZOOM
+# endif
+# define machine_is_nanozoom() (machine_arch_type == MACH_TYPE_NANOZOOM)
+#else
+# define machine_is_nanozoom() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM3730_SOM_LV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM3730_SOM_LV
+# endif
+# define machine_is_dm3730_som_lv() (machine_arch_type == MACH_TYPE_DM3730_SOM_LV)
+#else
+# define machine_is_dm3730_som_lv() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM3730_TORPEDO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM3730_TORPEDO
+# endif
+# define machine_is_dm3730_torpedo() (machine_arch_type == MACH_TYPE_DM3730_TORPEDO)
+#else
+# define machine_is_dm3730_torpedo() (0)
+#endif
+
+#ifdef CONFIG_MACH_ANCHOVY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ANCHOVY
+# endif
+# define machine_is_anchovy() (machine_arch_type == MACH_TYPE_ANCHOVY)
+#else
+# define machine_is_anchovy() (0)
+#endif
+
+#ifdef CONFIG_MACH_RE2REV20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RE2REV20
+# endif
+# define machine_is_re2rev20() (machine_arch_type == MACH_TYPE_RE2REV20)
+#else
+# define machine_is_re2rev20() (0)
+#endif
+
+#ifdef CONFIG_MACH_RE2REV21
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RE2REV21
+# endif
+# define machine_is_re2rev21() (machine_arch_type == MACH_TYPE_RE2REV21)
+#else
+# define machine_is_re2rev21() (0)
+#endif
+
+#ifdef CONFIG_MACH_CNS21XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CNS21XX
+# endif
+# define machine_is_cns21xx() (machine_arch_type == MACH_TYPE_CNS21XX)
+#else
+# define machine_is_cns21xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_RIDER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RIDER
+# endif
+# define machine_is_rider() (machine_arch_type == MACH_TYPE_RIDER)
+#else
+# define machine_is_rider() (0)
+#endif
+
+#ifdef CONFIG_MACH_NSK330
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NSK330
+# endif
+# define machine_is_nsk330() (machine_arch_type == MACH_TYPE_NSK330)
+#else
+# define machine_is_nsk330() (0)
+#endif
+
+#ifdef CONFIG_MACH_CNS2133EVB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CNS2133EVB
+# endif
+# define machine_is_cns2133evb() (machine_arch_type == MACH_TYPE_CNS2133EVB)
+#else
+# define machine_is_cns2133evb() (0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_816X_MOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_Z3_816X_MOD
+# endif
+# define machine_is_z3_816x_mod() (machine_arch_type == MACH_TYPE_Z3_816X_MOD)
+#else
+# define machine_is_z3_816x_mod() (0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_814X_MOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_Z3_814X_MOD
+# endif
+# define machine_is_z3_814x_mod() (machine_arch_type == MACH_TYPE_Z3_814X_MOD)
+#else
+# define machine_is_z3_814x_mod() (0)
+#endif
+
+#ifdef CONFIG_MACH_BEECT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BEECT
+# endif
+# define machine_is_beect() (machine_arch_type == MACH_TYPE_BEECT)
+#else
+# define machine_is_beect() (0)
+#endif
+
+#ifdef CONFIG_MACH_DMA_THUNDERBUG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DMA_THUNDERBUG
+# endif
+# define machine_is_dma_thunderbug() (machine_arch_type == MACH_TYPE_DMA_THUNDERBUG)
+#else
+# define machine_is_dma_thunderbug() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMN_AT91SAM9G20
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMN_AT91SAM9G20
+# endif
+# define machine_is_omn_at91sam9g20() (machine_arch_type == MACH_TYPE_OMN_AT91SAM9G20)
+#else
+# define machine_is_omn_at91sam9g20() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX25_E2S_UC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX25_E2S_UC
+# endif
+# define machine_is_mx25_e2s_uc() (machine_arch_type == MACH_TYPE_MX25_E2S_UC)
+#else
+# define machine_is_mx25_e2s_uc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MIONE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MIONE
+# endif
+# define machine_is_mione() (machine_arch_type == MACH_TYPE_MIONE)
+#else
+# define machine_is_mione() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_TCU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOP9000_TCU
+# endif
+# define machine_is_top9000_tcu() (machine_arch_type == MACH_TYPE_TOP9000_TCU)
+#else
+# define machine_is_top9000_tcu() (0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_BSL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TOP9000_BSL
+# endif
+# define machine_is_top9000_bsl() (machine_arch_type == MACH_TYPE_TOP9000_BSL)
+#else
+# define machine_is_top9000_bsl() (0)
+#endif
+
+#ifdef CONFIG_MACH_KINGDOM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KINGDOM
+# endif
+# define machine_is_kingdom() (machine_arch_type == MACH_TYPE_KINGDOM)
+#else
+# define machine_is_kingdom() (0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO460
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ARMADILLO460
+# endif
+# define machine_is_armadillo460() (machine_arch_type == MACH_TYPE_ARMADILLO460)
+#else
+# define machine_is_armadillo460() (0)
+#endif
+
+#ifdef CONFIG_MACH_LQ2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LQ2
+# endif
+# define machine_is_lq2() (machine_arch_type == MACH_TYPE_LQ2)
+#else
+# define machine_is_lq2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SWEDA_TMS2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SWEDA_TMS2
+# endif
+# define machine_is_sweda_tms2() (machine_arch_type == MACH_TYPE_SWEDA_TMS2)
+#else
+# define machine_is_sweda_tms2() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_LOCO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX53_LOCO
+# endif
+# define machine_is_mx53_loco() (machine_arch_type == MACH_TYPE_MX53_LOCO)
+#else
+# define machine_is_mx53_loco() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A8
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_A8
+# endif
+# define machine_is_acer_a8() (machine_arch_type == MACH_TYPE_ACER_A8)
+#else
+# define machine_is_acer_a8() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_GAUGUIN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_GAUGUIN
+# endif
+# define machine_is_acer_gauguin() (machine_arch_type == MACH_TYPE_ACER_GAUGUIN)
+#else
+# define machine_is_acer_gauguin() (0)
+#endif
+
+#ifdef CONFIG_MACH_GUPPY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GUPPY
+# endif
+# define machine_is_guppy() (machine_arch_type == MACH_TYPE_GUPPY)
+#else
+# define machine_is_guppy() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX61_ARD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX61_ARD
+# endif
+# define machine_is_mx61_ard() (machine_arch_type == MACH_TYPE_MX61_ARD)
+#else
+# define machine_is_mx61_ard() (0)
+#endif
+
+#ifdef CONFIG_MACH_TX53
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TX53
+# endif
+# define machine_is_tx53() (machine_arch_type == MACH_TYPE_TX53)
+#else
+# define machine_is_tx53() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_CASE_A3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAPL138_CASE_A3
+# endif
+# define machine_is_omapl138_case_a3() (machine_arch_type == MACH_TYPE_OMAPL138_CASE_A3)
+#else
+# define machine_is_omapl138_case_a3() (0)
+#endif
+
+#ifdef CONFIG_MACH_UEMD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_UEMD
+# endif
+# define machine_is_uemd() (machine_arch_type == MACH_TYPE_UEMD)
+#else
+# define machine_is_uemd() (0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51MUT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CCWMX51MUT
+# endif
+# define machine_is_ccwmx51mut() (machine_arch_type == MACH_TYPE_CCWMX51MUT)
+#else
+# define machine_is_ccwmx51mut() (0)
+#endif
+
+#ifdef CONFIG_MACH_ROCKHOPPER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ROCKHOPPER
+# endif
+# define machine_is_rockhopper() (machine_arch_type == MACH_TYPE_ROCKHOPPER)
+#else
+# define machine_is_rockhopper() (0)
+#endif
+
+#ifdef CONFIG_MACH_NOOKCOLOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NOOKCOLOR
+# endif
+# define machine_is_nookcolor() (machine_arch_type == MACH_TYPE_NOOKCOLOR)
+#else
+# define machine_is_nookcolor() (0)
+#endif
+
+#ifdef CONFIG_MACH_HKDKC100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HKDKC100
+# endif
+# define machine_is_hkdkc100() (machine_arch_type == MACH_TYPE_HKDKC100)
+#else
+# define machine_is_hkdkc100() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS42XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS42XX
+# endif
+# define machine_is_ts42xx() (machine_arch_type == MACH_TYPE_TS42XX)
+#else
+# define machine_is_ts42xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_AEBL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AEBL
+# endif
+# define machine_is_aebl() (machine_arch_type == MACH_TYPE_AEBL)
+#else
+# define machine_is_aebl() (0)
+#endif
+
+#ifdef CONFIG_MACH_WARIO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WARIO
+# endif
+# define machine_is_wario() (machine_arch_type == MACH_TYPE_WARIO)
+#else
+# define machine_is_wario() (0)
+#endif
+
+#ifdef CONFIG_MACH_GFS_SPM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GFS_SPM
+# endif
+# define machine_is_gfs_spm() (machine_arch_type == MACH_TYPE_GFS_SPM)
+#else
+# define machine_is_gfs_spm() (0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T3730
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CM_T3730
+# endif
+# define machine_is_cm_t3730() (machine_arch_type == MACH_TYPE_CM_T3730)
+#else
+# define machine_is_cm_t3730() (0)
+#endif
+
+#ifdef CONFIG_MACH_ISC3
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ISC3
+# endif
+# define machine_is_isc3() (machine_arch_type == MACH_TYPE_ISC3)
+#else
+# define machine_is_isc3() (0)
+#endif
+
+#ifdef CONFIG_MACH_RASCAL
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RASCAL
+# endif
+# define machine_is_rascal() (machine_arch_type == MACH_TYPE_RASCAL)
+#else
+# define machine_is_rascal() (0)
+#endif
+
+#ifdef CONFIG_MACH_HREFV60
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HREFV60
+# endif
+# define machine_is_hrefv60() (machine_arch_type == MACH_TYPE_HREFV60)
+#else
+# define machine_is_hrefv60() (0)
+#endif
+
+#ifdef CONFIG_MACH_TPT_2_0
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TPT_2_0
+# endif
+# define machine_is_tpt_2_0() (machine_arch_type == MACH_TYPE_TPT_2_0)
+#else
+# define machine_is_tpt_2_0() (0)
+#endif
+
+#ifdef CONFIG_MACH_PYRAMID_TD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PYRAMID_TD
+# endif
+# define machine_is_pyramid_td() (machine_arch_type == MACH_TYPE_PYRAMID_TD)
+#else
+# define machine_is_pyramid_td() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPLENDOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPLENDOR
+# endif
+# define machine_is_splendor() (machine_arch_type == MACH_TYPE_SPLENDOR)
+#else
+# define machine_is_splendor() (0)
+#endif
+
+#ifdef CONFIG_MACH_GUF_PLANET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GUF_PLANET
+# endif
+# define machine_is_guf_planet() (machine_arch_type == MACH_TYPE_GUF_PLANET)
+#else
+# define machine_is_guf_planet() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_QT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_QT
+# endif
+# define machine_is_msm8x60_qt() (machine_arch_type == MACH_TYPE_MSM8X60_QT)
+#else
+# define machine_is_msm8x60_qt() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTC_HD_MINI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTC_HD_MINI
+# endif
+# define machine_is_htc_hd_mini() (machine_arch_type == MACH_TYPE_HTC_HD_MINI)
+#else
+# define machine_is_htc_hd_mini() (0)
+#endif
+
+#ifdef CONFIG_MACH_ATHENE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ATHENE
+# endif
+# define machine_is_athene() (machine_arch_type == MACH_TYPE_ATHENE)
+#else
+# define machine_is_athene() (0)
+#endif
+
+#ifdef CONFIG_MACH_DEEP_R_EK_1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DEEP_R_EK_1
+# endif
+# define machine_is_deep_r_ek_1() (machine_arch_type == MACH_TYPE_DEEP_R_EK_1)
+#else
+# define machine_is_deep_r_ek_1() (0)
+#endif
+
+#ifdef CONFIG_MACH_VIVOW_CT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VIVOW_CT
+# endif
+# define machine_is_vivow_ct() (machine_arch_type == MACH_TYPE_VIVOW_CT)
+#else
+# define machine_is_vivow_ct() (0)
+#endif
+
+#ifdef CONFIG_MACH_NERY_1000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NERY_1000
+# endif
+# define machine_is_nery_1000() (machine_arch_type == MACH_TYPE_NERY_1000)
+#else
+# define machine_is_nery_1000() (0)
+#endif
+
+#ifdef CONFIG_MACH_RFL109145_SSRV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RFL109145_SSRV
+# endif
+# define machine_is_rfl109145_ssrv() (machine_arch_type == MACH_TYPE_RFL109145_SSRV)
+#else
+# define machine_is_rfl109145_ssrv() (0)
+#endif
+
+#ifdef CONFIG_MACH_NMH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NMH
+# endif
+# define machine_is_nmh() (machine_arch_type == MACH_TYPE_NMH)
+#else
+# define machine_is_nmh() (0)
+#endif
+
+#ifdef CONFIG_MACH_WN802T
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WN802T
+# endif
+# define machine_is_wn802t() (machine_arch_type == MACH_TYPE_WN802T)
+#else
+# define machine_is_wn802t() (0)
+#endif
+
+#ifdef CONFIG_MACH_DRAGONET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DRAGONET
+# endif
+# define machine_is_dragonet() (machine_arch_type == MACH_TYPE_DRAGONET)
+#else
+# define machine_is_dragonet() (0)
+#endif
+
+#ifdef CONFIG_MACH_GENEVA_B
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GENEVA_B
+# endif
+# define machine_is_geneva_b() (machine_arch_type == MACH_TYPE_GENEVA_B)
+#else
+# define machine_is_geneva_b() (0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263DESK16L
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AT91SAM9263DESK16L
+# endif
+# define machine_is_at91sam9263desk16l() (machine_arch_type == MACH_TYPE_AT91SAM9263DESK16L)
+#else
+# define machine_is_at91sam9263desk16l() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMHANA_SV
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMHANA_SV
+# endif
+# define machine_is_bcmhana_sv() (machine_arch_type == MACH_TYPE_BCMHANA_SV)
+#else
+# define machine_is_bcmhana_sv() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMHANA_TABLET
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMHANA_TABLET
+# endif
+# define machine_is_bcmhana_tablet() (machine_arch_type == MACH_TYPE_BCMHANA_TABLET)
+#else
+# define machine_is_bcmhana_tablet() (0)
+#endif
+
+#ifdef CONFIG_MACH_KOI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KOI
+# endif
+# define machine_is_koi() (machine_arch_type == MACH_TYPE_KOI)
+#else
+# define machine_is_koi() (0)
+#endif
+
+#ifdef CONFIG_MACH_TS4800
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TS4800
+# endif
+# define machine_is_ts4800() (machine_arch_type == MACH_TYPE_TS4800)
+#else
+# define machine_is_ts4800() (0)
+#endif
+
+#ifdef CONFIG_MACH_TQMA9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TQMA9263
+# endif
+# define machine_is_tqma9263() (machine_arch_type == MACH_TYPE_TQMA9263)
+#else
+# define machine_is_tqma9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_HOLIDAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HOLIDAY
+# endif
+# define machine_is_holiday() (machine_arch_type == MACH_TYPE_HOLIDAY)
+#else
+# define machine_is_holiday() (0)
+#endif
+
+#ifdef CONFIG_MACH_DMA6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DMA6410
+# endif
+# define machine_is_dma_6410() (machine_arch_type == MACH_TYPE_DMA6410)
+#else
+# define machine_is_dma_6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCATS_OVERLAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCATS_OVERLAY
+# endif
+# define machine_is_pcats_overlay() (machine_arch_type == MACH_TYPE_PCATS_OVERLAY)
+#else
+# define machine_is_pcats_overlay() (0)
+#endif
+
+#ifdef CONFIG_MACH_HWGW6410
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HWGW6410
+# endif
+# define machine_is_hwgw6410() (machine_arch_type == MACH_TYPE_HWGW6410)
+#else
+# define machine_is_hwgw6410() (0)
+#endif
+
+#ifdef CONFIG_MACH_SHENZHOU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SHENZHOU
+# endif
+# define machine_is_shenzhou() (machine_arch_type == MACH_TYPE_SHENZHOU)
+#else
+# define machine_is_shenzhou() (0)
+#endif
+
+#ifdef CONFIG_MACH_CWME9210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CWME9210
+# endif
+# define machine_is_cwme9210() (machine_arch_type == MACH_TYPE_CWME9210)
+#else
+# define machine_is_cwme9210() (0)
+#endif
+
+#ifdef CONFIG_MACH_CWME9210JS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CWME9210JS
+# endif
+# define machine_is_cwme9210js() (machine_arch_type == MACH_TYPE_CWME9210JS)
+#else
+# define machine_is_cwme9210js() (0)
+#endif
+
+#ifdef CONFIG_MACH_PGS_SITARA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PGS_SITARA
+# endif
+# define machine_is_pgs_v1() (machine_arch_type == MACH_TYPE_PGS_SITARA)
+#else
+# define machine_is_pgs_v1() (0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI_TEGRA2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2
+# endif
+# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
+#else
+# define machine_is_colibri_tegra2() (0)
+#endif
+
+#ifdef CONFIG_MACH_W21
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_W21
+# endif
+# define machine_is_w21() (machine_arch_type == MACH_TYPE_W21)
+#else
+# define machine_is_w21() (0)
+#endif
+
+#ifdef CONFIG_MACH_POLYSAT1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_POLYSAT1
+# endif
+# define machine_is_polysat1() (machine_arch_type == MACH_TYPE_POLYSAT1)
+#else
+# define machine_is_polysat1() (0)
+#endif
+
+#ifdef CONFIG_MACH_DATAWAY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DATAWAY
+# endif
+# define machine_is_dataway() (machine_arch_type == MACH_TYPE_DATAWAY)
+#else
+# define machine_is_dataway() (0)
+#endif
+
+#ifdef CONFIG_MACH_COBRAL138
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_COBRAL138
+# endif
+# define machine_is_cobral138() (machine_arch_type == MACH_TYPE_COBRAL138)
+#else
+# define machine_is_cobral138() (0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERPCS8
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ROVERPCS8
+# endif
+# define machine_is_roverpcs8() (machine_arch_type == MACH_TYPE_ROVERPCS8)
+#else
+# define machine_is_roverpcs8() (0)
+#endif
+
+#ifdef CONFIG_MACH_MARVELC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MARVELC
+# endif
+# define machine_is_marvelc() (machine_arch_type == MACH_TYPE_MARVELC)
+#else
+# define machine_is_marvelc() (0)
+#endif
+
+#ifdef CONFIG_MACH_NAVEFIHID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NAVEFIHID
+# endif
+# define machine_is_navefihid() (machine_arch_type == MACH_TYPE_NAVEFIHID)
+#else
+# define machine_is_navefihid() (0)
+#endif
+
+#ifdef CONFIG_MACH_DM365_CV100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DM365_CV100
+# endif
+# define machine_is_dm365_cv100() (machine_arch_type == MACH_TYPE_DM365_CV100)
+#else
+# define machine_is_dm365_cv100() (0)
+#endif
+
+#ifdef CONFIG_MACH_ABLE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ABLE
+# endif
+# define machine_is_able() (machine_arch_type == MACH_TYPE_ABLE)
+#else
+# define machine_is_able() (0)
+#endif
+
+#ifdef CONFIG_MACH_LEGACY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LEGACY
+# endif
+# define machine_is_legacy() (machine_arch_type == MACH_TYPE_LEGACY)
+#else
+# define machine_is_legacy() (0)
+#endif
+
+#ifdef CONFIG_MACH_ICONG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ICONG
+# endif
+# define machine_is_icong() (machine_arch_type == MACH_TYPE_ICONG)
+#else
+# define machine_is_icong() (0)
+#endif
+
+#ifdef CONFIG_MACH_ROVER_G8
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ROVER_G8
+# endif
+# define machine_is_rover_g8() (machine_arch_type == MACH_TYPE_ROVER_G8)
+#else
+# define machine_is_rover_g8() (0)
+#endif
+
+#ifdef CONFIG_MACH_T5388P
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_T5388P
+# endif
+# define machine_is_t5388p() (machine_arch_type == MACH_TYPE_T5388P)
+#else
+# define machine_is_t5388p() (0)
+#endif
+
+#ifdef CONFIG_MACH_DINGO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DINGO
+# endif
+# define machine_is_dingo() (machine_arch_type == MACH_TYPE_DINGO)
+#else
+# define machine_is_dingo() (0)
+#endif
+
+#ifdef CONFIG_MACH_GOFLEXHOME
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GOFLEXHOME
+# endif
+# define machine_is_goflexhome() (machine_arch_type == MACH_TYPE_GOFLEXHOME)
+#else
+# define machine_is_goflexhome() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a1649eef0..77349530f 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -327,12 +327,12 @@ void setup_revision_tag(struct tag **in_params)
}
#endif /* CONFIG_REVISION_TAG */
-
static void setup_end_tag (bd_t *bd)
{
params->hdr.tag = ATAG_NONE;
params->hdr.size = 0;
}
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
static ulong get_sp(void)
{
@@ -341,5 +341,3 @@ static ulong get_sp(void)
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
-
-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/i386/config.mk b/arch/i386/config.mk
index 3fb97c198..a84af6321 100644
--- a/arch/i386/config.mk
+++ b/arch/i386/config.mk
@@ -21,8 +21,6 @@
# MA 02111-1307 USA
#
-CROSS_COMPILE ?= i386-linux-
-
STANDALONE_LOAD_ADDR = 0x40000
PLATFORM_CPPFLAGS += -fno-strict-aliasing
@@ -33,8 +31,13 @@ PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding)
PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time))
PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
-PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
+PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
+
+PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
+
+LDFLAGS_u-boot += --gc-sections -pie
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
-LDFLAGS += --cref
-LDFLAGS_u-boot += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections
diff --git a/arch/i386/cpu/config.mk b/arch/i386/cpu/config.mk
index 16a160d2f..9b2e2c9fe 100644
--- a/arch/i386/cpu/config.mk
+++ b/arch/i386/cpu/config.mk
@@ -21,6 +21,12 @@
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS +=
+CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror
+
+# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
+LDPPFLAGS += -DRESET_SEG_START=0xffff0000
+LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
+LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
+LDPPFLAGS += -DSTART_16=0xf800
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c
index ae40384f0..2339cd41b 100644
--- a/arch/i386/cpu/cpu.c
+++ b/arch/i386/cpu/cpu.c
@@ -35,6 +35,8 @@
#include <common.h>
#include <command.h>
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
#include <asm/interrupt.h>
/* Constructor for a conventional segment GDT (or LDT) entry */
@@ -46,13 +48,6 @@
(((base) & 0x00ffffffULL) << 16) | \
(((limit) & 0x0000ffffULL)))
-/* Simple and small GDT entries for booting only */
-
-#define GDT_ENTRY_32BIT_CS 2
-#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1)
-#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1)
-#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1)
-
/*
* Set up the GDT
*/
@@ -92,26 +87,40 @@ static void reload_gdt(void)
}
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
{
+ const u32 em_rst = ~X86_CR0_EM;
+ const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
/* initialize FPU, reset EM, set MP and NE */
asm ("fninit\n" \
- "movl %cr0, %eax\n" \
- "andl $~0x4, %eax\n" \
- "orl $0x22, %eax\n" \
- "movl %eax, %cr0\n" );
+ "movl %%cr0, %%eax\n" \
+ "andl %0, %%eax\n" \
+ "orl %1, %%eax\n" \
+ "movl %%eax, %%cr0\n" \
+ : : "i" (em_rst), "i" (mp_ne_set) : "eax");
return 0;
}
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
{
+ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl %0, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
return 0;
}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c
index e4d0868cd..1cefe02c8 100644
--- a/arch/i386/cpu/interrupts.c
+++ b/arch/i386/cpu/interrupts.c
@@ -29,6 +29,8 @@
#include <common.h>
#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
@@ -108,6 +110,7 @@ void dump_regs(struct irq_regs *regs)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
+ unsigned long sp;
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
(u16)regs->xcs, regs->eip, regs->eflags);
@@ -139,6 +142,20 @@ void dump_regs(struct irq_regs *regs)
d7 = get_debugreg(7);
printf("DR6: %08lx DR7: %08lx\n",
d6, d7);
+
+ printf("Stack:\n");
+ sp = regs->esp;
+
+ sp += 64;
+
+ while (sp > (regs->esp - 16)) {
+ if (sp == regs->esp)
+ printf("--->");
+ else
+ printf(" ");
+ printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
+ sp -= 4;
+ }
}
struct idt_entry {
@@ -221,7 +238,7 @@ int disable_interrupts(void)
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
- return (flags&0x200); /* IE flags is bit 9 */
+ return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
}
/* IRQ Low-Level Service Routine */
diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile
index fb47c2099..54260b610 100644
--- a/arch/i386/cpu/sc520/Makefile
+++ b/arch/i386/cpu/sc520/Makefile
@@ -32,11 +32,12 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_PCI) += sc520_pci.o
+COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
+SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 7acd471d9..d0c313b91 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -26,169 +26,43 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/processor-flags.h>
#include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * utility functions for boards based on the AMD sc520
- *
- * void init_sc520(void)
- * unsigned long init_sc520_dram(void)
- */
+sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
-
-void init_sc520(void)
+int cpu_init_f(void)
{
- /*
- * Set the UARTxCTL register at it's slower,
- * baud clock giving us a 1.8432 MHz reference
- */
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
-
- /* first set the timer pin mapping */
- writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
-
- /* enable PCI bus arbiter (concurrent mode) */
- writeb(0x02, &sc520_mmcr->sysarbctl);
-
- /* enable external grants */
- writeb(0x1f, &sc520_mmcr->sysarbmenb);
-
- /* enable posted-writes */
- writeb(0x04, &sc520_mmcr->hbctl);
-
if (CONFIG_SYS_SC520_HIGH_SPEED) {
/* set it to 133 MHz and write back */
writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 133000000;
- printf("## CPU Speed set to 133MHz\n");
} else {
/* set it to 100 MHz and write back */
writeb(0x01, &sc520_mmcr->cpuctl);
- printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
-
/* wait at least one millisecond */
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl $0x9fffffff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
+ return x86_cpu_init_f();
}
-unsigned long init_sc520_dram(void)
+int cpu_init_r(void)
{
- bd_t *bd = gd->bd;
-
- u32 dram_present=0;
- u32 dram_ctrl;
-
-#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
- /* these memory control registers are set up in the assember part,
- * in sc520_asm.S, during 'mem_init'. If we muck with them here,
- * after we are running a stack in RAM, we have troubles. Besides,
- * these refresh and delay values are better ? simply specified
- * outright in the include/configs/{cfg} file since the HW designer
- * simply dictates it.
- */
-#else
- u8 tmp;
- u8 val;
-
- int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
- int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
- int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
-
- /* set SDRAM speed here */
-
- refresh_rate /= 78;
- if (refresh_rate <= 1) {
- val = 0; /* 7.8us */
- } else if (refresh_rate == 2) {
- val = 1; /* 15.6us */
- } else if (refresh_rate == 3 || refresh_rate == 4) {
- val = 2; /* 31.2us */
- } else {
- val = 3; /* 62.4us */
- }
-
- tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
- writeb(tmp, &sc520_mmcr->drcctl);
+ /* Disable the PAR used for CAR */
+ writel(0x0000000, &sc520_mmcr->par[2]);
- val = readb(&sc520_mmcr->drctmctl) & 0xf0;
-
- if (cas_precharge_delay==3) {
- val |= 0x04; /* 3T */
- } else if (cas_precharge_delay==4) {
- val |= 0x08; /* 4T */
- } else if (cas_precharge_delay>4) {
- val |= 0x0c;
- }
-
- if (ras_cas_delay > 3) {
- val |= 2;
- } else {
- val |= 1;
- }
- writeb(val, &c520_mmcr->drctmctl);
-#endif
-
- /*
- * We read-back the configuration of the dram
- * controller that the assembly code wrote
- */
- dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
- bd->bi_dram[0].start = 0;
- if (dram_ctrl & 0x80) {
- /* bank 0 enabled */
- dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
- bd->bi_dram[0].size = bd->bi_dram[1].start;
- } else {
- bd->bi_dram[0].size = 0;
- bd->bi_dram[1].start = bd->bi_dram[0].start;
- }
-
- if (dram_ctrl & 0x8000) {
- /* bank 1 enabled */
- dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
- bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
- } else {
- bd->bi_dram[1].size = 0;
- bd->bi_dram[2].start = bd->bi_dram[1].start;
- }
-
- if (dram_ctrl & 0x800000) {
- /* bank 2 enabled */
- dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
- bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
- } else {
- bd->bi_dram[2].size = 0;
- bd->bi_dram[3].start = bd->bi_dram[2].start;
- }
-
- if (dram_ctrl & 0x80000000) {
- /* bank 3 enabled */
- dram_present = (dram_ctrl & 0x7f000000) >> 2;
- bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
- } else {
- bd->bi_dram[3].size = 0;
- }
- gd->ram_size = dram_present;
+ /* turn on the SDRAM write buffer */
+ writeb(0x11, &sc520_mmcr->dbctl);
- return dram_present;
+ return x86_cpu_init_r();
}
#ifdef CONFIG_SYS_SC520_RESET
diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
deleted file mode 100644
index 63c14b7eb..000000000
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ /dev/null
@@ -1,615 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* This file is largely based on code obtned from AMD. AMD's original
- * copyright is included below
- */
-
-/* TITLE SIZER - Aspen DRAM Sizing Routine.
- * =============================================================================
- *
- * Copyright 1999 Advanced Micro Devices, Inc.
- * You may redistribute this program and/or modify this program under the terms
- * of the GNU General Public License as published by the Free Software Foundation;
- * either version 2 of the License, or (at your option) any later version.
- *
- * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
- *
- * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
- * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
- * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
- * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
- * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
- * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
- * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
- * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
- * LIMITATION MAY NOT APPLY TO YOU.
- *
- * AMD does not assume any responsibility for any errors that may appear in
- * the Materials nor any responsibility to support or update the Materials.
- * AMD retains the right to make changes to its test specifications at any
- * time, without notice.
- * ==============================================================================
- */
-
-/*
- ******************************************************************************
- *
- * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
- *
- *
- *
- * FUNCTIONS : sizemem() - jumped to, not called. To be executed after
- * reset to determine the size of the SDRAM DIMMs. Initializes
- * the memory subsystem.
- *
- *
- * AUTHOR : Buddy Fey - Original.
- *
- *
- * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
- * NOTE: This is a small memory model version
- *
- *
- * INPUTS : BP contains return address offset
- * CACHE is assumed to be disabled.
- * The FS segment limit has already been set to big real mode
- * (full 32-bit addressing capability)
- *
- *
- * OUTPUTS : None
- *
- *
- * REG USE : ax,bx,cx,dx,di,si,bp, fs
- *
- *
- * REVISION : See PVCS info below
- *
- *
- * TEST PLAN CROSS REFERENCE:
- *
- *
- * $Workfile: $
- * $Revision: 1.2 $
- * $Date: 1999/09/22 12:49:33 $
- * $Author: chipf $
- * $Log: sizer.asm $
- * Revision 1.2 1999/09/22 12:49:33 chipf
- * Add legal header
- *
- *******************************************************************************
- */
-
-
-/*******************************************************************************
- * FUNCTIONAL DESCRIPTION:
- * This routine is called to autodetect the geometry of the DRAM.
- *
- * This routine is called to determine the number of column bits for the DRAM
- * devices in this external bank. This routine assumes that the external bank
- * has been configured for an 11-bit column and for 4 internal banks. This gives
- * us the maximum address reach in memory. By writing a test value to the max
- * address and locating where it aliases to, we can determine the number of valid
- * column bits.
- *
- * This routine is called to determine the number of internal banks each DRAM
- * device has. The external bank (under test) is configured for maximum reach
- * with 11-bit columns and 4 internal banks. This routine will write to a max
- * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
- * that column is a "don't care". If BA1 does not affect write/read of data,
- * then this device has only 2 internal banks.
- *
- * This routine is called to determine the ending address for this external
- * bank of SDRAM. We write to a max address with a data value and then disable
- * row address bits looking for "don't care" locations. Each "don't care" bit
- * represents a dividing of the maximum density (128M) by 2. By dividing the
- * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
- * determined during sizing, we set the proper density.
- *
- * WARNINGS.
- * bp must be preserved because it is used for return linkage.
- *
- * EXIT
- * nothing returned - but the memory subsystem is enabled
- *******************************************************************************
- */
-
-#include <config.h>
-
-.section .text
-.equ DRCCTL, 0x0fffef010 /* DRAM control register */
-.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
-.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
-.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
-.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
-.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
-.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
-
-.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
-.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
-.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
-.equ COL09_ADR, 0x0e000600 /* 9 col addrs */
-.equ COL08_ADR, 0x0e000200 /* 8 col addrs */
-.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
-.equ ROW13_ADR, 0x07000000 /* 13 row addrs */
-.equ ROW12_ADR, 0x03000000 /* 12 row addrs */
-.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
-.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
-.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
-.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
-.equ COL09_DATA, 0x09090909 /* 9 col data */
-.equ COL08_DATA, 0x08080808 /* 8 col data */
-.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
-.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
-.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
-.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
-.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
-
-.globl mem_init
-mem_init:
- /* Preserve Boot Flags */
- movl %ebx, %ebp
-
- /* initialize dram controller registers */
- xorw %ax, %ax
- movl $DBCTL, %edi
- movb %al, (%edi) /* disable write buffer */
-
- movl $ECCCTL, %edi
- movb %al, (%edi) /* disable ECC */
-
- movl $DRCTMCTL, %edi
- movb $0x1e, %al /* Set SDRAM timing for slowest */
- movb %al, (%edi)
-
- /* setup loop to do 4 external banks starting with bank 3 */
- movl $0xff000000, %eax /* enable last bank and setup */
- movl $DRCBENDADR, %edi /* ending address register */
- movl %eax, (%edi)
-
- movl $DRCCFG, %edi /* setup */
- movw $0xbbbb, %ax /* dram config register for */
- movw %ax, (%edi)
-
- /* issue a NOP to all DRAMs */
- movl $DRCCTL, %edi /* setup DRAM control register with */
- movb $0x01, %al /* Disable refresh,disable write buffer */
- movb %al, (%edi)
- movl $CACHELINESZ, %esi /* just a dummy address to write for */
- movw %ax, (%esi)
-
- /* delay for 100 usec? */
- movw $100, %cx
-sizdelay:
- loop sizdelay
-
- /* issue all banks precharge */
- movb $0x02, %al
- movb %al, (%edi)
- movw %ax, (%esi)
-
- /* issue 2 auto refreshes to all banks */
- movb $0x04, %al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $0x02, %cx
-refresh1:
- movw %ax, (%esi)
- loop refresh1
-
- /* issue LOAD MODE REGISTER command */
- movb $0x03, %al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
-
- /* issue 8 more auto refreshes to all banks */
- movb $0x04, %al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $0x0008, %cx
-refresh2:
- movw %ax, (%esi)
- loop refresh2
-
- /* set control register to NORMAL mode */
- movb $0x00, %al /* Normal mode value */
- movb %al, (%edi)
-
- /*
- * size dram starting with external bank 3
- * moving to external bank 0
- */
- movl $0x3, %ecx /* start with external bank 3 */
-
-nextbank:
-
- /* write col 11 wrap adr */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
- movl %eax, (%esi) /* write max col pattern at max col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 10 wrap adr */
- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
- movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 9 wrap adr */
- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
- movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 8 wrap adr */
- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
- movl %eax, (%esi) /* write min col pattern @ min col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 14 wrap adr */
- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
- movl %eax, (%esi) /* write max row pattern at max row adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 13 wrap adr */
- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
- movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 12 wrap adr */
- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
- movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 11 wrap adr */
- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
- movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /*
- * write row 10 wrap adr --- this write is really to determine
- * number of banks
- */
- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
- movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /*
- * read data @ row 12 wrap adr to determine * banks,
- * and read data @ row 14 wrap adr to determine * rows.
- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
- */
- xorw %di, %di /* value for 2 banks in DI */
- movl (%esi), %ebx /* read from 12 row wrap to check banks */
- /* (esi is setup from the write to row 12 wrap) */
- cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
- jz only2 /* if pattern == AA, we only have 2 banks */
-
- /* 4 banks */
-
- movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
- jz only2
- cmpl $ROW12_DATA, %ebx /* and 12 */
- jnz bad_ram /* its bad if not 11 or 12! */
-
- /* fall through */
-only2:
- /*
- * validate row mask
- */
- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
- movl (%esi), %eax /* read actual number of rows @ row14 adr */
-
- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
- jb bad_ram
-
- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
- ja bad_ram
-
- cmpb %ah, %al /* verify all 4 bytes of dword same */
- jnz bad_ram
- movl %eax, %ebx
- shrl $16, %ebx
- cmpw %bx, %ax
- jnz bad_ram
-
- /*
- * read col 11 wrap adr for real column data value
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl (%esi), %eax /* read real col number at max col adr */
-
- /*
- * validate column data
- */
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
- jb bad_ram
-
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
- ja bad_ram
-
- subl $COL08_DATA, %eax /* normalize column data to zero */
- jc bad_ram
- cmpb %ah, %al /* verify all 4 bytes of dword equal */
- jnz bad_ram
- movl %eax, %edx
- shrl $16, %edx
- cmpw %dx, %ax
- jnz bad_ram
-
- /*
- * merge bank and col data together
- */
- addw %di, %dx /* merge of bank and col info in dl */
-
- /*
- * fix ending addr mask based upon col info
- */
- movb $0x03, %al
- subb %dh, %al /* dh contains the overflow from the bank/col merge */
- movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
- xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
- shrb %cl, %dh
- incb %dh /* ending addr is 1 greater than real end */
- xchgw %cx, %ax /* cx is bank number again */
-
-bad_reint:
- /*
- * issue all banks precharge
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x02, %al /* All banks precharge */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
-
- /*
- * update ENDING ADDRESS REGISTER
- */
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movl %ecx, %ebx
- addl %ebx, %edi
- movb %dh, (%edi)
-
- /*
- * update CONFIG REGISTER
- */
- xorb %dh, %dh
- movw $0x000f, %bx
- movw %cx, %ax
- shlw $2, %ax
- xchgw %cx, %ax
- shlw %cl, %dx
- shlw %cl, %bx
- notw %bx
- xchgw %cx, %ax
- movl $DRCCFG, %edi
- movw (%edi), %ax
- andw %bx, %ax
- orw %dx, %ax
- movw %ax, (%edi)
- jcxz cleanup
-
- decw %cx
- movl %ecx, %ebx
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movb $0xff, %al
- addl %ebx, %edi
- movb %al, (%edi)
-
- /*
- * set control register to NORMAL mode
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x00, %al /* Normal mode value */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
- jmp nextbank
-
-cleanup:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movw $0x04, %cx
- xorw %ax, %ax
-cleanuplp:
- movb (%edi), %al
- orb %al, %al
- jz emptybank
-
- addb %ah, %al
- jns nottoomuch
-
- movb $0x7f, %al
-nottoomuch:
- movb %al, %ah
- orb $0x80, %al
- movb %al, (%edi)
-emptybank:
- incl %edi
- loop cleanuplp
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
- /* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
- movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
- movb %al, (%edi)
-#else
-#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
- /*
- * Set the CAS latency now since it is hard to do
- * when we run from the RAM
- */
- movl $DRCTMCTL, %edi /* DRAM timing register */
- movb (%edi), %al
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
- andb $0xef, %al
-#endif
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
- orb $0x10, %al
-#endif
- movb %al, (%edi)
-#endif
-#endif
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x03, %al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
-
-
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x18, %al /* Enable refresh and NORMAL mode */
- movb %al, (%edi)
-
- jmp dram_done
-
-bad_ram:
- xorl %edx, %edx
- xorl %edi, %edi
- jmp bad_reint
-
-dram_done:
- /* Restore Boot Flags */
- movl %ebx, %ebp
- jmp mem_init_ret
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-.globl init_ecc
-init_ecc:
- /* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
- movl $0x1, %edi
-memtest0:
- movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
- jne out
- shrl $0x1, %ecx
- andl %ecx, %ecx
- jz set_ecc
- shll $0x1, %edi
- jmp memtest0
-
-set_ecc:
- /* clear all ram with a memset */
- movl %eax, %ecx
- xorl %esi, %esi
- xorl %edi, %edi
- xorl %eax, %eax
- shrl $0x2, %ecx
- cld
- rep stosl
-
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
-
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- movb $0x10, %al
- movb %al, (%edi)
-
- /* Turn on ECC */
- movl $ECCCTL, %edi
- movb $0x05, %al
- movb %al,(%edi)
-
-out:
- jmp init_ecc_ret
-#endif
-
-/*
- * Read and decode the sc520 DRCBENDADR MMCR and return the number of
- * available ram bytes in %eax
- */
-.globl get_mem_size
-get_mem_size:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
-
-bank0: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00000080, %ecx
- jz bank1
- andl $0x0000007f, %eax
- shll $22, %eax
- movl %eax, %edx
-
-bank1: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00008000, %ecx
- jz bank2
- andl $0x00007f00, %eax
- shll $14, %eax
- movl %eax, %edx
-
-bank2: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00800000, %ecx
- jz bank3
- andl $0x007f0000, %eax
- shll $6, %eax
- movl %eax, %edx
-
-bank3: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x80000000, %ecx
- jz done
- andl $0x7f000000, %eax
- shrl $2, %eax
- movl %eax, %edx
-
-done:
- movl %edx, %eax
- jmp get_mem_size_ret
diff --git a/arch/i386/cpu/sc520/sc520_car.S b/arch/i386/cpu/sc520/sc520_car.S
new file mode 100644
index 000000000..22f522531
--- /dev/null
+++ b/arch/i386/cpu/sc520/sc520_car.S
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+.section .text
+
+.globl car_init
+car_init:
+ /*
+ * How to enable Cache-As-RAM for the AMD Elan SC520:
+ * 1. Turn off the CPU Cache (may not be strictly required)
+ * 2. Set code execution PAR (usually the BOOTCS region) to be
+ * non-cachable
+ * 3. Create a Cachable PAR Region for an area of memory which is
+ * a) NOT where the code is being executed
+ * b) NOT SDRAM (Controller not initialised yet)
+ * c) WILL response to read requests
+ * The easiest way to do this is to create a second BOOTCS
+ * PAR mappnig with an address != the PAR in step 2
+ * 4. Issue a wbinvd to invalidate the CPU cache
+ * 5. Turn on the CPU Cache
+ * 6. Read 16kB from the cached PAR region setup in step 3
+ * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
+ *
+ * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
+ * are avoided as these are the only two PARs which can be used
+ * as PCI BUS Memory regions which the board might require)
+ *
+ * The configuration of PAR2 must be set in the board configuration
+ * file as CONFIG_SYS_SC520_CAR_PAR
+ */
+
+ /* Configure Cache-As-RAM PAR */
+ movl $CONFIG_SYS_SC520_CAR_PAR, %eax
+ movl $SC520_PAR2, %edi
+ movl %eax, (%edi)
+
+ /* Trash the cache then turn it on */
+ wbinvd
+ movl %cr0, %eax
+ andl $~(X86_CR0_NW | X86_CR0_CD), %eax
+ movl %eax, %cr0
+
+ /*
+ * The cache is now enabled and empty. Map a region of memory to
+ * it by reading that region.
+ */
+ movl $CONFIG_SYS_CAR_ADDR, %esi
+ movl $CONFIG_SYS_CAR_SIZE, %ecx
+ shrl $2, %ecx /* we are reading longs */
+ cld
+ rep lodsl
+
+ /* Turn off the cache, but don't trash it */
+ movl %cr0, %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
+ movl %eax, %cr0
+
+ /* Clear the CAR region */
+ xorl %eax, %eax
+ movl $CONFIG_SYS_CAR_ADDR, %edi
+ movl $CONFIG_SYS_CAR_SIZE, %ecx
+ shrl $2, %ecx /* we are writing longs */
+ rep stosl
+
+ /*
+ * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
+ * Cache-As-RAM
+ */
+ jmp car_init_ret
diff --git a/arch/i386/cpu/sc520/sc520_sdram.c b/arch/i386/cpu/sc520/sc520_sdram.c
new file mode 100644
index 000000000..d5ab55df0
--- /dev/null
+++ b/arch/i386/cpu/sc520/sc520_sdram.c
@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sc520_sdram_info {
+ u8 banks;
+ u8 columns;
+ u8 rows;
+ u8 size;
+};
+
+static void sc520_sizemem(void);
+static void sc520_set_dram_timing(void);
+static void sc520_set_dram_refresh_rate(void);
+static void sc520_enable_dram_refresh(void);
+static void sc520_enable_sdram(void);
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+#endif
+
+int dram_init_f(void)
+{
+ sc520_sizemem();
+ sc520_set_dram_timing();
+ sc520_set_dram_refresh_rate();
+ sc520_enable_dram_refresh();
+ sc520_enable_sdram();
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+ sc520_enable_ecc();
+#endif
+
+ return 0;
+}
+
+static inline void sc520_dummy_write(void)
+{
+ writew(0x0000, CACHELINESZ);
+}
+static inline void sc520_issue_sdram_op_mode_select(u8 command)
+{
+ writeb(command, &sc520_mmcr->drcctl);
+ sc520_dummy_write();
+}
+
+static inline int check_long(u32 test_long)
+{
+ u8 i;
+ u8 tmp_byte = (u8)(test_long & 0x000000ff);
+
+ for (i = 1; i < 4; i++) {
+ if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
+ return -1;
+ }
+
+ return 0;
+}
+
+static inline int write_and_test(u32 data, u32 address)
+{
+ writel(data, address);
+ if (readl(address) == data)
+ return 0; /* Good */
+ else
+ return -1; /* Bad */
+}
+
+static void sc520_enable_sdram(void)
+{
+ u32 par_config;
+
+ /* Enable Writes, Caching and Code Execution to SDRAM */
+ par_config = readl(&sc520_mmcr->par[3]);
+ par_config &= ~(SC520_PAR_EXEC_DIS |
+ SC520_PAR_CACHE_DIS |
+ SC520_PAR_WRITE_DIS);
+ writel(par_config, &sc520_mmcr->par[3]);
+
+ par_config = readl(&sc520_mmcr->par[4]);
+ par_config &= ~(SC520_PAR_EXEC_DIS |
+ SC520_PAR_CACHE_DIS |
+ SC520_PAR_WRITE_DIS);
+ writel(par_config, &sc520_mmcr->par[4]);
+}
+
+static void sc520_set_dram_timing(void)
+{
+ u8 drctmctl = 0x00;
+
+#if defined CONFIG_SYS_SDRAM_DRCTMCTL
+ /* just have your hardware designer _GIVE_ you what you need here! */
+ drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
+#else
+ switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
+ case 2:
+ break;
+ case 3:
+ drctmctl |= 0x01;
+ break;
+ case 4:
+ default:
+ drctmctl |= 0x02;
+ break;
+ }
+
+ switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
+ case 2:
+ break;
+ case 3:
+ drctmctl |= 0x04;
+ break;
+ case 4:
+ default:
+ drctmctl |= 0x08;
+ break;
+
+ case 6:
+ drctmctl |= 0x0c;
+ break;
+ }
+
+ switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
+ case 2:
+ break;
+ case 3:
+ default:
+ drctmctl |= 0x10;
+ break;
+ }
+#endif
+ writeb(drctmctl, &sc520_mmcr->drctmctl);
+
+ /* Issue load mode register command */
+ sc520_issue_sdram_op_mode_select(0x03);
+}
+
+static void sc520_set_dram_refresh_rate(void)
+{
+ u8 drctl;
+
+ drctl = readb(&sc520_mmcr->drcctl);
+ drctl &= 0xcf;
+
+ switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
+ case 78:
+ break;
+ case 156:
+ default:
+ drctl |= 0x10;
+ break;
+ case 312:
+ drctl |= 0x20;
+ break;
+ case 624:
+ drctl |= 0x30;
+ break;
+ }
+
+ writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_enable_dram_refresh(void)
+{
+ u8 drctl;
+
+ drctl = readb(&sc520_mmcr->drcctl);
+ drctl &= 0x30; /* keep refresh rate */
+ drctl |= 0x08; /* enable refresh, normal mode */
+
+ writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
+{
+ u32 col_data;
+ u32 row_data;
+
+ u32 drcbendadr;
+ u16 drccfg;
+
+ u8 banks = 0x00;
+ u8 columns = 0x00;
+ u8 rows = 0x00;
+
+ bank_info->banks = 0x00;
+ bank_info->columns = 0x00;
+ bank_info->rows = 0x00;
+ bank_info->size = 0x00;
+
+ if ((bank < 0) || (bank > 3)) {
+ printf("Bad Bank ID\n");
+ return;
+ }
+
+ /* Save configuration */
+ drcbendadr = readl(&sc520_mmcr->drcbendadr);
+ drccfg = readw(&sc520_mmcr->drccfg);
+
+ /* Setup SDRAM Bank to largest possible size */
+ writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
+
+ /* Set ending address for this bank */
+ writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
+
+ /* write col 11 wrap adr */
+ if (write_and_test(COL11_DATA, COL11_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 10 wrap adr */
+ if (write_and_test(COL10_DATA, COL10_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 9 wrap adr */
+ if (write_and_test(COL09_DATA, COL09_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 8 wrap adr */
+ if (write_and_test(COL08_DATA, COL08_ADR) != 0)
+ goto restore_and_exit;
+
+ col_data = readl(COL11_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(col_data) < 0)
+ goto restore_and_exit;
+
+ if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
+ columns = (u8)(col_data & 0x000000ff);
+ else
+ goto restore_and_exit;
+
+ /* write row 14 wrap adr */
+ if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 13 wrap adr */
+ if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 12 wrap adr */
+ if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 11 wrap adr */
+ if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
+ goto restore_and_exit;
+
+ if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
+ goto restore_and_exit;
+
+ /*
+ * read data @ row 12 wrap adr to determine number of banks,
+ * and read data @ row 14 wrap adr to determine number of rows.
+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+ */
+ row_data = readl(ROW12_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(row_data) != 0)
+ goto restore_and_exit;
+
+ switch (row_data) {
+ case ROW10_DATA:
+ banks = 2;
+ break;
+
+ case ROW11_DATA:
+ case ROW12_DATA:
+ banks = 4;
+ break;
+
+ default:
+ goto restore_and_exit;
+ }
+
+ row_data = readl(ROW14_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(row_data) != 0)
+ goto restore_and_exit;
+
+ switch (row_data) {
+ case ROW11_DATA:
+ case ROW12_DATA:
+ case ROW13_DATA:
+ case ROW14_DATA:
+ rows = (u8)(row_data & 0x000000ff);
+ break;
+
+ default:
+ goto restore_and_exit;
+ }
+
+ bank_info->banks = banks;
+ bank_info->columns = columns;
+ bank_info->rows = rows;
+
+ if ((bank_info->banks != 0) &&
+ (bank_info->columns != 0) &&
+ (bank_info->rows != 0)) {
+ bank_info->size = bank_info->rows;
+ bank_info->size >>= (11 - bank_info->columns);
+ bank_info->size++;
+ }
+
+restore_and_exit:
+ /* Restore configuration */
+ writel(drcbendadr, &sc520_mmcr->drcbendadr);
+ writew(drccfg, &sc520_mmcr->drccfg);
+}
+
+static void sc520_setup_sizemem(void)
+{
+ u8 i;
+
+ /* Disable write buffer */
+ writeb(0x00, &sc520_mmcr->dbctl);
+
+ /* Disable ECC */
+ writeb(0x00, &sc520_mmcr->eccctl);
+
+ /* Set slowest SDRAM timing */
+ writeb(0x1e, &sc520_mmcr->drctmctl);
+
+ /* Issue a NOP to all SDRAM banks */
+ sc520_issue_sdram_op_mode_select(0x01);
+
+ /* Delay for 100 microseconds */
+ udelay(100);
+
+ /* Issue 'All Banks Precharge' command */
+ sc520_issue_sdram_op_mode_select(0x02);
+
+ /* Issue 2 'Auto Refresh Enable' command */
+ sc520_issue_sdram_op_mode_select(0x04);
+ sc520_dummy_write();
+
+ /* Issue 'Load Mode Register' command */
+ sc520_issue_sdram_op_mode_select(0x03);
+
+ /* Issue 8 more 'Auto Refresh Enable' commands */
+ sc520_issue_sdram_op_mode_select(0x04);
+ for (i = 0; i < 7; i++)
+ sc520_dummy_write();
+
+ /* Set control register to 'Normal Mode' */
+ writeb(0x00, &sc520_mmcr->drcctl);
+}
+
+static void sc520_sizemem(void)
+{
+ struct sc520_sdram_info sdram_info[4];
+ u8 bank_config = 0x00;
+ u8 end_addr = 0x00;
+ u16 drccfg = 0x0000;
+ u32 drcbendadr = 0x00000000;
+ u8 i;
+
+ /* Use PARs to disable caching of maximum allowable 256MB SDRAM */
+ writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
+ writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
+
+ sc520_setup_sizemem();
+
+ gd->ram_size = 0;
+
+ /* Size each SDRAM bank */
+ for (i = 0; i <= 3; i++) {
+ sc520_get_bank_info(i, &sdram_info[i]);
+
+ if (sdram_info[i].banks != 0) {
+ /* Update Configuration register */
+ bank_config = sdram_info[i].columns - 8;
+
+ if (sdram_info[i].banks == 4)
+ bank_config |= 0x08;
+
+ drccfg |= bank_config << (i * 4);
+
+ /* Update End Address register */
+ end_addr += sdram_info[i].size;
+ drcbendadr |= (end_addr | 0x80) << (i * 8);
+
+ gd->ram_size += sdram_info[i].size << 22;
+ }
+
+ /* Issue 'All Banks Precharge' command */
+ sc520_issue_sdram_op_mode_select(0x02);
+
+ /* Set control register to 'Normal Mode' */
+ writeb(0x00, &sc520_mmcr->drcctl);
+ }
+
+ writel(drcbendadr, &sc520_mmcr->drcbendadr);
+ writew(drccfg, &sc520_mmcr->drccfg);
+
+ /* Clear PARs preventing caching of SDRAM */
+ writel(0x00000000, &sc520_mmcr->par[3]);
+ writel(0x00000000, &sc520_mmcr->par[4]);
+}
+
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+
+ /* A nominal memory test: just a byte at each address line */
+ movl %eax, %ecx
+ shrl $0x1, %ecx
+ movl $0x1, %edi
+memtest0:
+ movb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
+ jne out
+ shrl $0x1, %ecx
+ andl %ecx, %ecx
+ jz set_ecc
+ shll $0x1, %edi
+ jmp memtest0
+
+set_ecc:
+ /* clear all ram with a memset */
+ movl %eax, %ecx
+ xorl %esi, %esi
+ xorl %edi, %edi
+ xorl %eax, %eax
+ shrl $0x2, %ecx
+ cld
+ rep stosl
+
+ /* enable read, write buffers */
+ movb $0x11, %al
+ movl $DBCTL, %edi
+ movb %al, (%edi)
+
+ /* enable NMI mapping for ECC */
+ movl $ECCINT, %edi
+ movb $0x10, %al
+ movb %al, (%edi)
+
+ /* Turn on ECC */
+ movl $ECCCTL, %edi
+ movb $0x05, %al
+ movb %al,(%edi)
+
+out:
+ jmp init_ecc_ret
+}
+#endif
+
+int dram_init(void)
+{
+ ulong dram_ctrl;
+ ulong dram_present = 0x00000000;
+
+ /*
+ * We read-back the configuration of the dram
+ * controller that the assembly code wrote
+ */
+ dram_ctrl = readl(&sc520_mmcr->drcbendadr);
+
+ gd->bd->bi_dram[0].start = 0;
+ if (dram_ctrl & 0x80) {
+ /* bank 0 enabled */
+ gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
+ dram_present = gd->bd->bi_dram[1].start;
+ gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[0].size = 0;
+ gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
+ }
+
+ if (dram_ctrl & 0x8000) {
+ /* bank 1 enabled */
+ gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
+ dram_present = gd->bd->bi_dram[2].start;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
+ gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[1].size = 0;
+ gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
+ }
+
+ if (dram_ctrl & 0x800000) {
+ /* bank 2 enabled */
+ gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
+ dram_present = gd->bd->bi_dram[3].start;
+ gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
+ gd->bd->bi_dram[2].start;
+ } else {
+ gd->bd->bi_dram[2].size = 0;
+ gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
+ }
+
+ if (dram_ctrl & 0x80000000) {
+ /* bank 3 enabled */
+ dram_present = (dram_ctrl & 0x7f000000) >> 2;
+ gd->bd->bi_dram[3].size = dram_present -
+ gd->bd->bi_dram[3].start;
+ } else {
+ gd->bd->bi_dram[3].size = 0;
+ }
+
+ gd->ram_size = dram_present;
+
+ return 0;
+}
diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S
index 829468fe7..00313897c 100644
--- a/arch/i386/cpu/start.S
+++ b/arch/i386/cpu/start.S
@@ -1,7 +1,7 @@
/*
* U-boot - i386 Startup Code
*
- * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m <denaiel@omicron.se>
+ * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -26,6 +26,7 @@
#include <config.h>
#include <version.h>
#include <asm/global_data.h>
+#include <asm/processor-flags.h>
.section .text
@@ -46,7 +47,7 @@ _i386boot_start:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000, %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
@@ -66,78 +67,68 @@ _start:
/* Clear the interupt vectors */
lidt blank_idt_ptr
- /* Skip low-level initialization if not starting from cold-reset */
- movl %ebx, %ecx
- andl $GD_FLG_COLD_BOOT, %ecx
- jz skip_mem_init
-
/* Early platform init (setup gpio, etc ) */
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
- /* size memory */
- jmp mem_init
-.globl mem_init_ret
-mem_init_ret:
-
-skip_mem_init:
- /* fetch memory size (into %eax) */
- jmp get_mem_size
-.globl get_mem_size_ret
-get_mem_size_ret:
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
- /* Skip ECC initialization if not starting from cold-reset */
- movl %ebx, %ecx
- andl $GD_FLG_COLD_BOOT, %ecx
- jz init_ecc_ret
- jmp init_ecc
-
-.globl init_ecc_ret
-init_ecc_ret:
-#endif
-
- /* Check we have enough memory for stack */
- movl $CONFIG_SYS_STACK_SIZE, %ecx
- cmpl %ecx, %eax
- jb die
-mem_ok:
- /* Set stack pointer to upper memory limit*/
- movl %eax, %esp
+ /* Initialise Cache-As-RAM */
+ jmp car_init
+.globl car_init_ret
+car_init_ret:
+ /*
+ * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
+ * or fully initialised SDRAM - we really don't care which)
+ * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
+ */
+ movl $CONFIG_SYS_INIT_SP_ADDR, %esp
+ movl $CONFIG_SYS_INIT_GD_ADDR, %ebp
- /* Test the stack */
- pushl $0
- popl %ecx
- cmpl $0, %ecx
- jne die
- push $0x55aa55aa
- popl %ecx
- cmpl $0x55aa55aa, %ecx
- jne die
+ /* Set Boot Flags in Global Data */
+ movl %ebx, (GD_FLAGS * 4)(%ebp)
- wbinvd
-
- /* Determine our load offset */
+ /* Determine our load offset (and put in Global Data) */
call 1f
1: popl %ecx
subl $1b, %ecx
+ movl %ecx, (GD_LOAD_OFF * 4)(%ebp)
- /* Set the upper memory limit parameter */
- subl $CONFIG_SYS_STACK_SIZE, %eax
-
- /* Reserve space for global data */
- subl $(GD_SIZE * 4), %eax
-
- /* %eax points to the global data structure */
- movl %esp, (GD_RAM_SIZE * 4)(%eax)
- movl %ebx, (GD_FLAGS * 4)(%eax)
- movl %ecx, (GD_LOAD_OFF * 4)(%eax)
+ /* Set parameter to board_init_f() to boot flags */
+ movl (GD_FLAGS * 4)(%ebp), %eax
call board_init_f /* Enter, U-boot! */
/* indicate (lack of) progress */
movw $0x85, %ax
+ jmp die
+
+.globl relocate_code
+.type relocate_code, @function
+relocate_code:
+ /*
+ * SDRAM has been initialised, U-Boot code has been copied into
+ * RAM, BSS has been cleared and relocation adjustments have been
+ * made. It is now time to jump into the in-RAM copy of U-Boot
+ *
+ * %eax = Address of top of stack
+ * %edx = Address of Global Data
+ * %ecx = Base address of in-RAM copy of U-Boot
+ */
+
+ /* Setup stack in RAM */
+ movl %eax, %esp
+
+ /* Setup call address of in-RAM copy of board_init_r() */
+ movl $board_init_r, %ebp
+ addl (GD_RELOC_OFF * 4)(%edx), %ebp
+
+ /* Setup parameters to board_init_r() */
+ movl %edx, %eax
+ movl %ecx, %edx
+
+ /* Jump to in-RAM copy of board_init_r() */
+ call *%ebp
+
die: hlt
jmp die
hlt
diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S
index 0a5823d3c..7dc535836 100644
--- a/arch/i386/cpu/start16.S
+++ b/arch/i386/cpu/start16.S
@@ -23,6 +23,7 @@
*/
#include <asm/global_data.h>
+#include <asm/processor-flags.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
#define a32 .byte 0x67;
@@ -45,7 +46,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000, %eax
+ orl $(X86_CR0_NW & X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
@@ -55,7 +56,7 @@ o32 cs lgdt gdt_ptr
/* Now, we enter protected mode */
movl %cr0, %eax
- orl $1, %eax
+ orl $X86_CR0_PE, %eax
movl %eax, %cr0
/* Flush the prefetch queue */
diff --git a/board/eNET/u-boot.lds b/arch/i386/cpu/u-boot.lds
index 3eeb2a201..98a548d62 100644
--- a/board/eNET/u-boot.lds
+++ b/arch/i386/cpu/u-boot.lds
@@ -73,7 +73,7 @@ SECTIONS
/DISCARD/ : { *(.gnu*) }
/* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
+ .realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
__realmode_start = LOADADDR(.realmode);
__realmode_size = SIZEOF(.realmode);
@@ -84,21 +84,13 @@ SECTIONS
__bios_start = LOADADDR(.bios);
__bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash
- * will be mapped so that 0x387f0000 == 0xffff0000
- * at reset time
- *
- * The fe00 and ff00 offsets of the start32 and start16
- * segments are arbitrary, the just have to be mapped
- * at reset and the code have to fit.
- * The fff0 offset of resetvec is important, however.
+ /*
+ * The following expressions place the 16-bit Real-Mode code and
+ * Reset Vector at the end of the Flash ROM
*/
- . = 0xfffffe00;
- .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
+ . = START_16;
+ .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
- . = 0xf800;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
-
- . = 0xfff0;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC;
+ .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
}
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h
index e3f8a25ef..f8a16d646 100644
--- a/arch/i386/include/asm/global_data.h
+++ b/arch/i386/include/asm/global_data.h
@@ -35,7 +35,7 @@
#ifndef __ASSEMBLY__
-typedef struct {
+typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
@@ -46,6 +46,8 @@ typedef struct {
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
+ unsigned long relocaddr; /* Start address of U-Boot in RAM */
+ unsigned long start_addr_sp; /* start_addr_stackpointer */
phys_size_t ram_size; /* RAM size */
unsigned long reset_status; /* reset status register at boot */
void **jt; /* jump table */
@@ -67,11 +69,13 @@ extern gd_t *gd;
#define GD_ENV_VALID 7
#define GD_CPU_CLK 8
#define GD_BUS_CLK 9
-#define GD_RAM_SIZE 10
-#define GD_RESET_STATUS 11
-#define GD_JT 12
+#define GD_RELOC_ADDR 10
+#define GD_START_ADDR_SP 11
+#define GD_RAM_SIZE 12
+#define GD_RESET_STATUS 13
+#define GD_JT 14
-#define GD_SIZE 13
+#define GD_SIZE 15
/*
* Global Data Flags
@@ -87,7 +91,12 @@ extern gd_t *gd;
#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
-
+#if 0
#define DECLARE_GLOBAL_DATA_PTR
+#else
+#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
+#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
+gd_t *gd
+#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h
index 053d9c677..956c1c263 100644
--- a/arch/i386/include/asm/ic/sc520.h
+++ b/arch/i386/include/asm/ic/sc520.h
@@ -252,16 +252,68 @@ typedef struct sc520_mmcr {
u8 pad_0xdc0[0x0240];
} sc520_mmcr_t;
-extern volatile sc520_mmcr_t *sc520_mmcr;
+extern sc520_mmcr_t *sc520_mmcr;
#endif
-/* MMCR Offsets (required for assembler code */
-#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
-#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
-#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
-#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
+/* Memory Mapped Control Registers (MMCR) Base Address */
+#define SC520_MMCR_BASE 0xfffef000
+
+/* MMCR Addresses (required for assembler code) */
+#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
+#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
+#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
+#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
+#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
+#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
+#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
+
+#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
+#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
+#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
+#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
+#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
+#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
+#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
+#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
+#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
+#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
+#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
+#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
+#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
+#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
+#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
+#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
+
+/*
+ * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
+ * Two PARs are required due to maximum PAR size of 128MB
+ * These are used in the SDRAM sizing code to disable caching
+ *
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x00000000
+ * | | | | | | 0x08000000
+ * | | | | | +----------------------- 128MB Region Size
+ * | | | | | ((2047 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM1_PAR 0xe3ffc000
+#define SC520_SDRAM2_PAR 0xe3ffc800
+
+#define SC520_PAR_WRITE_DIS 0x04000000
+#define SC520_PAR_CACHE_DIS 0x08000000
+#define SC520_PAR_EXEC_DIS 0x10000000
+
+/*
+ * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
+ * required for DRAM sizing code
+ */
/* MMCR Register bits (not all of them :) ) */
@@ -293,6 +345,33 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
#define UART2_DIS 0x02 /* UART2 Disable */
#define UART1_DIS 0x01 /* UART1 Disable */
+/*
+ * Defines used for SDRAM Sizing (number of columns and rows)
+ * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
+ * Elan SC520 Microcontroller User's Manual (Order #22004B)
+ */
+#define CACHELINESZ 0x00000010
+
+#define COL11_ADR 0x0e001e00
+#define COL10_ADR 0x0e000e00
+#define COL09_ADR 0x0e000600
+#define COL08_ADR 0x0e000200
+#define COL11_DATA 0x0b0b0b0b
+#define COL10_DATA 0x0a0a0a0a
+#define COL09_DATA 0x09090909
+#define COL08_DATA 0x08080808
+
+#define ROW14_ADR 0x0f000000
+#define ROW13_ADR 0x07000000
+#define ROW12_ADR 0x03000000
+#define ROW11_ADR 0x01000000
+#define ROW10_ADR 0x00000000
+#define ROW14_DATA 0x3f3f3f3f
+#define ROW13_DATA 0x1f1f1f1f
+#define ROW12_DATA 0x0f0f0f0f
+#define ROW11_DATA 0x07070707
+#define ROW10_DATA 0xaaaaaaaa
+
/* 0x28000000 - 0x3fffffff is used by the flash banks */
/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
diff --git a/arch/i386/include/asm/processor-flags.h b/arch/i386/include/asm/processor-flags.h
new file mode 100644
index 000000000..7a3e836eb
--- /dev/null
+++ b/arch/i386/include/asm/processor-flags.h
@@ -0,0 +1,100 @@
+#ifndef _ASM_X86_PROCESSOR_FLAGS_H
+#define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
+
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE 0x00000001 /* Protection Enable */
+#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM 0x00000004 /* Emulation */
+#define X86_CR0_TS 0x00000008 /* Task Switched */
+#define X86_CR0_ET 0x00000010 /* Extension Type */
+#define X86_CR0_NE 0x00000020 /* Numeric Error */
+#define X86_CR0_WP 0x00010000 /* Write Protect */
+#define X86_CR0_AM 0x00040000 /* Alignment Mask */
+#define X86_CR0_NW 0x20000000 /* Not Write-through */
+#define X86_CR0_CD 0x40000000 /* Cache Disable */
+#define X86_CR0_PG 0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT 0x00000008 /* Page Write Through */
+#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE 0x00000040 /* Machine check enable */
+#define X86_CR4_PGE 0x00000080 /* enable global pages */
+#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR 0x0000000F /* task priority register */
+
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+
+/*
+ * NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0 0x20
+#define CX86_GCR 0xb8
+#define CX86_CCR0 0xc0
+#define CX86_CCR1 0xc1
+#define CX86_CCR2 0xc2
+#define CX86_CCR3 0xc3
+#define CX86_CCR4 0xe8
+#define CX86_CCR5 0xe9
+#define CX86_CCR6 0xea
+#define CX86_CCR7 0xeb
+#define CX86_PCR1 0xf0
+#define CX86_DIR0 0xfe
+#define CX86_DIR1 0xff
+#define CX86_ARR_BASE 0xc4
+#define CX86_RCR_BASE 0xdc
+
+#ifdef __KERNEL__
+#ifdef CONFIG_VM86
+#define X86_VM_MASK X86_EFLAGS_VM
+#else
+#define X86_VM_MASK 0 /* No VM86 support */
+#endif
+#endif
+
+#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
diff --git a/arch/i386/include/asm/processor.h b/arch/i386/include/asm/processor.h
index 5dedba82c..22a129813 100644
--- a/arch/i386/include/asm/processor.h
+++ b/arch/i386/include/asm/processor.h
@@ -23,7 +23,10 @@
#ifndef __ASM_PROCESSOR_H_
#define __ASM_PROCESSOR_H_ 1
-/* Currently this header is unused in the i386 port
- * but some generic files #include <asm/processor.h>
- * so this file is a placeholder. */
+
+#define GDT_ENTRY_32BIT_CS 2
+#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1)
+#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1)
+#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1)
+
#endif
diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h
index ce097a3bf..7b39bd2ae 100644
--- a/arch/i386/include/asm/u-boot-i386.h
+++ b/arch/i386/include/asm/u-boot-i386.h
@@ -25,7 +25,9 @@
#define _U_BOOT_I386_H_ 1
/* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
int cpu_init_r(void);
+int x86_cpu_init_f(void);
int cpu_init_f(void);
/* cpu/.../timer.c */
@@ -35,6 +37,7 @@ int register_timer_isr (timer_fnc_t *isr_func);
/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */
int timer_init(void);
+int dram_init_f(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c
index 30cb9a207..e0f9803e5 100644
--- a/arch/i386/lib/board.c
+++ b/arch/i386/lib/board.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -45,7 +45,15 @@
#include <miiphy.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+#undef XTRN_DECLARE_GLOBAL_DATA_PTR
+#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
+DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+
/* Exports from the Linker Script */
extern ulong __text_start;
@@ -148,15 +156,33 @@ static void display_flash_config (ulong size)
*/
typedef int (init_fnc_t) (void);
-init_fnc_t *init_sequence[] = {
+static int calculate_relocation_address(void);
+static int copy_uboot_to_ram(void);
+static int clear_bss(void);
+static int do_elf_reloc_fixups(void);
+
+init_fnc_t *init_sequence_f[] = {
+ cpu_init_f,
+ board_early_init_f,
+ env_init,
+ init_baudrate,
+ serial_init,
+ console_init_f,
+ dram_init_f,
+ calculate_relocation_address,
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+
+ NULL,
+};
+
+init_fnc_t *init_sequence_r[] = {
cpu_init_r, /* basic cpu dependent setup */
board_early_init_r, /* basic board dependent setup */
dram_init, /* configure available RAM banks */
interrupt_init, /* set up exceptions */
timer_init,
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
display_banner,
display_dram_config,
@@ -165,88 +191,101 @@ init_fnc_t *init_sequence[] = {
gd_t *gd;
-/*
- * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
- */
-void board_init_f (ulong gdp)
+static int calculate_relocation_address(void)
{
void *text_start = &__text_start;
- void *data_end = &__data_end;
- void *rel_dyn_start = &__rel_dyn_start;
- void *rel_dyn_end = &__rel_dyn_end;
- void *bss_start = &__bss_start;
void *bss_end = &__bss_end;
-
- ulong *dst_addr;
- ulong *src_addr;
- ulong *end_addr;
-
void *dest_addr;
ulong rel_offset;
- Elf32_Rel *re_src;
- Elf32_Rel *re_end;
/* Calculate destination RAM Address and relocation offset */
- dest_addr = (void *)gdp - (bss_end - text_start);
- rel_offset = text_start - dest_addr;
+ dest_addr = (void *)gd->ram_size;
+ dest_addr -= CONFIG_SYS_STACK_SIZE;
+ dest_addr -= (bss_end - text_start);
+ rel_offset = dest_addr - text_start;
- /* Perform low-level initialization only when cold booted */
- if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) {
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
+ gd->start_addr_sp = gd->ram_size;
+ gd->relocaddr = (ulong)dest_addr;
+ gd->reloc_off = rel_offset;
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
- }
+ return 0;
+}
- /* Copy U-Boot into RAM */
- dst_addr = (ulong *)dest_addr;
- src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off);
- end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off);
+static int copy_uboot_to_ram(void)
+{
+ ulong *dst_addr = (ulong *)gd->relocaddr;
+ ulong *src_addr = (ulong *)&__text_start;
+ ulong *end_addr = (ulong *)&__data_end;
while (src_addr < end_addr)
*dst_addr++ = *src_addr++;
- /* Clear BSS */
- dst_addr = (ulong *)(bss_start - rel_offset);
- end_addr = (ulong *)(bss_end - rel_offset);
+ return 0;
+}
+
+static int clear_bss(void)
+{
+ void *bss_start = &__bss_start;
+ void *bss_end = &__bss_end;
+
+ ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
+ ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
while (dst_addr < end_addr)
*dst_addr++ = 0x00000000;
- /* Perform relocation adjustments */
- re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off);
- re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off);
+ return 0;
+}
+
+static int do_elf_reloc_fixups(void)
+{
+ Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
+ Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
do {
if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
- if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= CONFIG_SYS_TEXT_BASE)
- *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset;
+ if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE)
+ *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off;
} while (re_src++ < re_end);
- ((gd_t *)gdp)->reloc_off = rel_offset;
- ((gd_t *)gdp)->flags |= GD_FLG_RELOC;
+ return 0;
+}
+
+/*
+ * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
+ */
+void board_init_f(ulong boot_flags)
+{
+ init_fnc_t **init_fnc_ptr;
+
+ for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
+
+ gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */
- (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr);
+ relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
- /* NOTREACHED - board_init_f() does not return */
+ /* NOTREACHED - relocate_code() does not return */
while(1);
}
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
- int i;
ulong size;
static bd_t bd_data;
+ static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
show_boot_progress(0x21);
- gd = id;
+ /* Global data pointer is now writable */
+ gd = &gd_data;
+ memcpy(gd, id, sizeof(gd_t));
+
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
@@ -259,12 +298,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
CONFIG_SYS_MALLOC_LEN);
- for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) {
- show_boot_progress(0xa130|i);
-
- if ((*init_fnc_ptr)() != 0) {
+ for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
hang ();
- }
}
show_boot_progress(0x23);
diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c
index 60fe1816a..2dda95b06 100644
--- a/arch/i386/lib/realmode.c
+++ b/arch/i386/lib/realmode.c
@@ -27,7 +27,6 @@
#include <asm/realmode.h>
-#define REALMODE_BASE ((char*)0x7c0)
#define REALMODE_MAILBOX ((char*)0xe00)
@@ -41,13 +40,14 @@ int realmode_setup(void)
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
- if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
+ if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
- realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+ realmode_size,
+ (REALMODE_MAILBOX - (char *)REALMODE_BASE));
return -1;
}
- memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size);
+ memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
asm("wbinvd\n");
return 0;
diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S
index 47bba36f2..8c76a73e9 100644
--- a/arch/microblaze/cpu/irq.S
+++ b/arch/microblaze/cpu/irq.S
@@ -60,7 +60,6 @@ _interrupt_handler:
addik r1, r1, -124
brlid r15, interrupt_handler
nop
- nop
addik r1, r1, 124
lwi r31, r1, -120
lwi r30, r1, -116
@@ -93,22 +92,6 @@ _interrupt_handler:
lwi r3, r1, -8
lwi r2, r1, -4
- /* enable_interrupt */
-#ifdef XILINX_USE_MSR_INSTR
- msrset r0, 2
-#else
- /* FIXME unstable in stressed mode - two irqs */
- nop
- addi r1, r1, -4
- swi r12, r1, 0
- mfs r12, rmsr
- ori r12, r12, 2
- mts rmsr, r12
- lwi r12, r1, 0
- addi r1, r1, 4
- nop
-#endif
- bra r14
- nop
+ rtid r14, 0
nop
.size _interrupt_handler,.-_interrupt_handler
diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
index deb23e094..c89e90438 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -62,7 +62,7 @@
#define NOP __asm__ __volatile__ ("nop");
/* use machine status registe USE_MSR_REG */
-#ifdef XILINX_USE_MSR_INSTR
+#if XILINX_USE_MSR_INSTR == 1
#define MSRSET(val) \
__asm__ __volatile__ ("msrset r0," #val );
diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h
index cff1dd9a1..4b21c8f7f 100644
--- a/arch/nios2/include/asm/gpio.h
+++ b/arch/nios2/include/asm/gpio.h
@@ -26,6 +26,11 @@ static inline int gpio_request(unsigned gpio, const char *label)
return 0;
}
+static inline int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
static inline int gpio_direction_input(unsigned gpio)
{
writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2));
@@ -47,12 +52,19 @@ static inline void gpio_set_value(unsigned gpio, int value)
{
writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
}
+
+static inline int gpio_is_valid(int number)
+{
+ return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
+}
#else
extern int gpio_request(unsigned gpio, const char *label);
+extern int gpio_free(unsigned gpio);
extern int gpio_direction_input(unsigned gpio);
extern int gpio_direction_output(unsigned gpio, int value);
extern int gpio_get_value(unsigned gpio);
extern void gpio_set_value(unsigned gpio, int value);
+extern int gpio_is_valid(int number);
#endif /* CONFIG_SYS_GPIO_BASE */
#endif /* _ASM_NIOS2_GPIO_H_ */
diff --git a/arch/nios2/include/asm/posix_types.h b/arch/nios2/include/asm/posix_types.h
index c2deea6bf..673364099 100644
--- a/arch/nios2/include/asm/posix_types.h
+++ b/arch/nios2/include/asm/posix_types.h
@@ -17,7 +17,7 @@ typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned long __kernel_size_t;
-typedef int __kernel_ssize_t;
+typedef long __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d34..52d446175 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -48,11 +48,26 @@ static struct {
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+ u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+ {
+ /* pcie controller 1 */
+ .index = 0,
+ },
+ {
+ /* pcie controller 2 */
+ .index = 1,
+ },
+};
+
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- pex83xx_t *pex = &immr->pciexp[bus];
+ struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+ pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
@@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
+ hose->priv_data = &pcie_priv[bus];
+
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 93e9f1c3f..5e616dda7 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -161,7 +161,7 @@ int get_clocks(void)
#endif
}
- spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
+ spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
sccr = im->clk.sccr;
@@ -392,7 +392,7 @@ int get_clocks(void)
#endif
lbiu_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+ (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
@@ -406,11 +406,12 @@ int get_clocks(void)
}
mem_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
- corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
+ (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
+ corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
+
#if defined(CONFIG_MPC8360)
mem_sec_clk = csb_clk * (1 +
- ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+ ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
@@ -442,8 +443,8 @@ int get_clocks(void)
}
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
- qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
- qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
+ qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
+ qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
brg_clk = qe_clk / 2;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b7f51e740..cbb0fc6bb 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -89,7 +89,7 @@ COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
COBJS-$(CONFIG_P1011) += p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
-COBJS-$(CONFIG_P1013) += p1013_serdes.o
+COBJS-$(CONFIG_P1013) += p1022_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 0cc8b1e13..e94975a1c 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -59,6 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
puts("Work-around for Erratum ESDHC136 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
+ puts("Work-around for Erratum ESDHC-A001 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
puts("Work-around for Erratum CPC-A002 enabled\n");
#endif
@@ -71,7 +74,13 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
puts("Work-around for Erratum DDR-A003 enabled\n");
#endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+ puts("Work-around for Erratum DDR115 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ puts("Work-around for Erratum DDR111 enabled\n");
+ puts("Work-around for Erratum DDR134 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index fa7e09f39..73b320b60 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -21,6 +21,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int i;
volatile ccsr_ddr_t *ddr;
u32 temp_sdram_cfg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+ u32 total_gb_size_per_controller;
+#endif
switch (ctrl_num) {
case 0:
@@ -178,13 +182,33 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
* when operatiing in 32-bit bus mode with 4-beat bursts,
* This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
-#ifdef CONFIG_MPC8572
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
setbits_be32(&ddr->debug[0], 1);
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ /*
+ * This is the combined workaround for DDR111 and DDR134
+ * following the published errata for MPC8572
+ */
+
+ /* 1. Set EEBACR[3] */
+ setbits_be32(&ecm->eebacr, 0x10000000);
+ debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+
+ /* 2. Set DINIT in SDRAM_CFG_2*/
+ setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
+ debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
+ in_be32(&ddr->sdram_cfg_2));
+
+ /* 3. Set DEBUG_3[21] */
+ setbits_be32(&ddr->debug[2], 0x400);
+ debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+#endif /* part 1 of the workaound */
/*
* 500 painful micro-seconds must elapse between
@@ -199,11 +223,90 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
- while (!(in_be32(&ddr->debug[1]) & 0x2))
- ;
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
- while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+ while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
udelay(10000); /* throttle polling rate */
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ /* continue this workaround */
+
+ /* 4. Clear DEBUG3[21] */
+ clrbits_be32(&ddr->debug[2], 0x400);
+ debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+ /* DDR134 workaround starts */
+ /* A: Clear sdram_cfg_2[odt_cfg] */
+ clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
+ debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
+ in_be32(&ddr->sdram_cfg_2));
+
+ /* B: Set DEBUG1[15] */
+ setbits_be32(&ddr->debug[0], 0x10000);
+ debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+ /* C: Set timing_cfg_2[cpo] to 0b11111 */
+ setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
+ debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
+ in_be32(&ddr->timing_cfg_2));
+
+ /* D: Set D6 to 0x9f9f9f9f */
+ out_be32(&ddr->debug[5], 0x9f9f9f9f);
+ debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
+
+ /* E: Set D7 to 0x9f9f9f9f */
+ out_be32(&ddr->debug[6], 0x9f9f9f9f);
+ debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
+
+ /* F: Set D2[20] */
+ setbits_be32(&ddr->debug[1], 0x800);
+ debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+ /* G: Poll on D2[20] until cleared */
+ while (in_be32(&ddr->debug[1]) & 0x800)
+ udelay(10000); /* throttle polling rate */
+
+ /* H: Clear D1[15] */
+ clrbits_be32(&ddr->debug[0], 0x10000);
+ debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+ /* I: Set sdram_cfg_2[odt_cfg] */
+ setbits_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
+ debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+ /* Continuing with the DDR111 workaround */
+ /* 5. Set D2[21] */
+ setbits_be32(&ddr->debug[1], 0x400);
+ debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+ /* 6. Poll D2[21] until its cleared */
+ while (in_be32(&ddr->debug[1]) & 0x400)
+ udelay(10000); /* throttle polling rate */
+
+ /* 7. Wait for 400ms/GB */
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ total_gb_size_per_controller +=
+ ((regs->cs[i].bnds & 0xFFFF) >> 6)
+ - (regs->cs[i].bnds >> 22) + 1;
}
+ if (in_be32(&ddr->sdram_cfg) & 0x80000)
+ total_gb_size_per_controller <<= 1;
+ debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
+ udelay(total_gb_size_per_controller * 400000);
+
+ /* 8. Set sdram_cfg_2[dinit] if options requires */
+ setbits_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
+ debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+ /* 9. Poll until dinit is cleared */
+ while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+ udelay(10000);
+
+ /* 10. Clear EEBACR[3] */
+ clrbits_be32(&ecm->eebacr, 10000000);
+ debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index c3e1d7664..936c1951f 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -236,9 +236,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ unsigned int data_rate = fsl_ddr_get_mem_data_rate();
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
+ if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
+ twrt_mclk = 1;
if (popts->dynamic_power == 0) { /* powerdown is not used */
act_pd_exit_mclk = 1;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 35b60a041..c7c12c1c2 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -80,5 +80,5 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
extern unsigned int mclk_to_picos(unsigned int mclk);
extern unsigned int get_memory_clk_period_ps(void);
extern unsigned int picos_to_mclk(unsigned int picos);
-
+extern unsigned int fsl_ddr_get_mem_data_rate(void);
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 36464aa7c..3a29d1cd2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -77,6 +77,8 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_DDR_115
+#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
#elif defined(CONFIG_P1010)
#define CONFIG_MAX_CPUS 1
@@ -130,11 +132,15 @@
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS 4
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 852e5c3bd..02a1f5d32 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -89,6 +89,11 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_BI 0x00000001
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
+
+#define TIMING_CFG_2_CPO_MASK 0x0F800000
+
#if defined(CONFIG_P4080)
#define RD_TO_PRE_MASK 0xf
#define RD_TO_PRE_SHIFT 13
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2e218de0b..a33ca2f7b 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -172,6 +172,9 @@ typedef struct global_data {
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+ unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 4ef85e3e5..433cc1538 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -31,4 +31,10 @@ endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDFLAGS_u-boot = --gc-sections
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+endif
+
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index fdcebd608..9b29d3ae7 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -44,6 +44,8 @@
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
+#elif defined (CONFIG_CPU_SH7757)
+# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h
new file mode 100644
index 000000000..17a6537bc
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7757.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CPU_SH7757_H_
+#define _ASM_CPU_SH7757_H_
+
+#define CCR 0xFF00001C
+#define WTCNT 0xFFCC0000
+#define CCR_CACHE_INIT 0x0000090b
+#define CACHE_OC_NUM_WAYS 1
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+ unsigned int reserved[4];
+ unsigned int mmucr;
+};
+#define MMU_BASE ((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0 0xffcc0002
+#define WRSTCSR_R 0xffcc0003
+#define WRSTCSR_W 0xffcc0002
+#define WTCSR_PREFIX 0xa500
+#define WRSTCSR_PREFIX 0x6900
+#define WRSTCSR_WOVF_PREFIX 0x9600
+
+/* SCIF */
+#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
+#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
+#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
+
+/* SerMux */
+#define SMR0 0xfe470000
+
+/* TMU0 */
+#define TSTR 0xFE430004
+#define TOCR 0xFE430000
+#define TSTR0 0xFE430004
+#define TCOR0 0xFE430008
+#define TCNT0 0xFE43000C
+#define TCR0 0xFE430010
+#define TCOR1 0xFE430014
+#define TCNT1 0xFE430018
+#define TCR1 0xFE43001C
+#define TCOR2 0xFE430020
+#define TCNT2 0xFE430024
+#define TCR2 0xFE430028
+#define TCPR2 0xFE43002C
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+ unsigned int reserved[114];
+ unsigned int mahr;
+ unsigned int reserved2;
+ unsigned int malr;
+};
+#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+ unsigned int gbecont;
+};
+#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1 0x00020000
+#define GBECONT_RMII0 0x00010000
+
+/* USB0/1 */
+struct usb_common_regs {
+ unsigned short reserved[129];
+ unsigned short suspmode;
+};
+#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+ unsigned short reset;
+ unsigned short reserved[4];
+ unsigned short portsel;
+};
+#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+ unsigned int port1sel;
+ unsigned int reserved;
+ unsigned int usb1intsts;
+};
+#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+ unsigned int ehcidatac; /* 0xfe4fe018 */
+ unsigned int reserved[63];
+ unsigned int ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GCTRL, GRA */
+struct gctrl_regs {
+ unsigned int wprotect;
+ unsigned int gplldiv;
+ unsigned int gracr2; /* GRA */
+ unsigned int gracr3; /* GRA */
+ unsigned int reserved[4];
+ unsigned int fcntcr1;
+ unsigned int fcntcr2;
+ unsigned int reserved2[2];
+ unsigned int gpll1div;
+ unsigned int vcompsel;
+ unsigned int reserved3[62];
+ unsigned int fdlmon;
+ unsigned int reserved4[2];
+ unsigned int flcrmon;
+ unsigned int reserved5[944];
+ unsigned int spibootcan;
+};
+#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
+
+/* PCIe setup */
+struct pcie_setup_regs {
+ unsigned int pbictl0;
+ unsigned int gradevctl;
+ unsigned int reserved[2];
+ unsigned int bmcinf[6];
+ unsigned int reserved2[118];
+ unsigned int idset[2];
+ unsigned int subidset;
+ unsigned int reserved3[2];
+ unsigned int linkconfset[4];
+ unsigned int trsid;
+ unsigned int reserved4[6];
+ unsigned int toutset;
+ unsigned int reserved5[7];
+ unsigned int lad0;
+ unsigned int ladmsk0;
+ unsigned int lad1;
+ unsigned int ladmsk1;
+ unsigned int lad2;
+ unsigned int ladmsk2;
+ unsigned int lad3;
+ unsigned int ladmsk3;
+ unsigned int lad4;
+ unsigned int ladmsk4;
+ unsigned int lad5;
+ unsigned int ladmsk5;
+ unsigned int reserved6[94];
+ unsigned int vdmrxvid[2];
+ unsigned int reserved7;
+ unsigned int pbiintfr;
+ unsigned int pbiinten;
+ unsigned int msimap;
+ unsigned int barmap;
+ unsigned int baracsize;
+ unsigned int advserest;
+ unsigned int pbictl3;
+ unsigned int reserved8[8];
+ unsigned int pbictl1;
+ unsigned int scratch0;
+ unsigned int reserved9[6];
+ unsigned int pbictl2;
+ unsigned int reserved10;
+ unsigned int pbirev;
+};
+#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
+
+struct pcie_system_bus_regs {
+ unsigned int reserved[3];
+ unsigned int endictl0;
+ unsigned int endictl1;
+};
+#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
+
+
+/* PCIe-Bridge */
+struct pciebrg_regs {
+ unsigned short ctrl_h8s;
+ unsigned short reserved[7];
+ unsigned short cp_addr;
+ unsigned short reserved2;
+ unsigned short cp_data;
+ unsigned short reserved3;
+ unsigned short cp_ctrl;
+};
+#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
+
+/* CPU version */
+#define CCN_PRR 0xff000044
+#define prr_mask(_val) ((_val >> 4) & 0xff)
+#define PRR_SH7757_B0 0x10
+#define PRR_SH7757_C0 0x11
+
+#define is_sh7757_b0(_val) \
+({ \
+ int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
+ __ret; \
+})
+#endif /* ifndef __ASSEMBLY__ */
+
+#endif /* _ASM_CPU_SH7757_H_ */
diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile
new file mode 100644
index 000000000..2fafdb3cf
--- /dev/null
+++ b/board/Marvell/dkb/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dkb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
new file mode 100644
index 000000000..72a2d2a98
--- /dev/null
+++ b/board/Marvell/dkb/dkb.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* Enable Console on UART2 */
+ MFP47_UART2_RXD,
+ MFP48_UART2_TXD,
+
+ MFP_EOC /*End of configureation*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
+ return 0;
+}
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
index a11add559..f7f38535f 100644
--- a/board/altera/nios2-generic/custom_fpga.h
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -50,6 +50,7 @@
/* led_pio.s1 is a altera_avalon_pio */
#define LED_PIO_BASE 0x82120870
+#define LED_PIO_WIDTH 8
/* high_res_timer.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_BASE 0x82120820
diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c
index d4496843f..4a3056435 100644
--- a/board/altera/nios2-generic/gpio.c
+++ b/board/altera/nios2-generic/gpio.c
@@ -10,6 +10,7 @@
#ifndef CONFIG_SYS_GPIO_BASE
#define ALTERA_PIO_BASE LED_PIO_BASE
+#define ALTERA_PIO_WIDTH LED_PIO_WIDTH
#define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0)
#define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4)
static u32 pio_data_reg;
@@ -20,6 +21,11 @@ int gpio_request(unsigned gpio, const char *label)
return 0;
}
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
int gpio_direction_input(unsigned gpio)
{
u32 mask = 1 << gpio;
@@ -57,4 +63,9 @@ void gpio_set_value(unsigned gpio, int value)
pio_data_reg &= ~mask;
writel(pio_data_reg, ALTERA_PIO_DATA);
}
+
+int gpio_is_valid(int number)
+{
+ return ((unsigned)number) < ALTERA_PIO_WIDTH;
+}
#endif
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
index f1594a236..e36a9d204 100644
--- a/board/dbau1x00/Makefile
+++ b/board/dbau1x00/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/eNET/config.mk b/board/eNET/config.mk
index c4242add1..9d2dfa535 100644
--- a/board/eNET/config.mk
+++ b/board/eNET/config.mk
@@ -21,8 +21,4 @@
# MA 02111-1307 USA
#
-CONFIG_SYS_TEXT_BASE = 0x06000000
-CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
-PLATFORM_RELFLAGS += -fvisibility=hidden
-PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
-PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions
+LDPPFLAGS += -DFLASH_SIZE=0x40000
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 7f0e2577f..dd0ce5451 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -35,76 +35,52 @@
DECLARE_GLOBAL_DATA_PTR;
-#undef SC520_CDP_DEBUG
-
-#ifdef SC520_CDP_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
-
-void init_sc520_enet (void)
-{
- /* Set CPU Speed to 100MHz */
- writeb(0x01, &sc520_mmcr->cpuctl);
-
- /* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
- "0: pushl %%ecx\n"
- "popl %%ecx\n"
- "loop 0b\n": : : "ecx");
-
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl $0x9fffffff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
-}
+static void enet_setup_pars(void);
/*
* Miscellaneous platform dependent initializations
*/
int board_early_init_f(void)
{
- init_sc520_enet();
-
- writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
- writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
- writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
- writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
- writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
- writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
- writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
-
- writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
- writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
- writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
- writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
- writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
- writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
- writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
-
- writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
- writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
- writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
- writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
- writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
- writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
- writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
- writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
- writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
- writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
- writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
- writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
-/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
-/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+ u16 pio_out_cfg = 0x0000;
+
+ /* Configure General Purpose Bus timing */
+ writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
+ writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
+ writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
+ writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
+ writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
+ writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
+ writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
+
+ /* Configure Programmable Input/Output Pins */
+ writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
+ writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
+ writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
+ writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
+
+ /*
+ * Turn off top board
+ * Set StrataFlash chips to 16-bit width
+ * Set StrataFlash chips to normal (non reset/power down) mode
+ */
+ pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
+ writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
+
+ /* Turn off auxiliary power output */
+ writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
+
+ /* Clear FPGA program mode */
+ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
+
+ enet_setup_pars();
/* Disable Watchdog */
writew(0x3333, &sc520_mmcr->wdtmrctl);
@@ -112,19 +88,67 @@ int board_early_init_f(void)
writew(0x0000, &sc520_mmcr->wdtmrctl);
/* Chip Select Configuration */
- writew(0x0033, &sc520_mmcr->bootcsctl);
- writew(0x0615, &sc520_mmcr->romcs1ctl);
- writew(0x0615, &sc520_mmcr->romcs2ctl);
+ writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
+ writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
+ writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
+
+ writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
+ writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
+ writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
+
+ writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
+ writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
- writeb(0x00, &sc520_mmcr->adddecctl);
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
- writeb(0x06, &sc520_mmcr->sysarbctl);
- writew(0x0003, &sc520_mmcr->sysarbmenb);
+ /* enable posted-writes */
+ writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
return 0;
}
+static void enet_setup_pars(void)
+{
+ /*
+ * PARs 11 and 12 are 2MB SRAM @ 0x19000000
+ *
+ * These are setup now because older version of U-Boot have them
+ * mapped to a different PAR which gets clobbered which prevents
+ * using SRAM for warm-booting a new image
+ */
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+ /* PARs 0 and 1 are Compact Flash slots (4kB each) */
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+ /* PAR 2 is used for Cache-As-RAM */
+
+ /*
+ * PARs 5 through 8 are additional NS16550 UARTS
+ * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+ */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+ /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
+ writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
+
+ /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+ /*
+ * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+ * Already configured in board_init16 (eNET_start16.S)
+ *
+ * PAR 15 is Boot ROM
+ * Already configured in board_init16 (eNET_start16.S)
+ */
+}
+
+
int board_early_init_r(void)
{
/* CPU Speed to 100MHz */
@@ -136,12 +160,6 @@ int board_early_init_r(void)
return 0;
}
-int dram_init(void)
-{
- init_sc520_dram();
- return 0;
-}
-
void show_boot_progress(int val)
{
uchar led_mask;
@@ -165,22 +183,23 @@ int last_stage_init(void)
outb(0x00, LED_LATCH_ADDRESS);
- register_timer_isr (enet_timer_isr);
+ register_timer_isr(enet_timer_isr);
printf("Serck Controls eNET\n");
return 0;
}
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
- } else
+ } else {
return 0;
+ }
}
int board_eth_init(bd_t *bis)
@@ -204,10 +223,18 @@ void setup_pcat_compatibility()
*/
writew(0x0000,&sc520_mmcr->intpinpol);
- /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
+ /*
+ * PIT 0 -> IRQ0
+ * RTC -> IRQ8
+ * FP error -> IRQ13
+ * UART1 -> IRQ4
+ * UART2 -> IRQ3
+ */
writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
+ writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
+ writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
/* Disable all other interrupt sources */
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
@@ -215,11 +242,6 @@ void setup_pcat_compatibility()
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 137fe41b4..1b3d289f5 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -29,10 +29,3 @@ early_board_init:
/* No 32-bit board specific initialisation */
jmp early_board_init_ret
-.globl cpu_halt_asm
-cpu_halt_asm:
- movb $0x0f, %al
- movw $LED_LATCH_ADDRESS, %dx
- outb %al, %dx
- hlt
- jmp cpu_halt_asm
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 06cfd558d..77e551964 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -29,7 +29,9 @@
/* #include <asm/ic/sc520_defs.h> */
+#include "config.h"
#include "hardware.h"
+#include <asm/ic/sc520.h>
.text
.section .start16, "ax"
@@ -46,20 +48,15 @@ board_init16:
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
- movl $0x00c0, %edi /* SC520_PAR14 */
- movl $0x8bfff800, %eax /* TODO: Check this */
+ movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
+ movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
- movl $0x00c4, %edi /* SC520_PAR15 */
- movl $0x38201000, %eax
+ movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
+ movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
- /* Disable SDRAM write buffer */
- movw $0x0040, %di /* SC520_DBCTL */
- xorw %ax, %ax
- movb %al, (%di)
-
/* Disabe MMCR alias */
movw $0xfffc, %dx
movl $0x000000cb, %eax
diff --git a/board/espt/config.mk b/board/espt/config.mk
deleted file mode 100644
index 21b51de76..000000000
--- a/board/espt/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# board/espt/config.mk
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 11dfd84fe..3ecfb06cc 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -361,6 +361,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
+ update_crc();
return 0;
}
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 9f471692d..a9f0fb477 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -33,13 +33,19 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
-int board_init(void)
+int board_early_init_f(void)
{
/* CS5: CPLD incl. network controller */
__REG(CSCR_U(5)) = 0x0000d843;
@@ -50,6 +56,11 @@ int board_init(void)
mx31_uart1_hw_init();
mx31_spi2_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd23309..86a3ec882 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,8 +26,9 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -36,8 +37,29 @@
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
int board_early_init_f(void)
{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
+
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
@@ -66,10 +88,18 @@ int board_early_init_f(void)
/*
* wait for fpga-done
- * fail ungraceful if fpga is not configuring properly
*/
- while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
- ;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!(in_le16((void *)LATCH2_BASE)
+ & CONFIG_SYS_FPGA_DONE(k))) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
/*
* setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@ int board_early_init_f(void)
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- /*
- * wait for fpga out of reset
- * fail ungraceful if fpga is not working properly
- */
- while (1) {
- fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
- if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
- REFLECTION_TESTPATTERN_INV)
- break;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ out_le16(&fpga->reflection_low,
+ REFLECTION_TESTPATTERN);
+ if (in_le16(&fpga->reflection_high) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
}
return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index ed3120784..169418c28 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -27,6 +27,7 @@ LIB = $(obj)lib$(BOARD).o
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
COBJS := $(BOARD).o $(COBJS-y)
SOBJS =
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 000000000..df7fb143c
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+ UNITTYPE_VIDEO_USER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+ HWVER_101 = 0,
+ HWVER_110 = 1,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_156250 = 2,
+};
+
+enum {
+ RAM_NONE = 0,
+ RAM_DDR2_32 = 1,
+ RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_rs232;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+ int fpga_state = get_fpga_state(dev);
+
+ printf("FPGA%d: ", dev);
+
+ hardware_version = versions & 0x000f;
+
+ if (fpga_state
+ && !((hardware_version == HWVER_101)
+ && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+ puts("not available\n");
+ print_fpga_state(dev);
+ return;
+ }
+
+ unit_type = (versions >> 4) & 0x000f;
+ hardware_version = versions & 0x000f;
+ feature_compression = (fpga_features >> 13) & 0x0003;
+ feature_rs232 = fpga_features & (1<<11);
+ feature_audio = (fpga_features >> 9) & 0x0003;
+ feature_sysclock = (fpga_features >> 7) & 0x0003;
+ feature_ramconfig = (fpga_features >> 5) & 0x0003;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features >> 2) & 0x0003;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel Userside");
+ break;
+
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel Userside");
+ break;
+
+ case UNITTYPE_VIDEO_SERVER:
+ printf("Videochannel Serverside");
+ break;
+
+ case UNITTYPE_MAIN_SERVER:
+ printf("Mainchannel Serverside");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_101:
+ printf(" HW-Ver 1.01\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ switch (feature_sysclock) {
+ case SYSCLK_156250:
+ printf(", clock 156.25 MHz");
+ break;
+
+ default:
+ printf(", clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_ramconfig) {
+ case RAM_NONE:
+ printf("no RAM");
+ break;
+
+ case RAM_DDR2_32:
+ printf("RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR2_64:
+ printf("RAM 64 bit DDR2");
+ break;
+
+ default:
+ printf("RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned k;
+ char *s = getenv("serial#");
+
+ printf("Board: ");
+
+ printf("DLVision 10G");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ print_fpga_info(k);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ unsigned k;
+
+ for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+ if (!get_fpga_state(k)
+ || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+ osd_probe(k);
+
+ return 0;
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 80877b61f..0974019ef 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -29,7 +29,7 @@
#include <miiphy.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
@@ -37,13 +37,6 @@
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_FEATURES = 0x0004,
- REG_FPGA_VERSION = 0x0006,
- REG_QUAD_SERDES_RESET = 0x0012,
-};
-
-enum {
UNITTYPE_CCD_SWITCH = 1,
};
@@ -94,10 +87,11 @@ err_out:
*/
int checkboard(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
@@ -166,6 +160,7 @@ int checkboard(void)
*/
int last_stage_init(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
@@ -175,7 +170,7 @@ int last_stage_init(void)
configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
- fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+ out_le16(&fpga->quad_serdes_reset, 0);
return 0;
}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ecd6cb239..20770e4ef 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,14 +27,9 @@
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
-#include "../common/fpga.h"
-#include "../common/osd.h"
+#include <gdsys_fpga.h>
-enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_VERSION = 0x0004,
- REG_FPGA_FEATURES = 0x0006,
-};
+#include "../common/osd.h"
enum {
UNITTYPE_MAIN_SERVER = 0,
@@ -74,10 +69,11 @@ enum {
*/
int checkboard(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_compression;
@@ -214,7 +210,7 @@ int checkboard(void)
int last_stage_init(void)
{
- return osd_probe();
+ return osd_probe(0);
}
/*
@@ -222,15 +218,15 @@ int last_stage_init(void)
*/
void fpga_gpio_set(int pin)
{
- out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+ out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
}
void fpga_gpio_clear(int pin)
{
- out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+ out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
}
int fpga_gpio_get(int pin)
{
- return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+ return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
}
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 225703738..4c7fc99f0 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -31,6 +31,7 @@ LIB = $(obj)lib$(VENDOR).o
COBJS-$(CONFIG_IO) += miiphybb.o
COBJS-$(CONFIG_IOCON) += osd.o
+COBJS-$(CONFIG_DLVISION_10G) += osd.o
COBJS := $(COBJS-y)
SOBJS =
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 239c870ef..4d8c046a8 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -25,10 +25,16 @@
#include <i2c.h>
#include <asm/io.h>
-#include "fpga.h"
+#include <gdsys_fpga.h>
#define CH7301_I2C_ADDR 0x75
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
#define PIXCLK_640_480_60 25180000
#define BASE_WIDTH 32
@@ -36,17 +42,6 @@
#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
enum {
- REG_CONTROL = 0x0010,
- REG_MPC3W_CONTROL = 0x001a,
- REG_VIDEOCONTROL = 0x0042,
- REG_OSDVERSION = 0x0100,
- REG_OSDFEATURES = 0x0102,
- REG_OSDCONTROL = 0x0104,
- REG_XY_SIZE = 0x0106,
- REG_VIDEOMEM = 0x0800,
-};
-
-enum {
CH7301_CM = 0x1c, /* Clock Mode Register */
CH7301_IC = 0x1d, /* Input Clock Register */
CH7301_GPIO = 0x1e, /* GPIO Control Register */
@@ -67,6 +62,41 @@ enum {
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
};
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_i2c_t *i2c = &fpga->i2c;
+
+ while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+ ;
+ out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
+ out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_i2c_t *i2c = &fpga->i2c;
+ unsigned int ctr = 0;
+
+ while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+ ;
+ out_le16(&fpga->extended_interrupt, 1 << 14);
+ out_le16(&i2c->write_mailbox_ext, reg);
+ out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
+ while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("iic receive timeout\n");
+ break;
+ }
+ }
+ return in_le16(&i2c->read_mailbox_ext) >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
{
@@ -92,8 +122,9 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
*feedback_div = m;
}
-static void mpc92469ac_set(unsigned int fout)
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
unsigned int n;
unsigned int m;
unsigned int bitval = 0;
@@ -114,17 +145,85 @@ static void mpc92469ac_set(unsigned int fout)
break;
}
- fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+ out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
}
+#endif
-static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+ unsigned int *_mint, unsigned int *_mfrac,
+ unsigned int *_n)
{
+ unsigned int n;
+ unsigned int foutiic;
+ unsigned int fvcoiic;
+ unsigned int mint;
+ unsigned long long mfrac;
+
+ n = 2550000000U / fout;
+ if ((n & 1) && (n > 5))
+ n -= 1;
+
+ foutiic = fout - (fout / 10000);
+ fvcoiic = foutiic * n;
+
+ mint = fvcoiic / 114285000;
+ if ((mint < 17) || (mint > 63))
+ printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+ mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+ / 114285000LL;
+
+ *_mint = mint;
+ *_mfrac = mfrac;
+ *_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+ unsigned int n;
+ unsigned int mint;
+ unsigned int mfrac;
+ u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+ ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+
+ reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 |= (mint & 0x1f) << 1;
+ reg0 |= (mfrac >> 17) & 0x01;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+ reg4 = mfrac >> 9;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+ reg8 = mfrac >> 1;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+ reg12 = mfrac << 7;
+ reg12 |= n & 0x7f;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+ reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 |= 0x20;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+ reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 |= mint & (1 << 5);
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+ u16 *data, size_t charcount)
+{
+ ihs_fpga_t *fpga =
+ (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
unsigned int k;
for (k = 0; k < charcount; ++k) {
if (offset + k >= BUFSIZE)
return -1;
- fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+ out_le16(&fpga->videomem + offset + k, data[k]);
}
return charcount;
@@ -132,46 +231,59 @@ static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned x;
- unsigned y;
- unsigned charcount;
- unsigned len;
- u8 color;
- unsigned int k;
- u16 buf[BUFSIZE];
- char *text;
-
- if (argc < 5) {
- return cmd_usage(cmdtp);
+ unsigned screen;
+
+ for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned charcount;
+ unsigned len;
+ u8 color;
+ unsigned int k;
+ u16 buf[BUFSIZE];
+ char *text;
+ int res;
+
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+ charcount = strlen(text);
+ len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+ for (k = 0; k < len; ++k)
+ buf[k] = (text[k] << 8) | color;
+
+ res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+ if (res < 0)
+ return res;
}
- x = simple_strtoul(argv[1], NULL, 16);
- y = simple_strtoul(argv[2], NULL, 16);
- color = simple_strtoul(argv[3], NULL, 16);
- text = argv[4];
- charcount = strlen(text);
- len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
-
- for (k = 0; k < len; ++k)
- buf[k] = (text[k] << 8) | color;
-
- return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+ return 0;
}
-int osd_probe(void)
+int osd_probe(unsigned screen)
{
- u8 value;
- u16 version = fpga_get_reg(REG_OSDVERSION);
- u16 features = fpga_get_reg(REG_OSDFEATURES);
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_osd_t *osd = &fpga->osd;
+ u16 version = in_le16(&osd->version);
+ u16 features = in_le16(&osd->features);
unsigned width;
unsigned height;
+ u8 value;
width = ((features & 0x3f00) >> 8) + 1;
height = (features & 0x001f) + 1;
- printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
- version/100, version%100, width, height);
+ printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ screen, version/100, version%100, width, height);
+#ifdef CONFIG_SYS_CH7301
value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
if (value != 0x17) {
printf(" Probing CH7301 failed, DID %02x\n", value);
@@ -182,51 +294,86 @@ int osd_probe(void)
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+ mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
- mpc92469ac_set(PIXCLK_640_480_60);
- fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
- fpga_set_reg(REG_OSDCONTROL, 0x0049);
+#ifdef CONFIG_SYS_ICS8N3QV01
+ ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
- fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+#ifdef CONFIG_SYS_SIL1178
+ value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ if (value != 0x06) {
+ printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+ return -1;
+ }
+ /* magic initialization sequence adapted from datasheet */
+ fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+ out_le16(&fpga->videocontrol, 0x0002);
+ out_le16(&osd->control, 0x0049);
+
+ out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
return 0;
}
int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned x;
- unsigned y;
- unsigned k;
- u16 buffer[BASE_WIDTH];
- char *rp;
- u16 *wp = buffer;
- unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
-
- if ((argc < 4) || (strlen(argv[3]) % 4)) {
- return cmd_usage(cmdtp);
- }
-
- x = simple_strtoul(argv[1], NULL, 16);
- y = simple_strtoul(argv[2], NULL, 16);
- rp = argv[3];
-
-
- while (*rp) {
- char substr[5];
-
- memcpy(substr, rp, 4);
- substr[4] = 0;
- *wp = simple_strtoul(substr, NULL, 16);
-
- rp += 4;
- wp++;
- if (wp - buffer > BASE_WIDTH)
- break;
- }
-
- for (k = 0; k < count; ++k) {
- unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
- osd_write_videomem(offset, buffer, wp - buffer);
+ unsigned screen;
+
+ for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned k;
+ u16 buffer[BASE_WIDTH];
+ char *rp;
+ u16 *wp = buffer;
+ unsigned count = (argc > 4) ?
+ simple_strtoul(argv[4], NULL, 16) : 1;
+
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ rp = argv[3];
+
+
+ while (*rp) {
+ char substr[5];
+
+ memcpy(substr, rp, 4);
+ substr[4] = 0;
+ *wp = simple_strtoul(substr, NULL, 16);
+
+ rp += 4;
+ wp++;
+ if (wp - buffer > BASE_WIDTH)
+ break;
+ }
+
+ for (k = 0; k < count; ++k) {
+ unsigned offset =
+ y * BASE_WIDTH + x + k * (wp - buffer);
+ osd_write_videomem(screen, offset, buffer,
+ wp - buffer);
+ }
}
return 0;
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
index 4431cbc09..c59d9c3ab 100644
--- a/board/gdsys/common/osd.h
+++ b/board/gdsys/common/osd.h
@@ -24,6 +24,6 @@
#ifndef _OSD_H_
#define _OSD_H_
-int osd_probe(void);
+int osd_probe(unsigned screen);
#endif
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
index fe525ec70..b76579568 100644
--- a/board/incaip/lowlevel_init.S
+++ b/board/incaip/lowlevel_init.S
@@ -283,7 +283,7 @@ lowlevel_init:
/* EBU, CGU and SDRAM Initialization.
*/
- li a0, CPU_CLOCK_RATE
+ li a0, CONFIG_CPU_CLOCK_RATE
move t0, ra
/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
diff --git a/board/mpr2/config.mk b/board/mpr2/config.mk
deleted file mode 100644
index 4a4bca17d..000000000
--- a/board/mpr2/config.mk
+++ /dev/null
@@ -1,37 +0,0 @@
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# Copyright (C) 2008
-# Mark Jonas <mark.jonas@de.bosch.com>
-#
-# board/mpr2/config.mk
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
diff --git a/board/ms7722se/config.mk b/board/ms7722se/config.mk
deleted file mode 100644
index 3f1606bf8..000000000
--- a/board/ms7722se/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7722se/config.mk
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
new file mode 100644
index 000000000..b2c412cf5
--- /dev/null
+++ b/board/nvidia/common/board.c
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct tegra2_sysinfo sysinfo = {
+ CONFIG_TEGRA2_BOARD_STRING
+};
+
+/*
+ * Routine: timer_init
+ * Description: init the timestamp and lastinc value
+ */
+int timer_init(void)
+{
+ reset_timer();
+ return 0;
+}
+
+/*
+ * Routine: clock_init_uart
+ * Description: init the PLL and clock for the UART(s)
+ */
+static void clock_init_uart(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ static int pllp_init_done;
+ u32 reg;
+
+ if (!pllp_init_done) {
+ /* Override pllp setup for 216MHz operation. */
+ reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
+ reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
+ writel(reg, &clkrst->crc_pllp_base);
+
+ reg |= PLL_ENABLE;
+ writel(reg, &clkrst->crc_pllp_base);
+
+ reg &= ~PLL_BYPASS;
+ writel(reg, &clkrst->crc_pllp_base);
+
+ pllp_init_done++;
+ }
+
+ /* Now do the UART reset/clock enable */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+ /* Assert Reset to UART */
+ reg = readl(&clkrst->crc_rst_dev_l);
+ reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */
+ writel(reg, &clkrst->crc_rst_dev_l);
+
+ /* Enable clk to UART */
+ reg = readl(&clkrst->crc_clk_out_enb_l);
+ reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */
+ writel(reg, &clkrst->crc_clk_out_enb_l);
+
+ /* Enable pllp_out0 to UART */
+ reg = readl(&clkrst->crc_clk_src_uarta);
+ reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
+ writel(reg, &clkrst->crc_clk_src_uarta);
+
+ /* wait for 2us */
+ udelay(2);
+
+ /* De-assert reset to UART */
+ reg = readl(&clkrst->crc_rst_dev_l);
+ reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */
+ writel(reg, &clkrst->crc_rst_dev_l);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+ /* Assert Reset to UART */
+ reg = readl(&clkrst->crc_rst_dev_u);
+ reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */
+ writel(reg, &clkrst->crc_rst_dev_u);
+
+ /* Enable clk to UART */
+ reg = readl(&clkrst->crc_clk_out_enb_u);
+ reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */
+ writel(reg, &clkrst->crc_clk_out_enb_u);
+
+ /* Enable pllp_out0 to UART */
+ reg = readl(&clkrst->crc_clk_src_uartd);
+ reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
+ writel(reg, &clkrst->crc_clk_src_uartd);
+
+ /* wait for 2us */
+ udelay(2);
+
+ /* De-assert reset to UART */
+ reg = readl(&clkrst->crc_rst_dev_u);
+ reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */
+ writel(reg, &clkrst->crc_rst_dev_u);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for the UART(s)
+ */
+static void pin_mux_uart(void)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 reg;
+
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+ reg = readl(&pmt->pmt_ctl_c);
+ reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
+ writel(reg, &pmt->pmt_ctl_c);
+
+ reg = readl(&pmt->pmt_tri_a);
+ reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
+ reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
+ writel(reg, &pmt->pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+ reg = readl(&pmt->pmt_ctl_b);
+ reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
+ writel(reg, &pmt->pmt_ctl_b);
+
+ reg = readl(&pmt->pmt_tri_a);
+ reg &= ~Z_GMC; /* Z_GMC = normal (0) */
+ writel(reg, &pmt->pmt_tri_a);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: clock_init
+ * Description: Do individual peripheral clock reset/enables
+ */
+void clock_init(void)
+{
+ clock_init_uart();
+}
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pin_mux_uart();
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ /* boot param addr */
+ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+ /* board id for Linux */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* Initialize peripheral clocks */
+ clock_init();
+
+ /* Initialize periph pinmuxes */
+ pinmux_init();
+
+ return 0;
+}
+
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
new file mode 100644
index 000000000..3a146cb9c
--- /dev/null
+++ b/board/nvidia/harmony/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS += ../common/board.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
new file mode 100644
index 000000000..3a146cb9c
--- /dev/null
+++ b/board/nvidia/seaboard/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS += ../common/board.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
index 542601af1..719f268f2 100644
--- a/board/purple/u-boot.lds
+++ b/board/purple/u-boot.lds
@@ -36,11 +36,6 @@ SECTIONS
{
arch/mips/cpu/start.o (.text)
board/purple/lowlevel_init.o (.text)
- arch/mips/cpu/cache.o (.text)
- common/main.o (.text)
- common/dlmalloc.o (.text)
- common/cmd_boot.o (.text)
- lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
diff --git a/board/renesas/ap325rxa/config.mk b/board/renesas/ap325rxa/config.mk
deleted file mode 100644
index f572afdd7..000000000
--- a/board/renesas/ap325rxa/config.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
diff --git a/board/renesas/r2dplus/config.mk b/board/renesas/r2dplus/config.mk
deleted file mode 100644
index 55163b925..000000000
--- a/board/renesas/r2dplus/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# Copyright (C) 2007,2008
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-CONFIG_SYS_TEXT_BASE = 0x0FFC0000
diff --git a/board/renesas/r7780mp/config.mk b/board/renesas/r7780mp/config.mk
deleted file mode 100644
index 70ee3fd25..000000000
--- a/board/renesas/r7780mp/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-#
-# board/r77870mp/config.mk
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x0FFC0000
diff --git a/board/renesas/rsk7203/config.mk b/board/renesas/rsk7203/config.mk
deleted file mode 100644
index 5b533f65b..000000000
--- a/board/renesas/rsk7203/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/rsk7203/config.mk
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x0C7C0000
diff --git a/board/renesas/MigoR/config.mk b/board/renesas/sh7757lcr/Makefile
index ffe954c10..e2e46ba08 100644
--- a/board/renesas/MigoR/config.mk
+++ b/board/renesas/sh7757lcr/Makefile
@@ -1,11 +1,5 @@
#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/MigoR/config.mk
+# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -22,10 +16,28 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := sh7757lcr.o spi-boot.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(obj).depend $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S
new file mode 100644
index 000000000..ab1aa494a
--- /dev/null
+++ b/board/renesas/sh7757lcr/lowlevel_init.S
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ mov.l \addr, r1
+ mov.l \data, r0
+ mov.l @r1, r2
+ or r2, r0
+ mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ mov.l DBWAIT_A, r0
+ mov.l @r0, r1
+.endm
+
+ .global lowlevel_init
+ .section .spiboot1.text
+ .align 2
+
+lowlevel_init:
+
+ /*------- GPIO -------*/
+ write8 PGDR_A, PGDR_D /* eMMC power off */
+
+ write16 PACR_A, PACR_D
+ write16 PBCR_A, PBCR_D
+ write16 PCCR_A, PCCR_D
+ write16 PDCR_A, PDCR_D
+ write16 PECR_A, PECR_D
+ write16 PFCR_A, PFCR_D
+ write16 PGCR_A, PGCR_D
+ write16 PHCR_A, PHCR_D
+ write16 PICR_A, PICR_D
+ write16 PJCR_A, PJCR_D
+ write16 PKCR_A, PKCR_D
+ write16 PLCR_A, PLCR_D
+ write16 PMCR_A, PMCR_D
+ write16 PNCR_A, PNCR_D
+ write16 POCR_A, POCR_D
+ write16 PQCR_A, PQCR_D
+ write16 PRCR_A, PRCR_D
+ write16 PSCR_A, PSCR_D
+ write16 PTCR_A, PTCR_D
+ write16 PUCR_A, PUCR_D
+ write16 PVCR_A, PVCR_D
+ write16 PWCR_A, PWCR_D
+ write16 PXCR_A, PXCR_D
+ write16 PYCR_A, PYCR_D
+ write16 PZCR_A, PZCR_D
+ write16 PSEL0_A, PSEL0_D
+ write16 PSEL1_A, PSEL1_D
+ write16 PSEL2_A, PSEL2_D
+ write16 PSEL3_A, PSEL3_D
+ write16 PSEL4_A, PSEL4_D
+ write16 PSEL5_A, PSEL5_D
+ write16 PSEL6_A, PSEL6_D
+ write16 PSEL7_A, PSEL7_D
+ write16 PSEL8_A, PSEL8_D
+
+ bra exit_gpio
+ nop
+
+ .align 4
+
+/*------- GPIO -------*/
+PGDR_A: .long 0xffec0040
+PACR_A: .long 0xffec0000
+PBCR_A: .long 0xffec0002
+PCCR_A: .long 0xffec0004
+PDCR_A: .long 0xffec0006
+PECR_A: .long 0xffec0008
+PFCR_A: .long 0xffec000a
+PGCR_A: .long 0xffec000c
+PHCR_A: .long 0xffec000e
+PICR_A: .long 0xffec0010
+PJCR_A: .long 0xffec0012
+PKCR_A: .long 0xffec0014
+PLCR_A: .long 0xffec0016
+PMCR_A: .long 0xffec0018
+PNCR_A: .long 0xffec001a
+POCR_A: .long 0xffec001c
+PQCR_A: .long 0xffec0020
+PRCR_A: .long 0xffec0022
+PSCR_A: .long 0xffec0024
+PTCR_A: .long 0xffec0026
+PUCR_A: .long 0xffec0028
+PVCR_A: .long 0xffec002a
+PWCR_A: .long 0xffec002c
+PXCR_A: .long 0xffec002e
+PYCR_A: .long 0xffec0030
+PZCR_A: .long 0xffec0032
+PSEL0_A: .long 0xffec0070
+PSEL1_A: .long 0xffec0072
+PSEL2_A: .long 0xffec0074
+PSEL3_A: .long 0xffec0076
+PSEL4_A: .long 0xffec0078
+PSEL5_A: .long 0xffec007a
+PSEL6_A: .long 0xffec007c
+PSEL7_A: .long 0xffec0082
+PSEL8_A: .long 0xffec0084
+
+PGDR_D: .long 0x80
+PACR_D: .long 0x0000
+PBCR_D: .long 0x0001
+PCCR_D: .long 0x0000
+PDCR_D: .long 0x0000
+PECR_D: .long 0x0000
+PFCR_D: .long 0x0000
+PGCR_D: .long 0x0000
+PHCR_D: .long 0x0000
+PICR_D: .long 0x0000
+PJCR_D: .long 0x0000
+PKCR_D: .long 0x0003
+PLCR_D: .long 0x0000
+PMCR_D: .long 0x0000
+PNCR_D: .long 0x0000
+POCR_D: .long 0x0000
+PQCR_D: .long 0xc000
+PRCR_D: .long 0x0000
+PSCR_D: .long 0x0000
+PTCR_D: .long 0x0000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+PUCR_D: .long 0x0055
+#else
+PUCR_D: .long 0x0000
+#endif
+PVCR_D: .long 0x0000
+PWCR_D: .long 0x0000
+PXCR_D: .long 0x0000
+PYCR_D: .long 0x0000
+PZCR_D: .long 0x0000
+PSEL0_D: .long 0xfe00
+PSEL1_D: .long 0x0000
+PSEL2_D: .long 0x3000
+PSEL3_D: .long 0xff00
+PSEL4_D: .long 0x771f
+PSEL5_D: .long 0x0ffc
+PSEL6_D: .long 0x00ff
+PSEL7_D: .long 0xfc00
+PSEL8_D: .long 0x0000
+
+ .align 2
+
+exit_gpio:
+ mov #0, r14
+ mova 2f, r0
+ mov.l PC_MASK, r1
+ tst r0, r1
+ bf 2f
+
+ bra exit_pmb
+ nop
+
+ .align 2
+
+/* If CPU runs on SDRAM, PC is 0x8???????. */
+PC_MASK: .long 0x20000000
+
+2:
+ mov #1, r14
+
+ mov.l EXPEVT_A, r0
+ mov.l @r0, r0
+ mov.l EXPEVT_POWER_ON_RESET, r1
+ cmp/eq r0, r1
+ bt 1f
+
+ /*
+ * If EXPEVT value is manual reset or tlb multipul-hit,
+ * initialization of DDR3IF is not necessary.
+ */
+ bra exit_ddr
+ nop
+
+1:
+ /* For Core Reset */
+ mov.l DBACEN_A, r0
+ mov.l @r0, r0
+ cmp/eq #0, r0
+ bt 3f
+
+ /*
+ * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ * initialization of DDR3-SDRAM.
+ */
+ bra exit_ddr
+ nop
+
+3:
+ /*------- DDR3IF -------*/
+ /* oscillation stabilization time */
+ wait_timer WAIT_OSC_TIME
+
+ /* step 3 */
+ write32 DBCMD_A, DBCMD_RSTL_VAL
+ wait_timer WAIT_30US
+
+ /* step 4 */
+ write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ /* step 5 */
+ write32 DBKIND_A, DBKIND_D
+
+ /* step 6 */
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBTR4_A, DBTR4_D
+ write32 DBTR5_A, DBTR5_D
+ write32 DBTR6_A, DBTR6_D
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D
+ write32 DBTR13_A, DBTR13_D
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D
+ write32 DBTR17_A, DBTR17_D
+ write32 DBTR18_A, DBTR18_D
+ write32 DBTR19_A, DBTR19_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ /* step 7 */
+ write32 DBPDCNT3_A, DBPDCNT3_D
+
+ /* step 8 */
+ write32 DBPDCNT1_A, DBPDCNT1_D
+ write32 DBPDCNT2_A, DBPDCNT2_D
+ write32 DBPDLCK_A, DBPDLCK_D
+ write32 DBPDRGA_A, DBPDRGA_D
+ write32 DBPDRGD_A, DBPDRGD_D
+
+ /* step 9 */
+ wait_timer WAIT_30US
+
+ /* step 10 */
+ write32 DBPDCNT0_A, DBPDCNT0_D
+
+ /* step 11 */
+ wait_timer WAIT_30US
+ wait_timer WAIT_30US
+
+ /* step 12 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ wait_DBCMD
+
+ /* step 13 */
+ write32 DBCMD_A, DBCMD_RSTH_VAL
+ wait_DBCMD
+
+ /* step 14 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ /* step 15 */
+ write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ /* step 16 */
+ write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ /* step 17 */
+ write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ /* step 18 */
+ write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ /* step 19 */
+ write32 DBCMD_A, DBCMD_MRS0_VAL
+
+ /* step 20 */
+ write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ write32 DBCMD_A, DBCMD_REF_VAL
+ write32 DBCMD_A, DBCMD_REF_VAL
+ wait_DBCMD
+
+ /* step 21 */
+ write32 DBADJ0_A, DBADJ0_D
+ write32 DBADJ1_A, DBADJ1_D
+ write32 DBADJ2_A, DBADJ2_D
+
+ /* step 22 */
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D
+ write32 DBRFCNF2_A, DBRFCNF2_D
+
+ /* step 23 */
+ write32 DBCALCNF_A, DBCALCNF_D
+
+ /* step 24 */
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ /* step 25 */
+ write32 DBACEN_A, DBACEN_D
+
+ /* step 26 */
+ wait_DBCMD
+
+ /* enable DDR-ECC */
+ write32 ECD_ECDEN_A, ECD_ECDEN_D
+ write32 ECD_INTSR_A, ECD_INTSR_D
+ write32 ECD_SPACER_A, ECD_SPACER_D
+ write32 ECD_MCR_A, ECD_MCR_D
+
+ bra exit_ddr
+ nop
+
+ .align 4
+
+EXPEVT_A: .long 0xff000024
+EXPEVT_POWER_ON_RESET: .long 0x00000000
+
+/*------- DDR3IF -------*/
+DBCMD_A: .long 0xfe800018
+DBKIND_A: .long 0xfe800020
+DBCONF_A: .long 0xfe800024
+DBTR0_A: .long 0xfe800040
+DBTR1_A: .long 0xfe800044
+DBTR2_A: .long 0xfe800048
+DBTR3_A: .long 0xfe800050
+DBTR4_A: .long 0xfe800054
+DBTR5_A: .long 0xfe800058
+DBTR6_A: .long 0xfe80005c
+DBTR7_A: .long 0xfe800060
+DBTR8_A: .long 0xfe800064
+DBTR9_A: .long 0xfe800068
+DBTR10_A: .long 0xfe80006c
+DBTR11_A: .long 0xfe800070
+DBTR12_A: .long 0xfe800074
+DBTR13_A: .long 0xfe800078
+DBTR14_A: .long 0xfe80007c
+DBTR15_A: .long 0xfe800080
+DBTR16_A: .long 0xfe800084
+DBTR17_A: .long 0xfe800088
+DBTR18_A: .long 0xfe80008c
+DBTR19_A: .long 0xfe800090
+DBRNK0_A: .long 0xfe800100
+DBPDCNT0_A: .long 0xfe800200
+DBPDCNT1_A: .long 0xfe800204
+DBPDCNT2_A: .long 0xfe800208
+DBPDCNT3_A: .long 0xfe80020c
+DBPDLCK_A: .long 0xfe800280
+DBPDRGA_A: .long 0xfe800290
+DBPDRGD_A: .long 0xfe8002a0
+DBADJ0_A: .long 0xfe8000c0
+DBADJ1_A: .long 0xfe8000c4
+DBADJ2_A: .long 0xfe8000c8
+DBRFCNF0_A: .long 0xfe8000e0
+DBRFCNF1_A: .long 0xfe8000e4
+DBRFCNF2_A: .long 0xfe8000e8
+DBCALCNF_A: .long 0xfe8000f4
+DBRFEN_A: .long 0xfe800014
+DBACEN_A: .long 0xfe800010
+DBWAIT_A: .long 0xfe80001c
+
+WAIT_OSC_TIME: .long 6000
+WAIT_30US: .long 13333
+
+DBCMD_RSTL_VAL: .long 0x20000000
+DBCMD_PDEN_VAL: .long 0x1000d73c
+DBCMD_WAIT_VAL: .long 0x0000d73c
+DBCMD_RSTH_VAL: .long 0x2100d73c
+DBCMD_PDXT_VAL: .long 0x110000c8
+DBCMD_MRS0_VAL: .long 0x28000930
+DBCMD_MRS1_VAL: .long 0x29000004
+DBCMD_MRS2_VAL: .long 0x2a000008
+DBCMD_MRS3_VAL: .long 0x2b000000
+DBCMD_ZQCL_VAL: .long 0x03000200
+DBCMD_REF_VAL: .long 0x0c000000
+DBCMD_SRXT_VAL: .long 0x19000000
+DBKIND_D: .long 0x00000007
+DBCONF_D: .long 0x0f030a01
+DBTR0_D: .long 0x00000007
+DBTR1_D: .long 0x00000006
+DBTR2_D: .long 0x00000000
+DBTR3_D: .long 0x00000007
+DBTR4_D: .long 0x00070007
+DBTR5_D: .long 0x0000001b
+DBTR6_D: .long 0x00000014
+DBTR7_D: .long 0x00000005
+DBTR8_D: .long 0x00000015
+DBTR9_D: .long 0x00000006
+DBTR10_D: .long 0x00000008
+DBTR11_D: .long 0x00000007
+DBTR12_D: .long 0x0000000e
+DBTR13_D: .long 0x00000056
+DBTR14_D: .long 0x00000006
+DBTR15_D: .long 0x00000004
+DBTR16_D: .long 0x00150002
+DBTR17_D: .long 0x000c0017
+DBTR18_D: .long 0x00000200
+DBTR19_D: .long 0x00000040
+DBRNK0_D: .long 0x00000001
+DBPDCNT0_D: .long 0x00000001
+DBPDCNT1_D: .long 0x00000001
+DBPDCNT2_D: .long 0x00000000
+DBPDCNT3_D: .long 0x00004010
+DBPDLCK_D: .long 0x0000a55a
+DBPDRGA_D: .long 0x00000028
+DBPDRGD_D: .long 0x00017100
+
+DBADJ0_D: .long 0x00000000
+DBADJ1_D: .long 0x00000000
+DBADJ2_D: .long 0x18061806
+DBRFCNF0_D: .long 0x000001ff
+DBRFCNF1_D: .long 0x08001000
+DBRFCNF2_D: .long 0x00000000
+DBCALCNF_D: .long 0x0000ffff
+DBRFEN_D: .long 0x00000001
+DBACEN_D: .long 0x00000001
+
+/*------- DDR-ECC -------*/
+ECD_ECDEN_A: .long 0xffc1012c
+ECD_ECDEN_D: .long 0x00000001
+ECD_INTSR_A: .long 0xfe900024
+ECD_INTSR_D: .long 0xffffffff
+ECD_SPACER_A: .long 0xfe900018
+ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
+ECD_MCR_A: .long 0xfe900010
+ECD_MCR_D: .long 0x00000001
+
+ .align 2
+exit_ddr:
+
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ */
+ write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
+ write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+
+ write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ /* CPU is running on ILRAM? */
+ mov r14, r0
+ tst #1, r0
+ bt 1f
+
+ mov.l _bss_start, r15
+ mov.l _spiboot_main, r0
+100: bsrf r0
+ nop
+
+ .align 2
+_spiboot_main: .long (spiboot_main - (100b + 4))
+_bss_start: .long bss_start
+
+1:
+
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 4
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: .long 0x00000000
+
+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: .long 0xff000070
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long CCR
+CCR_D: .long CCR_CACHE_INIT
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
new file mode 100644
index 000000000..a62be24cd
--- /dev/null
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ puts("BOARD: R0P7757LC0030RL board\n");
+
+ return 0;
+}
+
+static void init_gctrl(void)
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ unsigned long graofst;
+
+ graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ writel(graofst | 0x20000f00, &gctrl->gracr3);
+}
+
+static int init_pcie_bridge_from_spi(void *buf, size_t size)
+{
+ struct spi_flash *spi;
+ int ret;
+ unsigned long pcie_addr;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ if (is_sh7757_b0())
+ pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
+ else
+ pcie_addr = SH7757LCR_PCIEBRG_ADDR;
+
+ ret = spi_flash_read(spi, pcie_addr, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static void init_pcie_bridge(void)
+{
+ struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
+ struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ int i;
+ unsigned char *data;
+ unsigned short tmp;
+ unsigned long pcie_size;
+
+ if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
+ return;
+
+ if (is_sh7757_b0())
+ pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
+ else
+ pcie_size = SH7757LCR_PCIEBRG_SIZE;
+
+ data = malloc(pcie_size);
+ if (!data) {
+ printf("%s: malloc error.\n", __func__);
+ return;
+ }
+ if (init_pcie_bridge_from_spi(data, pcie_size)) {
+ free(data);
+ return;
+ }
+
+ if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
+ data[3] == 0xff) {
+ free(data);
+ printf("%s: skipped initialization\n", __func__);
+ return;
+ }
+
+ writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
+ writew(0x0000, &pciebrg->cp_ctrl);
+ writew(0x0000, &pciebrg->cp_addr);
+
+ for (i = 0; i < pcie_size; i += 2) {
+ tmp = (data[i] << 8) | data[i + 1];
+ writew(tmp, &pciebrg->cp_data);
+ }
+
+ writew(0xa500, &pciebrg->ctrl_h8s); /* start */
+ if (!is_sh7757_b0())
+ writel(0x00000001, &pcie_setup->pbictl3);
+
+ free(data);
+}
+
+static void init_usb_phy(void)
+{
+ struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ struct usb1_port_regs *port = USB1_PORT_BASE;
+ struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ writew(0x0100, &phy->reset); /* set reset */
+ /* port0 = USB0, port1 = USB1 */
+ writew(0x0002, &phy->portsel);
+ writel(0x0001, &port->port1sel); /* port1 = Host */
+ writew(0x0111, &phy->reset); /* clear reset */
+
+ writew(0x4000, &common0->suspmode);
+ writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ writel(0x00000000, &align->ehcidatac);
+ writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void set_mac_to_sh_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = ETHER0_MAC_BASE;
+ else
+ ether = ETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, &ether->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, &ether->malr);
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = GETHER0_MAC_BASE;
+ else
+ ether = GETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, &ether->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, &ether->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x40000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 2 0xb0000000 0x50000000 1 128M 0 1
+ * 3 0xb8000000 0x58000000 1 128M 0 1
+ * 4 0x80000000 0x40000000 1 128M 1 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ * 6 0x90000000 0x50000000 1 128M 1 1
+ * 7 0x98000000 0x58000000 1 128M 1 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ struct mmu_regs *mmu = MMU_BASE;
+
+ /* clear ITLB */
+ writel(0x00000004, &mmu->mmucr);
+
+ /* delete PMB for SPIBOOT */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ /* ppn ub v s1 s0 c wt */
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+ set_pmb_on_board_init();
+
+ /* enable RMII's MDIO (disable GRMII's MDIO) */
+ writel(0x00030000, &gether->gbecont);
+
+ init_gctrl();
+ init_usb_phy();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ printf(" Physical address\n");
+ printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
+ SH7757LCR_SDRAM_PHYS_TOP,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
+ printf(" 0x%08x - 0x%08x : No Access Area\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
+ printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
+ SH7757LCR_SDRAM_DVC_SIZE - 1);
+ printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
+
+ return 0;
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ struct spi_flash *spi;
+ int ret;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (spi == NULL) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
+ SH7757LCR_ETHERNET_MAC_SIZE);
+ mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ char mac_string[64];
+ char env_string[64];
+ int i;
+ unsigned char *buf;
+
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc error.\n", __func__);
+ return;
+ }
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* Fast Ethernet */
+ for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i == 0)
+ setenv("ethaddr", mac_string);
+ else {
+ sprintf(env_string, "eth%daddr", i);
+ setenv(env_string, mac_string);
+ }
+
+ set_mac_to_sh_eth_register(i, mac_string);
+ }
+
+ /* Gigabit Ethernet */
+ for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
+ sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
+ setenv(env_string, mac_string);
+
+ set_mac_to_sh_giga_eth_register(i, mac_string);
+ }
+
+ free(buf);
+}
+
+static void init_pcie(void)
+{
+ struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
+
+ writel(0x00000ff2, &pcie_setup->ladmsk0);
+ writel(0x00000001, &pcie_setup->barmap);
+ writel(0xffcaa000, &pcie_setup->lad0);
+ writel(0x00030000, &pcie_sysbus->endictl0);
+ writel(0x00000003, &pcie_sysbus->endictl1);
+ writel(0x00000004, &pcie_setup->pbictl2);
+}
+
+static void finish_spiboot(void)
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ /*
+ * SH7757 B0 does not use LBSC.
+ * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
+ * This setting is not cleared by manual reset, So we have to set it
+ * to 0.
+ */
+ writel(0x00000000, &gctrl->spibootcan);
+}
+
+int board_late_init(void)
+{
+ init_ethernet_mac();
+ init_pcie_bridge();
+ init_pcie();
+ finish_spiboot();
+
+ return 0;
+}
+
+int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ unsigned long graofst;
+
+ writel(0xfedcba98, &gctrl->wprotect);
+ graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ writel(graofst | 0xa0000f00, &gctrl->gracr3);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ sh_g200, 1, 1, do_sh_g200,
+ "enable sh-g200",
+ "enable SH-G200 bus (disable PCIe-G200)"
+);
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, ret;
+ char mac_string[256];
+ struct spi_flash *spi;
+ unsigned char *buf;
+
+ if (argc != 5) {
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc error.\n", __func__);
+ return 1;
+ }
+
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* print current MAC address */
+ for (i = 0; i < 4; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i < 2)
+ printf(" ETHERC ch%d = %s\n", i, mac_string);
+ else
+ printf("GETHERC ch%d = %s\n", i-2, mac_string);
+ }
+ free(buf);
+ return 0;
+ }
+
+ /* new setting */
+ memset(mac_string, 0xff, sizeof(mac_string));
+ sprintf(mac_string, "%s\t%s\t%s\t%s",
+ argv[1], argv[2], argv[3], argv[4]);
+
+ /* write MAC data to SPI rom */
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ SH7757LCR_SPI_SECTOR_SIZE);
+ if (ret) {
+ printf("%s: spi_flash erase error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ sizeof(mac_string), mac_string);
+ if (ret) {
+ printf("%s: spi_flash write error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ write_mac, 5, 1, do_write_mac,
+ "write MAC address for ETHERC/GETHERC",
+ "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7757lcr/spi-boot.c b/board/renesas/sh7757lcr/spi-boot.c
new file mode 100644
index 000000000..823844e54
--- /dev/null
+++ b/board/renesas/sh7757lcr/spi-boot.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License. See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS 0x4ef80000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+#define CONFIG_SPI_ADDR 0x00010000
+#else
+#define CONFIG_SPI_ADDR 0x00000000
+#endif
+#define CONFIG_SPI_LENGTH 0x00030000
+#define CONFIG_RAM_BOOT 0x8ef80000
+
+#define SPIWDMADR 0xFE001018
+#define SPIWDMCNTR 0xFE001020
+#define SPIDMCOR 0xFE001028
+#define SPIDMINTSR 0xFE001188
+#define SPIDMINTMR 0xFE001190
+
+#define SPIDMINTSR_DMEND 0x00000004
+
+#define TBR 0xFE002000
+#define RBR 0xFE002000
+
+#define CR1 0xFE002008
+#define CR2 0xFE002010
+#define CR3 0xFE002018
+#define CR4 0xFE002020
+
+/* CR1 */
+#define SPI_TBE 0x80
+#define SPI_TBF 0x40
+#define SPI_RBE 0x20
+#define SPI_RBF 0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD 0x02
+#define SPI_SSA 0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SPI_CPOL 0x20
+#define SPI_CPHA 0x10
+#define SPI_L1M0 0x08
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_SSS 0x01
+
+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ 0x03
+
+#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ spi_write(0xfe, CR1);
+
+ spi_write(0, SPIDMCOR);
+ spi_write(0x00, CR1);
+
+ spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
+ spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ unsigned long len)
+{
+ spi_write(M25_READ, TBR);
+ spi_write((addr >> 16) & 0xFF, TBR);
+ spi_write((addr >> 8) & 0xFF, TBR);
+ spi_write(addr & 0xFF, TBR);
+
+ spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ spi_write((unsigned long)buf, SPIWDMADR);
+ spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ spi_write(1, SPIDMCOR);
+
+ spi_write(0xff, CR3);
+ spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ;
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+ spi_reset();
+ spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+ CONFIG_SPI_LENGTH);
+
+ _start();
+}
+
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
new file mode 100644
index 000000000..a88d7814a
--- /dev/null
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2011
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ arch/sh/cpu/sh4/start.o (.text)
+ *(.spiboot1.text)
+ *(.spiboot2.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ PROVIDE (__u_boot_cmd_start = .);
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ . = ALIGN(4);
+ }
+ PROVIDE (__u_boot_cmd_end = .);
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (_end = .);
+}
diff --git a/board/renesas/sh7763rdp/config.mk b/board/renesas/sh7763rdp/config.mk
deleted file mode 100644
index 54c1a5b3e..000000000
--- a/board/renesas/sh7763rdp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# board/sh7763rdp/config.mk
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8FFC0000
-
-# PLATFORM_CPPFLAGS += -DCONFIG_MULTIBOOT
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
index b5c496f76..e404fa6e4 100644
--- a/board/renesas/sh7785lcr/Makefile
+++ b/board/renesas/sh7785lcr/Makefile
@@ -23,8 +23,12 @@ LIB = $(obj)lib$(BOARD).o
COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o
SOBJS := lowlevel_init.o
-$(LIB): $(obj).depend $(COBJS) $(SOBJS)
- $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/renesas/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk
deleted file mode 100644
index 6853d2b28..000000000
--- a/board/renesas/sh7785lcr/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# CONFIG_SYS_TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifdef CONFIG_SH_32BIT
-CONFIG_SYS_TEXT_BASE = 0x8FF80000
-else
-CONFIG_SYS_TEXT_BASE = 0x0ff80000
-endif
diff --git a/board/shmin/config.mk b/board/shmin/config.mk
deleted file mode 100644
index 0c7605e7f..000000000
--- a/board/shmin/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright (C) 2010 Nobuhiro Iwamatsu
-#
-# u-boot/board/shmin/config.mk
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-#
-# TEXT_BASE refers to image _after_ relocation.
-#
-# NOTE: Must match value used in u-boot.lds (in this directory).
-#
-
-CONFIG_SYS_TEXT_BASE = 0x8DFB0000
diff --git a/boards.cfg b/boards.cfg
index c3b164e7e..45c3102b0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -105,6 +105,7 @@ imx27lite arm arm926ejs imx27lite logicpd
magnesium arm arm926ejs imx27lite logicpd mx27
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
+dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
efikamx arm armv7 efikamx - mx5
mx51evk arm armv7 mx51evk freescale mx5
@@ -127,6 +128,8 @@ omap4_sdp4430 arm armv7 sdp4430 ti
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
+harmony arm armv7 harmony nvidia tegra2
+seaboard arm armv7 seaboard nvidia tegra2
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
@@ -199,7 +202,8 @@ ibf-dsp561 blackfin blackfin
ip04 blackfin blackfin
tcm-bf518 blackfin blackfin
tcm-bf537 blackfin blackfin
-eNET i386 i386 - - sc520
+eNET i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
+eNET_SRAM i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
idmr m68k mcf52x2
TASREG m68k mcf52x2 tasreg esd
M5208EVBE m68k mcf52x2 m5208evbe freescale
@@ -213,8 +217,32 @@ M5282EVB m68k mcf52x2 m5282evb freesca
M53017EVB m68k mcf52x2 m53017evb freescale
EP2500 m68k mcf52x2 ep2500 Mercury
microblaze-generic microblaze microblaze microblaze-generic xilinx
+dbau1000 mips mips dbau1x00 - - dbau1x00:DBAU1000
+dbau1100 mips mips dbau1x00 - - dbau1x00:DBAU1100
+dbau1500 mips mips dbau1x00 - - dbau1x00:DBAU1500
+dbau1550 mips mips dbau1x00 - - dbau1x00:DBAU1550
+dbau1550_el mips mips dbau1x00 - - dbau1x00:DBAU1550
+gth2 mips mips
+incaip mips mips
+incaip_100MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=100000000
+incaip_133MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=133000000
+incaip_150MHz mips mips incaip - - incaip:CPU_CLOCK_RATE=150000000
+pb1000 mips mips pb1x00 - - pb1x00:PB1000
purple mips mips
+qemu_mips mips mips qemu-mips - - qemu-mips
tb0229 mips mips
+vct_premium mips mips vct micronas - vct:VCT_PREMIUM
+vct_premium_small mips mips vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE
+vct_premium_onenand mips mips vct micronas - vct:VCT_PREMIUM,VCT_ONENAND
+vct_premium_onenand_small mips mips vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
+vct_platinum mips mips vct micronas - vct:VCT_PLATINUM
+vct_platinum_small mips mips vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE
+vct_platinum_onenand mips mips vct micronas - vct:VCT_PLATINUM,VCT_ONENAND
+vct_platinum_onenand_small mips mips vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE
+vct_platinumavc mips mips vct micronas - vct:VCT_PLATINUMAVC
+vct_platinumavc_small mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
+vct_platinumavc_onenand mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
+vct_platinumavc_onenand_small mips mips vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
@@ -480,26 +508,26 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
-P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011
-P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND
-P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD
-P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SPIFLASH
+P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
+P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND
+P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD
+P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH
P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB
P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
-P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH
+P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds freescale
-P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
-P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
-P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD
-P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SPIFLASH
+P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
+P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND
+P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD
+P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH
P2020DS powerpc mpc85xx p2020ds freescale
P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
-P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020
-P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
-P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
-P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH
+P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB
+P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
+P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
+P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
P4080DS powerpc mpc85xx corenet_ds freescale
mpq101 powerpc mpc85xx mpq101 mercury - mpq101
stxgp3 powerpc mpc85xx stxgp3 stx
@@ -717,6 +745,7 @@ VOM405 powerpc ppc4xx vom405 esd
WUH405 powerpc ppc4xx wuh405 esd
devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER
dlvision powerpc ppc4xx - gdsys
+dlvision-10g powerpc ppc4xx 405ep gdsys
gdppc440etx powerpc ppc4xx - gdsys
intip powerpc ppc4xx intip gdsys - intip:INTIB
io powerpc ppc4xx 405ep gdsys
@@ -750,6 +779,7 @@ ms7750se sh sh4 ms7750se -
ap325rxa sh sh4 ap325rxa renesas -
r2dplus sh sh4 r2dplus renesas -
r7780mp sh sh4 r7780mp renesas -
+sh7757lcr sh sh4 sh7757lcr renesas -
sh7763rdp sh sh4 sh7763rdp renesas -
sh7785lcr sh sh4 sh7785lcr renesas -
sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index f2a48f751..23fc82fe4 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -79,7 +79,7 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp)
return NULL;
}
- puts("Gzipped BMP image detected!\n");
+ debug("Gzipped BMP image detected!\n");
return bmp;
}
diff --git a/common/cmd_flash.c b/common/cmd_flash.c
index 4493948ec..bd49b796c 100644
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -459,15 +459,15 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
flash_info_t *info;
ulong bank;
int i, n, sect_first, sect_last;
-#endif /* CONFIG_SYS_NO_FLASH */
-#if !defined(CONFIG_SYS_NO_FLASH) || defined(CONFIG_HAS_DATAFLASH)
- ulong addr_first, addr_last;
-#endif
#if defined(CONFIG_CMD_MTDPARTS)
struct mtd_device *dev;
struct part_info *part;
u8 dev_type, dev_num, pnum;
#endif
+#endif /* CONFIG_SYS_NO_FLASH */
+#if !defined(CONFIG_SYS_NO_FLASH) || defined(CONFIG_HAS_DATAFLASH)
+ ulong addr_first, addr_last;
+#endif
#ifdef CONFIG_HAS_DATAFLASH
int status;
#endif
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index df7bdf56e..a1f7e5715 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -811,7 +811,8 @@ set_pcmcia_timing (int pmode)
/* We only need to swap data if we are running on a big endian cpu. */
/* But Au1x00 cpu:s already swaps data in big endian mode! */
-#if defined(__LITTLE_ENDIAN) || ( defined(CONFIG_AU1X00) && !defined(CONFIG_GTH2) )
+#if defined(__LITTLE_ENDIAN) || \
+ (defined(CONFIG_SOC_AU1X00) && !defined(CONFIG_GTH2))
#define input_swap_data(x,y,z) input_data(x,y,z)
#else
static void
diff --git a/common/cmd_itest.c b/common/cmd_itest.c
index fa6a0c301..2a238a43e 100644
--- a/common/cmd_itest.c
+++ b/common/cmd_itest.c
@@ -94,16 +94,13 @@ static char * evalstr(char *s)
static int stringcomp(char *s, char *t, int op)
{
- int n, p;
+ int p;
char *l, *r;
l = evalstr(s);
r = evalstr(t);
- /* we'll do a compare based on the length of the shortest string */
- n = min(strlen(l), strlen(r));
-
- p = strncmp(l, r, n);
+ p = strcmp(l, r);
switch (op) {
case EQ: return (p == 0);
case NE: return (p != 0);
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index ccf420a13..4b524cfc1 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -1212,6 +1212,7 @@ int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long src, dst;
unsigned long src_len = ~0UL, dst_len = ~0UL;
+ char buf[32];
switch (argc) {
case 4:
@@ -1225,7 +1226,14 @@ int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return cmd_usage(cmdtp);
}
- return !!gunzip((void *) dst, dst_len, (void *) src, &src_len);
+ if (gunzip((void *) dst, dst_len, (void *) src, &src_len) != 0)
+ return 1;
+
+ printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len);
+ sprintf(buf, "%lX", src_len);
+ setenv("filesize", buf);
+
+ return 0;
}
#endif /* CONFIG_CMD_UNZIP */
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index b04a8df76..b5731a7bb 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -34,6 +34,9 @@
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
#endif
+#ifdef CONFIG_USB_HOST_ETHER
+static int usb_ether_curr_dev = -1; /* current ethernet device */
+#endif
/* some display routines (info command) */
char *usb_get_class_desc(unsigned char dclass)
@@ -522,11 +525,16 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
usb_stop();
printf("(Re)start USB...\n");
i = usb_init();
+ if (i >= 0) {
#ifdef CONFIG_USB_STORAGE
- /* try to recognize storage devices immediately */
- if (i >= 0)
+ /* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
#endif
+#ifdef CONFIG_USB_HOST_ETHER
+ /* try to recognize ethernet devices immediately */
+ usb_ether_curr_dev = usb_host_eth_scan(1);
+#endif
+ }
return 0;
}
if (strncmp(argv[1], "stop", 4) == 0) {
diff --git a/common/env_nand.c b/common/env_nand.c
index 2682f07fd..980425a8e 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -181,7 +181,10 @@ int writeenv(size_t offset, u_char *buf)
return 0;
}
+
#ifdef CONFIG_ENV_OFFSET_REDUND
+static unsigned char env_flags;
+
int saveenv(void)
{
env_t env_new;
@@ -205,7 +208,7 @@ int saveenv(void)
return 1;
}
env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- env_new.flags = ACTIVE_FLAG;
+ env_new.flags = ++env_flags; /* increase the serial */
if(gd->env_valid == 1) {
puts("Erasing redundant NAND...\n");
@@ -399,6 +402,7 @@ void env_relocate_spec(void)
else
ep = tmp_env2;
+ env_flags = ep->flags;
env_import((char *)ep, 0);
free(tmp_env1);
diff --git a/common/serial.c b/common/serial.c
index 051ae4e1d..8ebf9a5d2 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
#elif defined(CONFIG_4xx) \
|| defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
|| defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
- || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520)
+ || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \
+ || defined(CONFIG_TEGRA2)
#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
diff --git a/common/usb.c b/common/usb.c
index 10e23de6a..4f7c520b3 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -55,7 +55,10 @@
#include <asm/4xx_pci.h>
#endif
-#undef USB_DEBUG
+#ifdef DEBUG
+#define USB_DEBUG
+#define USB_HUB_DEBUG
+#endif
#ifdef USB_DEBUG
#define USB_PRINTF(fmt, args...) printf(fmt , ##args)
@@ -142,10 +145,14 @@ int usb_stop(void)
/*
* disables the asynch behaviour of the control message. This is used for data
* transfers that uses the exclusiv access to the control and bulk messages.
+ * Returns the old value so it can be restored later.
*/
-void usb_disable_asynch(int disable)
+int usb_disable_asynch(int disable)
{
+ int old_value = asynch_allowed;
+
asynch_allowed = !disable;
+ return old_value;
}
@@ -960,8 +967,6 @@ void usb_scan_devices(void)
* Probes device for being a hub and configurate it
*/
-#undef USB_HUB_DEBUG
-
#ifdef USB_HUB_DEBUG
#define USB_HUB_PRINTF(fmt, args...) printf(fmt , ##args)
#else
@@ -1220,7 +1225,7 @@ int usb_hub_configure(struct usb_device *dev)
hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i];
+ hub->desc.PortPowerCtrlMask[i] = descriptor->PortPowerCtrlMask[i];
dev->maxchild = descriptor->bNbrPorts;
USB_HUB_PRINTF("%d ports detected\n", dev->maxchild);
diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr
new file mode 100644
index 000000000..cae14e055
--- /dev/null
+++ b/doc/README.sh7757lcr
@@ -0,0 +1,64 @@
+========================================
+Renesas R0P7757LC0030RL board
+========================================
+
+This board specification:
+=========================
+
+The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
+
+ - SH7757 (SH-4A)
+ - DDR3-SDRAM 256MB (with ECC)
+ - SPI ROM 8MB
+ - 2D Graphic controller
+ - Ethernet controller
+
+
+configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7785lcr_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - sh_g200
+ - write_mac
+
+
+1. sh_g200
+
+If we run this command, SH4 can control the G200.
+The default setting is that SH4 cannot control the G200.
+
+
+2. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+ write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
+
+ For example)
+ => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
+ *) We have to input the command as a single line
+ (without carriage return)
+ *) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+ write_mac
+
+ For example)
+ => write_mac
+ ETHERC ch0 = 00:00:87:6c:21:80
+ ETHERC ch1 = 00:00:87:6c:21:81
+ GETHERC ch0 = 00:00:87:6c:21:82
+ GETHERC ch1 = 00:00:87:6c:21:83
+
diff --git a/doc/README.usb b/doc/README.usb
index b3bcb91f4..9aa4f62dd 100644
--- a/doc/README.usb
+++ b/doc/README.usb
@@ -28,7 +28,8 @@ USB Support for PIP405 and MIP405 (UHCI)
The USB support is implemented on the base of the UHCI Host
controller.
-Currently supported are USB Hubs, USB Keyboards and USB Floppys.
+Currently supported are USB Hubs, USB Keyboards, USB Floppys, USB
+flash sticks and USB network adaptors.
Tested with a TEAC Floppy TEAC FD-05PUB and Chicony KU-8933 Keyboard.
How it works:
@@ -78,3 +79,4 @@ CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined
if using CONFIG_CMD_USB
CONFIG_USB_KEYBOARD enables the USB Keyboard
CONFIG_USB_STORAGE enables the USB storage devices
+CONFIG_USB_HOST_ETHER enables USB ethernet dongle support
diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
index 5646ed437..e7830c690 100644
--- a/drivers/gpio/mvmfp.c
+++ b/drivers/gpio/mvmfp.c
@@ -28,6 +28,8 @@
#include <asm/arch/mfp.h>
#ifdef CONFIG_ARMADA100
#include <asm/arch/armada100.h>
+#elif defined(CONFIG_PANTHEON)
+#include <asm/arch/pantheon.h>
#else
#error Unsupported SoC...
#endif
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d01c926c4..f3cccbe9b 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -219,6 +219,11 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
if (timeout < 0)
timeout = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ timeout++;
+#endif
+
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
index ab5eec772..7a85314eb 100644
--- a/drivers/net/ne2000.c
+++ b/drivers/net/ne2000.c
@@ -164,7 +164,8 @@ static hw_info_t hw_info[] = {
{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
{ /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 },
- { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 }
+ { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 },
+ { /* RTL8019AS */ 0x0, 0x0, 0x18, 0x5f, 0 }
};
#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 86cc324e9..53d918d38 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -36,6 +36,12 @@
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
+#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define flush_cache_wback(addr, len) \
+ dcache_wback_range((u32)addr, (u32)(addr + len - 1))
+#else
+#define flush_cache_wback(...)
+#endif
#define SH_ETH_PHY_DELAY 50000
@@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
}
/* Update tx descriptor */
+ flush_cache_wback(packet, len);
port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
port_info->tx_desc_cur->td1 = len << 16;
/* Must preserve the end of descriptor list indication */
@@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
~(TX_DESC_SIZE - 1));
+ flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
port_info->tx_desc_cur = port_info->tx_desc_base;
@@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
~(RX_DESC_SIZE - 1));
+ flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index ac4eb6aec..59f676534 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -31,6 +31,12 @@
#include <command.h>
#include <rtc.h>
+#ifdef __I386__
+#include <asm/io.h>
+#define in8(p) inb(p)
+#define out8(p, v) outb(v, p)
+#endif
+
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg);
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7d221fc40..5a6011e90 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -55,6 +55,7 @@ COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
COBJS := $(sort $(COBJS-y))
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index cd3439ee6..4032dfde7 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -33,6 +33,8 @@
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_ARMADA100)
#include <asm/arch/armada100.h>
+#elif defined(CONFIG_PANTHEON)
+#include <asm/arch/pantheon.h>
#endif
#if defined (CONFIG_SERIAL_MULTI)
diff --git a/drivers/serial/serial_tegra2.c b/drivers/serial/serial_tegra2.c
new file mode 100644
index 000000000..8ff34ea1b
--- /dev/null
+++ b/drivers/serial/serial_tegra2.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include "serial_tegra2.h"
+
+static void setup_uart(struct uart_ctlr *u)
+{
+ u32 reg;
+
+ /* Prepare the divisor value */
+ reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
+
+ /* Set up UART parameters */
+ writel(UART_LCR_DLAB, &u->uart_lcr);
+ writel(reg, &u->uart_thr_dlab_0);
+ writel(0, &u->uart_ier_dlab_0);
+ writel(0, &u->uart_lcr); /* clear DLAB */
+ writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
+ UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
+ writel(0, &u->uart_ier_dlab_0);
+ writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */
+ writel(UART_MCR_RTS, &u->uart_mcr);
+ writel(0, &u->uart_msr);
+ writel(0, &u->uart_spr);
+ writel(0, &u->uart_irda_csr);
+ writel(0, &u->uart_asr);
+ writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
+
+ /* Flush any old characters out of the RX FIFO */
+ reg = readl(&u->uart_lsr);
+
+ while (reg & UART_LSR_DR) {
+ reg = readl(&u->uart_thr_dlab_0);
+ reg = readl(&u->uart_lsr);
+ }
+}
+
+/*
+ * Routine: uart_init
+ * Description: init the UART clocks, muxes, and baudrate/parity/etc.
+ */
+void uart_init(void)
+{
+ struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE;
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
+ uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+ setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
+}
diff --git a/drivers/serial/serial_tegra2.h b/drivers/serial/serial_tegra2.h
new file mode 100644
index 000000000..5704800e3
--- /dev/null
+++ b/drivers/serial/serial_tegra2.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SERIAL_TEGRA_H_
+#define _SERIAL_TEGRA_H_
+
+#include <asm/arch/uart.h>
+
+#endif /* _SERIAL_TEGRA_H_ */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e34a12423..d582fbbb1 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
+COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index 918b22356..138d6f4b4 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -70,6 +70,11 @@ void spi_init(void)
{
}
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ /* altera spi core does not support programmable speed */
+}
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
new file mode 100644
index 000000000..ba43bec8b
--- /dev/null
+++ b/drivers/spi/sh_spi.c
@@ -0,0 +1,261 @@
+/*
+ * SH SPI driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include "sh_spi.h"
+
+static void sh_spi_write(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned long sh_spi_read(unsigned long *reg)
+{
+ return readl(reg);
+}
+
+static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(reg);
+ tmp |= val;
+ sh_spi_write(tmp, reg);
+}
+
+static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
+{
+ unsigned long tmp;
+
+ tmp = sh_spi_read(reg);
+ tmp &= ~val;
+ sh_spi_write(tmp, reg);
+}
+
+static void clear_fifo(struct sh_spi *ss)
+{
+ sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
+ sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
+}
+
+static int recvbuf_wait(struct sh_spi *ss)
+{
+ while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+static int write_fifo_empty_wait(struct sh_spi *ss)
+{
+ while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+ return 0;
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_spi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = malloc(sizeof(struct spi_slave));
+ if (!ss)
+ return NULL;
+
+ ss->slave.bus = bus;
+ ss->slave.cs = cs;
+ ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
+
+ /* SPI sycle stop */
+ sh_spi_write(0xfe, &ss->regs->cr1);
+ /* CR1 init */
+ sh_spi_write(0x00, &ss->regs->cr1);
+ /* CR3 init */
+ sh_spi_write(0x00, &ss->regs->cr3);
+
+ clear_fifo(ss);
+
+ /* 1/8 clock */
+ sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
+ udelay(10);
+
+ return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct sh_spi *spi = to_sh_spi(slave);
+
+ free(spi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct sh_spi *ss = to_sh_spi(slave);
+
+ sh_spi_write(sh_spi_read(&ss->regs->cr1) &
+ ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
+}
+
+static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
+ unsigned int len, unsigned long flags)
+{
+ int i, cur_len, ret = 0;
+ int remain = (int)len;
+ unsigned long tmp;
+
+ if (len >= SH_SPI_FIFO_SIZE)
+ sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
+
+ while (remain > 0) {
+ cur_len = (remain < SH_SPI_FIFO_SIZE) ?
+ remain : SH_SPI_FIFO_SIZE;
+ for (i = 0; i < cur_len &&
+ !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
+ !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
+ i++)
+ sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
+
+ cur_len = i;
+
+ if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
+ /* Abort the transaction */
+ flags |= SPI_XFER_END;
+ sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
+ ret = 1;
+ break;
+ }
+
+ remain -= cur_len;
+ tx_data += cur_len;
+
+ if (remain > 0)
+ write_fifo_empty_wait(ss);
+ }
+
+ if (flags & SPI_XFER_END) {
+ tmp = sh_spi_read(&ss->regs->cr1);
+ tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
+ sh_spi_write(tmp, &ss->regs->cr1);
+ sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
+ udelay(100);
+ write_fifo_empty_wait(ss);
+ }
+
+ return ret;
+}
+
+static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
+ unsigned int len, unsigned long flags)
+{
+ int i;
+ unsigned long tmp;
+
+ if (len > SH_SPI_MAX_BYTE)
+ sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
+ else
+ sh_spi_write(len, &ss->regs->cr3);
+
+ tmp = sh_spi_read(&ss->regs->cr1);
+ tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB);
+ sh_spi_write(tmp, &ss->regs->cr1);
+ sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
+
+ for (i = 0; i < len; i++) {
+ if (recvbuf_wait(ss))
+ return 0;
+
+ rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
+ }
+ sh_spi_write(0, &ss->regs->cr3);
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct sh_spi *ss = to_sh_spi(slave);
+ const unsigned char *tx_data = dout;
+ unsigned char *rx_data = din;
+ unsigned int len = bitlen / 8;
+ int ret = 0;
+
+ if (flags & SPI_XFER_BEGIN)
+ sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
+ &ss->regs->cr1);
+
+ if (tx_data)
+ ret = sh_spi_send(ss, tx_data, len, flags);
+
+ if (ret == 0 && rx_data)
+ ret = sh_spi_receive(ss, rx_data, len, flags);
+
+ if (flags & SPI_XFER_END) {
+ sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
+ udelay(100);
+
+ sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
+ &ss->regs->cr1);
+ clear_fifo(ss);
+ }
+
+ return ret;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* This driver supports "bus = 0" and "cs = 0" only. */
+ if (!bus && !cs)
+ return 1;
+ else
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+
+}
+
diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h
new file mode 100644
index 000000000..b1cf98cc3
--- /dev/null
+++ b/drivers/spi/sh_spi.h
@@ -0,0 +1,79 @@
+/*
+ * SH SPI driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#ifndef __SH_SPI_H__
+#define __SH_SPI_H__
+
+#include <spi.h>
+
+struct sh_spi_regs {
+ unsigned long tbr_rbr;
+ unsigned long resv1;
+ unsigned long cr1;
+ unsigned long resv2;
+ unsigned long cr2;
+ unsigned long resv3;
+ unsigned long cr3;
+ unsigned long resv4;
+ unsigned long cr4;
+};
+
+/* CR1 */
+#define SH_SPI_TBE 0x80
+#define SH_SPI_TBF 0x40
+#define SH_SPI_RBE 0x20
+#define SH_SPI_RBF 0x10
+#define SH_SPI_PFONRD 0x08
+#define SH_SPI_SSDB 0x04
+#define SH_SPI_SSD 0x02
+#define SH_SPI_SSA 0x01
+
+/* CR2 */
+#define SH_SPI_RSTF 0x80
+#define SH_SPI_LOOPBK 0x40
+#define SH_SPI_CPOL 0x20
+#define SH_SPI_CPHA 0x10
+#define SH_SPI_L1M0 0x08
+
+/* CR3 */
+#define SH_SPI_MAX_BYTE 0xFF
+
+/* CR4 */
+#define SH_SPI_TBEI 0x80
+#define SH_SPI_TBFI 0x40
+#define SH_SPI_RBEI 0x20
+#define SH_SPI_RBFI 0x10
+#define SH_SPI_WPABRT 0x04
+#define SH_SPI_SSS 0x01
+
+#define SH_SPI_FIFO_SIZE 32
+
+struct sh_spi {
+ struct spi_slave slave;
+ struct sh_spi_regs *regs;
+};
+
+static inline struct sh_spi *to_sh_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct sh_spi, slave);
+}
+
+#endif
+
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
new file mode 100644
index 000000000..6a5f25a38
--- /dev/null
+++ b/drivers/usb/eth/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libusb_eth.a
+
+# new USB host ethernet layer dependencies
+COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
+ifdef CONFIG_USB_ETHER_ASIX
+COBJS-y += asix.o
+endif
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
new file mode 100644
index 000000000..9b012e4a6
--- /dev/null
+++ b/drivers/usb/eth/asix.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <linux/mii.h>
+#include "usb_ether.h"
+
+
+/* ASIX AX8817X based USB 2.0 Ethernet Devices */
+
+#define AX_CMD_SET_SW_MII 0x06
+#define AX_CMD_READ_MII_REG 0x07
+#define AX_CMD_WRITE_MII_REG 0x08
+#define AX_CMD_SET_HW_MII 0x0a
+#define AX_CMD_READ_RX_CTL 0x0f
+#define AX_CMD_WRITE_RX_CTL 0x10
+#define AX_CMD_WRITE_IPG0 0x12
+#define AX_CMD_READ_NODE_ID 0x13
+#define AX_CMD_READ_PHY_ID 0x19
+#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
+#define AX_CMD_WRITE_GPIOS 0x1f
+#define AX_CMD_SW_RESET 0x20
+#define AX_CMD_SW_PHY_SELECT 0x22
+
+#define AX_SWRESET_CLEAR 0x00
+#define AX_SWRESET_PRTE 0x04
+#define AX_SWRESET_PRL 0x08
+#define AX_SWRESET_IPRL 0x20
+#define AX_SWRESET_IPPD 0x40
+
+#define AX88772_IPG0_DEFAULT 0x15
+#define AX88772_IPG1_DEFAULT 0x0c
+#define AX88772_IPG2_DEFAULT 0x12
+
+/* AX88772 & AX88178 Medium Mode Register */
+#define AX_MEDIUM_PF 0x0080
+#define AX_MEDIUM_JFE 0x0040
+#define AX_MEDIUM_TFC 0x0020
+#define AX_MEDIUM_RFC 0x0010
+#define AX_MEDIUM_ENCK 0x0008
+#define AX_MEDIUM_AC 0x0004
+#define AX_MEDIUM_FD 0x0002
+#define AX_MEDIUM_GM 0x0001
+#define AX_MEDIUM_SM 0x1000
+#define AX_MEDIUM_SBP 0x0800
+#define AX_MEDIUM_PS 0x0200
+#define AX_MEDIUM_RE 0x0100
+
+#define AX88178_MEDIUM_DEFAULT \
+ (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
+ AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
+ AX_MEDIUM_RE)
+
+#define AX88772_MEDIUM_DEFAULT \
+ (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
+ AX_MEDIUM_TFC | AX_MEDIUM_PS | \
+ AX_MEDIUM_AC | AX_MEDIUM_RE)
+
+/* AX88772 & AX88178 RX_CTL values */
+#define AX_RX_CTL_SO 0x0080
+#define AX_RX_CTL_AB 0x0008
+
+#define AX_DEFAULT_RX_CTL \
+ (AX_RX_CTL_SO | AX_RX_CTL_AB)
+
+/* GPIO 2 toggles */
+#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
+#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
+#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
+
+/* local defines */
+#define ASIX_BASE_NAME "asx"
+#define USB_CTRL_SET_TIMEOUT 5000
+#define USB_CTRL_GET_TIMEOUT 5000
+#define USB_BULK_SEND_TIMEOUT 5000
+#define USB_BULK_RECV_TIMEOUT 5000
+
+#define AX_RX_URB_SIZE 2048
+#define PHY_CONNECT_TIMEOUT 5000
+
+/* local vars */
+static int curr_eth_dev; /* index for name of next device detected */
+
+/*
+ * Asix infrastructure commands
+ */
+static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
+ u16 size, void *data)
+{
+ int len;
+
+ debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
+ "size=%d\n", cmd, value, index, size);
+
+ len = usb_control_msg(
+ dev->pusb_dev,
+ usb_sndctrlpipe(dev->pusb_dev, 0),
+ cmd,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ value,
+ index,
+ data,
+ size,
+ USB_CTRL_SET_TIMEOUT);
+
+ return len == size ? 0 : -1;
+}
+
+static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
+ u16 size, void *data)
+{
+ int len;
+
+ debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
+ cmd, value, index, size);
+
+ len = usb_control_msg(
+ dev->pusb_dev,
+ usb_rcvctrlpipe(dev->pusb_dev, 0),
+ cmd,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ value,
+ index,
+ data,
+ size,
+ USB_CTRL_GET_TIMEOUT);
+ return len == size ? 0 : -1;
+}
+
+static inline int asix_set_sw_mii(struct ueth_data *dev)
+{
+ int ret;
+
+ ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
+ if (ret < 0)
+ debug("Failed to enable software MII access\n");
+ return ret;
+}
+
+static inline int asix_set_hw_mii(struct ueth_data *dev)
+{
+ int ret;
+
+ ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
+ if (ret < 0)
+ debug("Failed to enable hardware MII access\n");
+ return ret;
+}
+
+static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
+{
+ __le16 res;
+
+ asix_set_sw_mii(dev);
+ asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res);
+ asix_set_hw_mii(dev);
+
+ debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
+ phy_id, loc, le16_to_cpu(res));
+
+ return le16_to_cpu(res);
+}
+
+static void
+asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
+{
+ __le16 res = cpu_to_le16(val);
+
+ debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
+ phy_id, loc, val);
+ asix_set_sw_mii(dev);
+ asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
+ asix_set_hw_mii(dev);
+}
+
+/*
+ * Asix "high level" commands
+ */
+static int asix_sw_reset(struct ueth_data *dev, u8 flags)
+{
+ int ret;
+
+ ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
+ if (ret < 0)
+ debug("Failed to send software reset: %02x\n", ret);
+ else
+ udelay(150 * 1000);
+
+ return ret;
+}
+
+static inline int asix_get_phy_addr(struct ueth_data *dev)
+{
+ u8 buf[2];
+ int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
+
+ debug("asix_get_phy_addr()\n");
+
+ if (ret < 0) {
+ debug("Error reading PHYID register: %02x\n", ret);
+ goto out;
+ }
+ debug("asix_get_phy_addr() returning 0x%04x\n", *((__le16 *)buf));
+ ret = buf[1];
+
+out:
+ return ret;
+}
+
+static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
+{
+ int ret;
+
+ debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
+ ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
+ 0, 0, NULL);
+ if (ret < 0) {
+ debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
+ mode, ret);
+ }
+ return ret;
+}
+
+static u16 asix_read_rx_ctl(struct ueth_data *dev)
+{
+ __le16 v;
+ int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
+
+ if (ret < 0)
+ debug("Error reading RX_CTL register: %02x\n", ret);
+ else
+ ret = le16_to_cpu(v);
+ return ret;
+}
+
+static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
+{
+ int ret;
+
+ debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
+ ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
+ if (ret < 0) {
+ debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
+ mode, ret);
+ }
+ return ret;
+}
+
+static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
+{
+ int ret;
+
+ debug("asix_write_gpio() - value = 0x%04x\n", value);
+ ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
+ if (ret < 0) {
+ debug("Failed to write GPIO value 0x%04x: %02x\n",
+ value, ret);
+ }
+ if (sleep)
+ udelay(sleep * 1000);
+
+ return ret;
+}
+
+/*
+ * mii commands
+ */
+
+/*
+ * mii_nway_restart - restart NWay (autonegotiation) for this interface
+ *
+ * Returns 0 on success, negative on error.
+ */
+static int mii_nway_restart(struct ueth_data *dev)
+{
+ int bmcr;
+ int r = -1;
+
+ /* if autoneg is off, it's an error */
+ bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
+
+ if (bmcr & BMCR_ANENABLE) {
+ bmcr |= BMCR_ANRESTART;
+ asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
+ r = 0;
+ }
+
+ return r;
+}
+
+/*
+ * Asix callbacks
+ */
+static int asix_init(struct eth_device *eth, bd_t *bd)
+{
+ int embd_phy;
+ unsigned char buf[ETH_ALEN];
+ u16 rx_ctl;
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ int timeout = 0;
+#define TIMEOUT_RESOLUTION 50 /* ms */
+ int link_detected;
+
+ debug("** %s()\n", __func__);
+
+ if (asix_write_gpio(dev,
+ AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
+ goto out_err;
+
+ /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
+ embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
+ if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
+ embd_phy, 0, 0, NULL) < 0) {
+ debug("Select PHY #1 failed\n");
+ goto out_err;
+ }
+
+ if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
+ goto out_err;
+
+ if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
+ goto out_err;
+
+ if (embd_phy) {
+ if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
+ goto out_err;
+ } else {
+ if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
+ goto out_err;
+ }
+
+ rx_ctl = asix_read_rx_ctl(dev);
+ debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
+ if (asix_write_rx_ctl(dev, 0x0000) < 0)
+ goto out_err;
+
+ rx_ctl = asix_read_rx_ctl(dev);
+ debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
+
+ /* Get the MAC address */
+ if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
+ 0, 0, ETH_ALEN, buf) < 0) {
+ debug("Failed to read MAC address.\n");
+ goto out_err;
+ }
+ memcpy(eth->enetaddr, buf, ETH_ALEN);
+ debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ eth->enetaddr[0], eth->enetaddr[1],
+ eth->enetaddr[2], eth->enetaddr[3],
+ eth->enetaddr[4], eth->enetaddr[5]);
+
+ dev->phy_id = asix_get_phy_addr(dev);
+ if (dev->phy_id < 0)
+ debug("Failed to read phy id\n");
+
+ if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
+ goto out_err;
+
+ if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
+ goto out_err;
+
+ asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
+ asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_CSMA);
+ mii_nway_restart(dev);
+
+ if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
+ goto out_err;
+
+ if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
+ AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
+ AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
+ debug("Write IPG,IPG1,IPG2 failed\n");
+ goto out_err;
+ }
+
+ if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
+ goto out_err;
+
+ do {
+ link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
+ BMSR_LSTATUS;
+ if (!link_detected) {
+ if (timeout == 0)
+ printf("Waiting for Ethernet connection... ");
+ udelay(TIMEOUT_RESOLUTION * 1000);
+ timeout += TIMEOUT_RESOLUTION;
+ }
+ } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
+ if (link_detected) {
+ if (timeout != 0)
+ printf("done.\n");
+ } else {
+ printf("unable to connect.\n");
+ goto out_err;
+ }
+
+ return 0;
+out_err:
+ return -1;
+}
+
+static int asix_send(struct eth_device *eth, volatile void *packet, int length)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ int err;
+ u32 packet_len;
+ int actual_len;
+ unsigned char msg[PKTSIZE + sizeof(packet_len)];
+
+ debug("** %s(), len %d\n", __func__, length);
+
+ packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
+ cpu_to_le32s(&packet_len);
+
+ memcpy(msg, &packet_len, sizeof(packet_len));
+ memcpy(msg + sizeof(packet_len), (void *)packet, length);
+ if (length & 1)
+ length++;
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ (void *)msg,
+ length + sizeof(packet_len),
+ &actual_len,
+ USB_BULK_SEND_TIMEOUT);
+ debug("Tx: len = %u, actual = %u, err = %d\n",
+ length + sizeof(packet_len), actual_len, err);
+
+ return err;
+}
+
+static int asix_recv(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ static unsigned char recv_buf[AX_RX_URB_SIZE];
+ unsigned char *buf_ptr;
+ int err;
+ int actual_len;
+ u32 packet_len;
+
+ debug("** %s()\n", __func__);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ (void *)recv_buf,
+ AX_RX_URB_SIZE,
+ &actual_len,
+ USB_BULK_RECV_TIMEOUT);
+ debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
+ actual_len, err);
+ if (err != 0) {
+ debug("Rx: failed to receive\n");
+ return -1;
+ }
+ if (actual_len > AX_RX_URB_SIZE) {
+ debug("Rx: received too many bytes %d\n", actual_len);
+ return -1;
+ }
+
+ buf_ptr = recv_buf;
+ while (actual_len > 0) {
+ /*
+ * 1st 4 bytes contain the length of the actual data as two
+ * complementary 16-bit words. Extract the length of the data.
+ */
+ if (actual_len < sizeof(packet_len)) {
+ debug("Rx: incomplete packet length\n");
+ return -1;
+ }
+ memcpy(&packet_len, buf_ptr, sizeof(packet_len));
+ le32_to_cpus(&packet_len);
+ if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) {
+ debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
+ packet_len, (packet_len >> 16) ^ 0xffff,
+ packet_len & 0xffff);
+ return -1;
+ }
+ packet_len = packet_len & 0xffff;
+ if (packet_len > actual_len - sizeof(packet_len)) {
+ debug("Rx: too large packet: %d\n", packet_len);
+ return -1;
+ }
+
+ /* Notify net stack */
+ NetReceive(buf_ptr + sizeof(packet_len), packet_len);
+
+ /* Adjust for next iteration. Packets are padded to 16-bits */
+ if (packet_len & 1)
+ packet_len++;
+ actual_len -= sizeof(packet_len) + packet_len;
+ buf_ptr += sizeof(packet_len) + packet_len;
+ }
+
+ return err;
+}
+
+static void asix_halt(struct eth_device *eth)
+{
+ debug("** %s()\n", __func__);
+}
+
+/*
+ * Asix probing functions
+ */
+void asix_eth_before_probe(void)
+{
+ curr_eth_dev = 0;
+}
+
+struct asix_dongle {
+ unsigned short vendor;
+ unsigned short product;
+};
+
+static struct asix_dongle asix_dongles[] = {
+ { 0x05ac, 0x1402 }, /* Apple USB Ethernet Adapter */
+ { 0x07d1, 0x3c05 }, /* D-Link DUB-E100 H/W Ver B1 */
+ { 0x0b95, 0x772a }, /* Cables-to-Go USB Ethernet Adapter */
+ { 0x0b95, 0x7720 }, /* Trendnet TU2-ET100 V3.0R */
+ { 0x0b95, 0x1720 }, /* SMC */
+ { 0x0db0, 0xa877 }, /* MSI - ASIX 88772a */
+ { 0x13b1, 0x0018 }, /* Linksys 200M v2.1 */
+ { 0x1557, 0x7720 }, /* 0Q0 cable ethernet */
+ { 0x2001, 0x3c05 }, /* DLink DUB-E100 H/W Ver B1 Alternate */
+ { 0x0000, 0x0000 } /* END - Do not remove */
+};
+
+/* Probe to see if a new device is actually an asix device */
+int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss)
+{
+ struct usb_interface *iface;
+ struct usb_interface_descriptor *iface_desc;
+ int i;
+
+ /* let's examine the device now */
+ iface = &dev->config.if_desc[ifnum];
+ iface_desc = &dev->config.if_desc[ifnum].desc;
+
+ for (i = 0; asix_dongles[i].vendor != 0; i++) {
+ if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
+ dev->descriptor.idProduct == asix_dongles[i].product)
+ /* Found a supported dongle */
+ break;
+ }
+
+ if (asix_dongles[i].vendor == 0)
+ return 0;
+
+ memset(ss, 0, sizeof(struct ueth_data));
+
+ /* At this point, we know we've got a live one */
+ debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+ /* Initialize the ueth_data structure with some useful info */
+ ss->ifnum = ifnum;
+ ss->pusb_dev = dev;
+ ss->subclass = iface_desc->bInterfaceSubClass;
+ ss->protocol = iface_desc->bInterfaceProtocol;
+
+ /*
+ * We are expecting a minimum of 3 endpoints - in, out (bulk), and
+ * int. We will ignore any others.
+ */
+ for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+ /* is it an BULK endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
+ if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
+ ss->ep_in = iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ else
+ ss->ep_out =
+ iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ }
+
+ /* is it an interrupt endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
+ ss->ep_int = iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ ss->irqinterval = iface->ep_desc[i].bInterval;
+ }
+ }
+ debug("Endpoints In %d Out %d Int %d\n",
+ ss->ep_in, ss->ep_out, ss->ep_int);
+
+ /* Do some basic sanity checks, and bail if we find a problem */
+ if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+ !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+ debug("Problems with device\n");
+ return 0;
+ }
+ dev->privptr = (void *)ss;
+ return 1;
+}
+
+int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth)
+{
+ if (!eth) {
+ debug("%s: missing parameter.\n", __func__);
+ return 0;
+ }
+ sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
+ eth->init = asix_init;
+ eth->send = asix_send;
+ eth->recv = asix_recv;
+ eth->halt = asix_halt;
+ eth->priv = ss;
+
+ return 1;
+}
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
new file mode 100644
index 000000000..9e3d00668
--- /dev/null
+++ b/drivers/usb/eth/usb_ether.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+
+#include "usb_ether.h"
+
+typedef void (*usb_eth_before_probe)(void);
+typedef int (*usb_eth_probe)(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss);
+typedef int (*usb_eth_get_info)(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *dev_desc);
+
+struct usb_eth_prob_dev {
+ usb_eth_before_probe before_probe; /* optional */
+ usb_eth_probe probe;
+ usb_eth_get_info get_info;
+};
+
+/* driver functions go here, each bracketed by #ifdef CONFIG_USB_ETHER_xxx */
+static const struct usb_eth_prob_dev prob_dev[] = {
+#ifdef CONFIG_USB_ETHER_ASIX
+ {
+ .before_probe = asix_eth_before_probe,
+ .probe = asix_eth_probe,
+ .get_info = asix_eth_get_info,
+ },
+#endif
+ { }, /* END */
+};
+
+static int usb_max_eth_dev; /* number of highest available usb eth device */
+static struct ueth_data usb_eth[USB_MAX_ETH_DEV];
+
+/*******************************************************************************
+ * tell if current ethernet device is a usb dongle
+ */
+int is_eth_dev_on_usb_host(void)
+{
+ int i;
+ struct eth_device *dev = eth_get_dev();
+
+ if (dev) {
+ for (i = 0; i < usb_max_eth_dev; i++)
+ if (&usb_eth[i].eth_dev == dev)
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Given a USB device, ask each driver if it can support it, and attach it
+ * to the first driver that says 'yes'
+ */
+static void probe_valid_drivers(struct usb_device *dev)
+{
+ int j;
+
+ for (j = 0; prob_dev[j].probe && prob_dev[j].get_info; j++) {
+ if (!prob_dev[j].probe(dev, 0, &usb_eth[usb_max_eth_dev]))
+ continue;
+ /*
+ * ok, it is a supported eth device. Get info and fill it in
+ */
+ if (prob_dev[j].get_info(dev,
+ &usb_eth[usb_max_eth_dev],
+ &usb_eth[usb_max_eth_dev].eth_dev)) {
+ /* found proper driver */
+ /* register with networking stack */
+ usb_max_eth_dev++;
+
+ /*
+ * usb_max_eth_dev must be incremented prior to this
+ * call since eth_current_changed (internally called)
+ * relies on it
+ */
+ eth_register(&usb_eth[usb_max_eth_dev - 1].eth_dev);
+ break;
+ }
+ }
+ }
+
+/*******************************************************************************
+ * scan the usb and reports device info
+ * to the user if mode = 1
+ * returns current device or -1 if no
+ */
+int usb_host_eth_scan(int mode)
+{
+ int i, old_async;
+ struct usb_device *dev;
+
+
+ if (mode == 1)
+ printf(" scanning bus for ethernet devices... ");
+
+ old_async = usb_disable_asynch(1); /* asynch transfer not allowed */
+
+ for (i = 0; i < USB_MAX_ETH_DEV; i++)
+ memset(&usb_eth[i], 0, sizeof(usb_eth[i]));
+
+ for (i = 0; prob_dev[i].probe; i++) {
+ if (prob_dev[i].before_probe)
+ prob_dev[i].before_probe();
+ }
+
+ usb_max_eth_dev = 0;
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ dev = usb_get_dev_index(i); /* get device */
+ debug("i=%d\n", i);
+ if (dev == NULL)
+ break; /* no more devices avaiable */
+
+ /* find valid usb_ether driver for this device, if any */
+ probe_valid_drivers(dev);
+
+ /* check limit */
+ if (usb_max_eth_dev == USB_MAX_ETH_DEV) {
+ printf("max USB Ethernet Device reached: %d stopping\n",
+ usb_max_eth_dev);
+ break;
+ }
+ } /* for */
+
+ usb_disable_asynch(old_async); /* restore asynch value */
+ printf("%d Ethernet Device(s) found\n", usb_max_eth_dev);
+ if (usb_max_eth_dev > 0)
+ return 0;
+ return -1;
+}
+
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index f13781739..7d5b504c7 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libusb_gadget.o
# new USB gadget layer dependencies
ifdef CONFIG_USB_ETHER
COBJS-y += ether.o epautoconf.o config.o usbstring.o
+COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
else
# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
ifdef CONFIG_USB_DEVICE
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 638486998..9fb0e80ad 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -22,13 +22,16 @@
#include <common.h>
#include <asm/errno.h>
+#include <linux/netdevice.h>
#include <linux/usb/ch9.h>
#include <linux/usb/cdc.h>
#include <linux/usb/gadget.h>
#include <net.h>
+#include <malloc.h>
#include <linux/ctype.h>
#include "gadget_chips.h"
+#include "rndis.h"
#define USB_NET_NAME "usb_ether"
@@ -94,7 +97,13 @@ static const char driver_desc[] = DRIVER_DESC;
#define RX_EXTRA 20 /* guard against rx overflows */
-/* CDC support the same host-chosen outgoing packet filters. */
+#ifndef CONFIG_USB_ETH_RNDIS
+#define rndis_uninit(x) do {} while (0)
+#define rndis_deregister(c) do {} while (0)
+#define rndis_exit() do {} while (0)
+#endif
+
+/* CDC and RNDIS support the same host-chosen outgoing packet filters. */
#define DEFAULT_FILTER (USB_CDC_PACKET_TYPE_BROADCAST \
|USB_CDC_PACKET_TYPE_ALL_MULTICAST \
|USB_CDC_PACKET_TYPE_PROMISCUOUS \
@@ -103,6 +112,44 @@ static const char driver_desc[] = DRIVER_DESC;
#define USB_CONNECT_TIMEOUT (3 * CONFIG_SYS_HZ)
/*-------------------------------------------------------------------------*/
+
+struct eth_dev {
+ struct usb_gadget *gadget;
+ struct usb_request *req; /* for control responses */
+ struct usb_request *stat_req; /* for cdc & rndis status */
+
+ u8 config;
+ struct usb_ep *in_ep, *out_ep, *status_ep;
+ const struct usb_endpoint_descriptor
+ *in, *out, *status;
+
+ struct usb_request *tx_req, *rx_req;
+
+ struct eth_device *net;
+ struct net_device_stats stats;
+ unsigned int tx_qlen;
+
+ unsigned zlp:1;
+ unsigned cdc:1;
+ unsigned rndis:1;
+ unsigned suspended:1;
+ unsigned network_started:1;
+ u16 cdc_filter;
+ unsigned long todo;
+ int mtu;
+#define WORK_RX_MEMORY 0
+ int rndis_config;
+ u8 host_mac[ETH_ALEN];
+};
+
+/*
+ * This version autoconfigures as much as possible at run-time.
+ *
+ * It also ASSUMES a self-powered device, without remote wakeup,
+ * although remote wakeup support would make sense.
+ */
+
+/*-------------------------------------------------------------------------*/
static struct eth_dev l_ethdev;
static struct eth_device l_netdev;
static struct usb_gadget_driver eth_driver;
@@ -121,8 +168,18 @@ static inline int is_cdc(struct eth_dev *dev)
#endif
}
-#define subset_active(dev) (!is_cdc(dev))
-#define cdc_active(dev) (is_cdc(dev))
+/* "secondary" RNDIS config may sometimes be activated */
+static inline int rndis_active(struct eth_dev *dev)
+{
+#ifdef CONFIG_USB_ETH_RNDIS
+ return dev->rndis;
+#else
+ return 0;
+#endif
+}
+
+#define subset_active(dev) (!is_cdc(dev) && !rndis_active(dev))
+#define cdc_active(dev) (is_cdc(dev) && !rndis_active(dev))
#define DEFAULT_QLEN 2 /* double buffering by default */
@@ -162,39 +219,6 @@ static inline int BITRATE(struct usb_gadget *g)
}
#endif
-struct eth_dev {
- struct usb_gadget *gadget;
- struct usb_request *req; /* for control responses */
- struct usb_request *stat_req; /* for cdc status */
-
- u8 config;
- struct usb_ep *in_ep, *out_ep, *status_ep;
- const struct usb_endpoint_descriptor
- *in, *out, *status;
-
- struct usb_request *tx_req, *rx_req;
-
- struct eth_device *net;
- unsigned int tx_qlen;
-
- unsigned zlp:1;
- unsigned cdc:1;
- unsigned suspended:1;
- unsigned network_started:1;
- u16 cdc_filter;
- unsigned long todo;
- int mtu;
-#define WORK_RX_MEMORY 0
- u8 host_mac[ETH_ALEN];
-};
-
-/*
- * This version autoconfigures as much as possible at run-time.
- *
- * It also ASSUMES a self-powered device, without remote wakeup,
- * although remote wakeup support would make sense.
- */
-
/*-------------------------------------------------------------------------*/
/*
@@ -221,8 +245,17 @@ struct eth_dev {
* RNDIS (like SA-1100, with no interrupt endpoint, or anything that
* doesn't handle control-OUT).
*/
-#define SIMPLE_VENDOR_NUM 0x049f
-#define SIMPLE_PRODUCT_NUM 0x505a
+#define SIMPLE_VENDOR_NUM 0x049f /* Compaq Computer Corp. */
+#define SIMPLE_PRODUCT_NUM 0x505a /* Linux-USB "CDC Subset" Device */
+
+/*
+ * For hardware that can talk RNDIS and either of the above protocols,
+ * use this ID ... the windows INF files will know it. Unless it's
+ * used with CDC Ethernet, Linux 2.4 hosts will need updates to choose
+ * the non-RNDIS configuration.
+ */
+#define RNDIS_VENDOR_NUM 0x0525 /* NetChip */
+#define RNDIS_PRODUCT_NUM 0xa4a2 /* Ethernet/RNDIS Gadget */
/*
* Some systems will want different product identifers published in the
@@ -230,17 +263,28 @@ struct eth_dev {
* parameters are in UTF-8 (superset of ASCII's 7 bit characters).
*/
-static ushort bcdDevice;
+/*
+ * Emulating them in eth_bind:
+ * static ushort idVendor;
+ * static ushort idProduct;
+ */
+
#if defined(CONFIG_USBNET_MANUFACTURER)
static char *iManufacturer = CONFIG_USBNET_MANUFACTURER;
#else
static char *iManufacturer = "U-boot";
#endif
+
+/* These probably need to be configurable. */
+static ushort bcdDevice;
static char *iProduct;
static char *iSerialNumber;
+
static char dev_addr[18];
+
static char host_addr[18];
+
/*-------------------------------------------------------------------------*/
/*
@@ -252,7 +296,12 @@ static char host_addr[18];
/*
* DESCRIPTORS ... most are static, but strings and (full) configuration
* descriptors are built on demand. For now we do either full CDC, or
- * our simple subset.
+ * our simple subset, with RNDIS as an optional second configuration.
+ *
+ * RNDIS includes some CDC ACM descriptors ... like CDC Ethernet. But
+ * the class descriptors match a modem (they're ignored; it's really just
+ * Ethernet functionality), they don't need the NOP altsetting, and the
+ * status transfer endpoint isn't optional.
*/
#define STRING_MANUFACTURER 1
@@ -260,22 +309,28 @@ static char host_addr[18];
#define STRING_ETHADDR 3
#define STRING_DATA 4
#define STRING_CONTROL 5
+#define STRING_RNDIS_CONTROL 6
#define STRING_CDC 7
#define STRING_SUBSET 8
+#define STRING_RNDIS 9
#define STRING_SERIALNUMBER 10
-/* holds our biggest descriptor */
+/* holds our biggest descriptor (or RNDIS response) */
#define USB_BUFSIZ 256
/*
- * This device advertises one configuration, eth_config,
- * on hardware supporting at least two configs.
+ * This device advertises one configuration, eth_config, unless RNDIS
+ * is enabled (rndis_config) on hardware supporting at least two configs.
+ *
+ * NOTE: Controllers like superh_udc should probably be able to use
+ * an RNDIS-only configuration.
*
* FIXME define some higher-powered configurations to make it easier
* to recharge batteries ...
*/
#define DEV_CONFIG_VALUE 1 /* cdc or subset */
+#define DEV_RNDIS_CONFIG_VALUE 2 /* rndis; optional */
static struct usb_device_descriptor
device_desc = {
@@ -316,11 +371,38 @@ eth_config = {
.bMaxPower = 1,
};
+#ifdef CONFIG_USB_ETH_RNDIS
+static struct usb_config_descriptor
+rndis_config = {
+ .bLength = sizeof rndis_config,
+ .bDescriptorType = USB_DT_CONFIG,
+
+ /* compute wTotalLength on the fly */
+ .bNumInterfaces = 2,
+ .bConfigurationValue = DEV_RNDIS_CONFIG_VALUE,
+ .iConfiguration = STRING_RNDIS,
+ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
+ .bMaxPower = 1,
+};
+#endif
+
/*
* Compared to the simple CDC subset, the full CDC Ethernet model adds
* three class descriptors, two interface descriptors, optional status
* endpoint. Both have a "data" interface and two bulk endpoints.
* There are also differences in how control requests are handled.
+ *
+ * RNDIS shares a lot with CDC-Ethernet, since it's a variant of the
+ * CDC-ACM (modem) spec. Unfortunately MSFT's RNDIS driver is buggy; it
+ * may hang or oops. Since bugfixes (or accurate specs, letting Linux
+ * work around those bugs) are unlikely to ever come from MSFT, you may
+ * wish to avoid using RNDIS.
+ *
+ * MCCI offers an alternative to RNDIS if you need to connect to Windows
+ * but have hardware that can't support CDC Ethernet. We add descriptors
+ * to present the CDC Subset as a (nonconformant) CDC MDLM variant called
+ * "SAFE". That borrows from both CDC Ethernet and CDC MDLM. You can
+ * get those drivers from MCCI, or bundled with various products.
*/
#ifdef DEV_CONFIG_CDC
@@ -339,6 +421,21 @@ control_intf = {
};
#endif
+#ifdef CONFIG_USB_ETH_RNDIS
+static const struct usb_interface_descriptor
+rndis_control_intf = {
+ .bLength = sizeof rndis_control_intf,
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bInterfaceNumber = 0,
+ .bNumEndpoints = 1,
+ .bInterfaceClass = USB_CLASS_COMM,
+ .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM,
+ .bInterfaceProtocol = USB_CDC_ACM_PROTO_VENDOR,
+ .iInterface = STRING_RNDIS_CONTROL,
+};
+#endif
+
static const struct usb_cdc_header_desc header_desc = {
.bLength = sizeof header_desc,
.bDescriptorType = USB_DT_CS_INTERFACE,
@@ -347,7 +444,7 @@ static const struct usb_cdc_header_desc header_desc = {
.bcdCDC = __constant_cpu_to_le16(0x0110),
};
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static const struct usb_cdc_union_desc union_desc = {
.bLength = sizeof union_desc,
@@ -358,7 +455,28 @@ static const struct usb_cdc_union_desc union_desc = {
.bSlaveInterface0 = 1, /* index of DATA interface */
};
-#endif /* CDC */
+#endif /* CDC || RNDIS */
+
+#ifdef CONFIG_USB_ETH_RNDIS
+
+static const struct usb_cdc_call_mgmt_descriptor call_mgmt_descriptor = {
+ .bLength = sizeof call_mgmt_descriptor,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubType = USB_CDC_CALL_MANAGEMENT_TYPE,
+
+ .bmCapabilities = 0x00,
+ .bDataInterface = 0x01,
+};
+
+static const struct usb_cdc_acm_descriptor acm_descriptor = {
+ .bLength = sizeof acm_descriptor,
+ .bDescriptorType = USB_DT_CS_INTERFACE,
+ .bDescriptorSubType = USB_CDC_ACM_TYPE,
+
+ .bmCapabilities = 0x00,
+};
+
+#endif
#ifndef DEV_CONFIG_CDC
@@ -410,7 +528,7 @@ static const struct usb_cdc_ether_desc ether_desc = {
.bNumberPowerFilters = 0,
};
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* include the status endpoint if we can, even where it's optional.
@@ -422,6 +540,9 @@ static const struct usb_cdc_ether_desc ether_desc = {
* if they ignore the connect/disconnect notifications that real aether
* can provide. more advanced cdc configurations might want to support
* encapsulated commands (vendor-specific, using control-OUT).
+ *
+ * RNDIS requires the status endpoint, since it uses that encapsulation
+ * mechanism for its funky RPC scheme.
*/
#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
@@ -474,6 +595,26 @@ data_intf = {
#endif
+#ifdef CONFIG_USB_ETH_RNDIS
+
+/* RNDIS doesn't activate by changing to the "real" altsetting */
+
+static const struct usb_interface_descriptor
+rndis_data_intf = {
+ .bLength = sizeof rndis_data_intf,
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bInterfaceNumber = 1,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = 2,
+ .bInterfaceClass = USB_CLASS_CDC_DATA,
+ .bInterfaceSubClass = 0,
+ .bInterfaceProtocol = 0,
+ .iInterface = STRING_DATA,
+};
+
+#endif
+
#ifdef DEV_CONFIG_SUBSET
/*
@@ -554,12 +695,30 @@ static inline void fs_subset_descriptors(void)
#endif
}
+#ifdef CONFIG_USB_ETH_RNDIS
+static const struct usb_descriptor_header *fs_rndis_function[] = {
+ (struct usb_descriptor_header *) &otg_descriptor,
+ /* control interface matches ACM, not Ethernet */
+ (struct usb_descriptor_header *) &rndis_control_intf,
+ (struct usb_descriptor_header *) &header_desc,
+ (struct usb_descriptor_header *) &call_mgmt_descriptor,
+ (struct usb_descriptor_header *) &acm_descriptor,
+ (struct usb_descriptor_header *) &union_desc,
+ (struct usb_descriptor_header *) &fs_status_desc,
+ /* data interface has no altsetting */
+ (struct usb_descriptor_header *) &rndis_data_intf,
+ (struct usb_descriptor_header *) &fs_source_desc,
+ (struct usb_descriptor_header *) &fs_sink_desc,
+ NULL,
+};
+#endif
+
/*
* usb 2.0 devices need to expose both high speed and full speed
* descriptors, unless they only run at full speed.
*/
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static struct usb_endpoint_descriptor
hs_status_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
@@ -636,6 +795,25 @@ static inline void hs_subset_descriptors(void)
#endif
}
+#ifdef CONFIG_USB_ETH_RNDIS
+static const struct usb_descriptor_header *hs_rndis_function[] = {
+ (struct usb_descriptor_header *) &otg_descriptor,
+ /* control interface matches ACM, not Ethernet */
+ (struct usb_descriptor_header *) &rndis_control_intf,
+ (struct usb_descriptor_header *) &header_desc,
+ (struct usb_descriptor_header *) &call_mgmt_descriptor,
+ (struct usb_descriptor_header *) &acm_descriptor,
+ (struct usb_descriptor_header *) &union_desc,
+ (struct usb_descriptor_header *) &hs_status_desc,
+ /* data interface has no altsetting */
+ (struct usb_descriptor_header *) &rndis_data_intf,
+ (struct usb_descriptor_header *) &hs_source_desc,
+ (struct usb_descriptor_header *) &hs_sink_desc,
+ NULL,
+};
+#endif
+
+
/* maxpacket and other transfer characteristics vary by speed. */
static inline struct usb_endpoint_descriptor *
ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
@@ -671,6 +849,10 @@ static struct usb_string strings[] = {
#ifdef DEV_CONFIG_SUBSET
{ STRING_SUBSET, "CDC Ethernet Subset", },
#endif
+#ifdef CONFIG_USB_ETH_RNDIS
+ { STRING_RNDIS, "RNDIS", },
+ { STRING_RNDIS_CONTROL, "RNDIS Communications Control", },
+#endif
{ } /* end of list */
};
@@ -731,8 +913,20 @@ config_buf(struct usb_gadget *g, u8 *buf, u8 type, unsigned index, int is_otg)
if (index >= device_desc.bNumConfigurations)
return -EINVAL;
- config = &eth_config;
- function = which_fn(eth);
+#ifdef CONFIG_USB_ETH_RNDIS
+ /*
+ * list the RNDIS config first, to make Microsoft's drivers
+ * happy. DOCSIS 1.0 needs this too.
+ */
+ if (device_desc.bNumConfigurations == 2 && index == 0) {
+ config = &rndis_config;
+ function = which_fn(rndis);
+ } else
+#endif
+ {
+ config = &eth_config;
+ function = which_fn(eth);
+ }
/* for now, don't advertise srp-only devices */
if (!is_otg)
@@ -747,6 +941,7 @@ config_buf(struct usb_gadget *g, u8 *buf, u8 type, unsigned index, int is_otg)
/*-------------------------------------------------------------------------*/
+static void eth_start(struct eth_dev *dev, gfp_t gfp_flags);
static int alloc_requests(struct eth_dev *dev, unsigned n, gfp_t gfp_flags);
static int
@@ -755,8 +950,8 @@ set_ether_config(struct eth_dev *dev, gfp_t gfp_flags)
int result = 0;
struct usb_gadget *gadget = dev->gadget;
-#if defined(DEV_CONFIG_CDC)
- /* status endpoint used for (optionally) CDC */
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+ /* status endpoint used for RNDIS and (optionally) CDC */
if (!subset_active(dev) && dev->status_ep) {
dev->status = ep_desc(gadget, &hs_status_desc,
&fs_status_desc);
@@ -781,6 +976,10 @@ set_ether_config(struct eth_dev *dev, gfp_t gfp_flags)
* With CDC, the host isn't allowed to use these two data
* endpoints in the default altsetting for the interface.
* so we don't activate them yet. Reset from SET_INTERFACE.
+ *
+ * Strictly speaking RNDIS should work the same: activation is
+ * a side effect of setting a packet filter. Deactivation is
+ * from REMOTE_NDIS_HALT_MSG, reset from REMOTE_NDIS_RESET_MSG.
*/
if (!cdc_active(dev)) {
result = usb_ep_enable(dev->in_ep, dev->in);
@@ -811,6 +1010,12 @@ done:
(void) usb_ep_disable(dev->out_ep);
dev->in = NULL;
dev->out = NULL;
+ } else if (!cdc_active(dev)) {
+ /*
+ * activate non-CDC configs right away
+ * this isn't strictly according to the RNDIS spec
+ */
+ eth_start(dev, GFP_ATOMIC);
}
/* caller is responsible for cleanup on error */
@@ -824,6 +1029,8 @@ static void eth_reset_config(struct eth_dev *dev)
debug("%s\n", __func__);
+ rndis_uninit(dev->rndis_config);
+
/*
* disable endpoints, forcing (synchronous) completion of
* pending i/o. then free the requests.
@@ -846,6 +1053,7 @@ static void eth_reset_config(struct eth_dev *dev)
if (dev->status)
usb_ep_disable(dev->status_ep);
+ dev->rndis = 0;
dev->cdc_filter = 0;
dev->config = 0;
}
@@ -873,6 +1081,12 @@ static int eth_set_config(struct eth_dev *dev, unsigned number,
case DEV_CONFIG_VALUE:
result = set_ether_config(dev, gfp_flags);
break;
+#ifdef CONFIG_USB_ETH_RNDIS
+ case DEV_RNDIS_CONFIG_VALUE:
+ dev->rndis = 1;
+ result = set_ether_config(dev, gfp_flags);
+ break;
+#endif
default:
result = -EINVAL;
/* FALL THROUGH */
@@ -906,7 +1120,10 @@ static int eth_set_config(struct eth_dev *dev, unsigned number,
dev->config = number;
printf("%s speed config #%d: %d mA, %s, using %s\n",
speed, number, power, driver_desc,
- (cdc_active(dev) ? "CDC Ethernet"
+ rndis_active(dev)
+ ? "RNDIS"
+ : (cdc_active(dev)
+ ? "CDC Ethernet"
: "CDC Ethernet Subset"));
}
return result;
@@ -919,7 +1136,7 @@ static int eth_set_config(struct eth_dev *dev, unsigned number,
/*
* The interrupt endpoint is used in CDC networking models (Ethernet, ATM)
* only to notify the host about link status changes (which we support) or
- * report completion of some encapsulated command. Since
+ * report completion of some encapsulated command (as used in RNDIS). Since
* we want this CDC Ethernet code to be vendor-neutral, we don't use that
* command mechanism; and only one status request is ever queued.
*/
@@ -1010,6 +1227,30 @@ static void eth_setup_complete(struct usb_ep *ep, struct usb_request *req)
req->status, req->actual, req->length);
}
+#ifdef CONFIG_USB_ETH_RNDIS
+
+static void rndis_response_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ if (req->status || req->actual != req->length)
+ debug("rndis response complete --> %d, %d/%d\n",
+ req->status, req->actual, req->length);
+
+ /* done sending after USB_CDC_GET_ENCAPSULATED_RESPONSE */
+}
+
+static void rndis_command_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ struct eth_dev *dev = ep->driver_data;
+ int status;
+
+ /* received RNDIS command from USB_CDC_SEND_ENCAPSULATED_COMMAND */
+ status = rndis_msg_parser(dev->rndis_config, (u8 *) req->buf);
+ if (status < 0)
+ error("%s: rndis parse error %d", __func__, status);
+}
+
+#endif /* RNDIS */
+
/*
* The setup() callback implements all the ep0 functionality that's not
* handled lower down. CDC has a number of less-common features:
@@ -1122,6 +1363,7 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
usb_ep_disable(dev->status_ep);
usb_ep_enable(dev->status_ep, dev->status);
}
+
value = 0;
break;
case 1: /* data intf */
@@ -1143,8 +1385,8 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
dev->cdc_filter = DEFAULT_FILTER;
if (dev->status)
issue_start_status(dev);
+ eth_start(dev, GFP_ATOMIC);
}
-
value = 0;
break;
}
@@ -1163,11 +1405,11 @@ done_set_intf:
|| !dev->config
|| wIndex > 1)
break;
- if (!(cdc_active(dev)) && wIndex != 0)
+ if (!(cdc_active(dev) || rndis_active(dev)) && wIndex != 0)
break;
/* for CDC, iff carrier is on, data interface is active. */
- if (wIndex != 1)
+ if (rndis_active(dev) || wIndex != 1)
*(u8 *)req->buf = 0;
else {
/* *(u8 *)req->buf = netif_carrier_ok (dev->net) ? 1 : 0; */
@@ -1203,6 +1445,49 @@ done_set_intf:
#endif /* DEV_CONFIG_CDC */
+#ifdef CONFIG_USB_ETH_RNDIS
+ /*
+ * RNDIS uses the CDC command encapsulation mechanism to implement
+ * an RPC scheme, with much getting/setting of attributes by OID.
+ */
+ case USB_CDC_SEND_ENCAPSULATED_COMMAND:
+ if (ctrl->bRequestType != (USB_TYPE_CLASS|USB_RECIP_INTERFACE)
+ || !rndis_active(dev)
+ || wLength > USB_BUFSIZ
+ || wValue
+ || rndis_control_intf.bInterfaceNumber
+ != wIndex)
+ break;
+ /* read the request, then process it */
+ value = wLength;
+ req->complete = rndis_command_complete;
+ /* later, rndis_control_ack () sends a notification */
+ break;
+
+ case USB_CDC_GET_ENCAPSULATED_RESPONSE:
+ if ((USB_DIR_IN|USB_TYPE_CLASS|USB_RECIP_INTERFACE)
+ == ctrl->bRequestType
+ && rndis_active(dev)
+ /* && wLength >= 0x0400 */
+ && !wValue
+ && rndis_control_intf.bInterfaceNumber
+ == wIndex) {
+ u8 *buf;
+ u32 n;
+
+ /* return the result */
+ buf = rndis_get_next_response(dev->rndis_config, &n);
+ if (buf) {
+ memcpy(req->buf, buf, n);
+ req->complete = rndis_response_complete;
+ rndis_free_response(dev->rndis_config, buf);
+ value = n;
+ }
+ /* else stalls ... spec says to avoid that */
+ }
+ break;
+#endif /* RNDIS */
+
default:
debug("unknown control req%02x.%02x v%04x i%04x l%d\n",
ctrl->bRequestType, ctrl->bRequest,
@@ -1244,17 +1529,24 @@ static int rx_submit(struct eth_dev *dev, struct usb_request *req,
* already allocated. Some hardware doesn't deal well with short
* reads (e.g. DMA must be N*maxpacket), so for now don't trim a
* byte off the end (to force hardware errors on overflow).
+ *
+ * RNDIS uses internal framing, and explicitly allows senders to
+ * pad to end-of-packet. That's potentially nice for speed,
+ * but means receivers can't recover synch on their own.
*/
debug("%s\n", __func__);
size = (ETHER_HDR_SIZE + dev->mtu + RX_EXTRA);
size += dev->out_ep->maxpacket - 1;
+ if (rndis_active(dev))
+ size += sizeof(struct rndis_packet_msg_type);
size -= size % dev->out_ep->maxpacket;
/*
* Some platforms perform better when IP packets are aligned,
- * but on at least one, checksumming fails otherwise.
+ * but on at least one, checksumming fails otherwise. Note:
+ * RNDIS headers involve variable numbers of LE32 values.
*/
req->buf = (u8 *) NetRxPackets[0];
@@ -1274,6 +1566,44 @@ static void rx_complete(struct usb_ep *ep, struct usb_request *req)
struct eth_dev *dev = ep->driver_data;
debug("%s: status %d\n", __func__, req->status);
+ switch (req->status) {
+ /* normal completion */
+ case 0:
+ if (rndis_active(dev)) {
+ /* we know MaxPacketsPerTransfer == 1 here */
+ int length = rndis_rm_hdr(req->buf, req->actual);
+ if (length < 0)
+ goto length_err;
+ req->length -= length;
+ req->actual -= length;
+ }
+ if (req->actual < ETH_HLEN || ETH_FRAME_LEN < req->actual) {
+length_err:
+ dev->stats.rx_errors++;
+ dev->stats.rx_length_errors++;
+ debug("rx length %d\n", req->length);
+ break;
+ }
+
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += req->length;
+ break;
+
+ /* software-driven interface shutdown */
+ case -ECONNRESET: /* unlink */
+ case -ESHUTDOWN: /* disconnect etc */
+ /* for hardware automagic (such as pxa) */
+ case -ECONNABORTED: /* endpoint reset */
+ break;
+
+ /* data overrun */
+ case -EOVERFLOW:
+ dev->stats.rx_over_errors++;
+ /* FALLTHROUGH */
+ default:
+ dev->stats.rx_errors++;
+ break;
+ }
packet_received = 1;
}
@@ -1302,7 +1632,22 @@ fail1:
static void tx_complete(struct usb_ep *ep, struct usb_request *req)
{
+ struct eth_dev *dev = ep->driver_data;
+
debug("%s: status %s\n", __func__, (req->status) ? "failed" : "ok");
+ switch (req->status) {
+ default:
+ dev->stats.tx_errors++;
+ debug("tx err %d\n", req->status);
+ /* FALLTHROUGH */
+ case -ECONNRESET: /* unlink */
+ case -ESHUTDOWN: /* disconnect etc */
+ break;
+ case 0:
+ dev->stats.tx_bytes += req->length;
+ }
+ dev->stats.tx_packets++;
+
packet_sent = 1;
}
@@ -1429,9 +1774,11 @@ drop:
static void eth_unbind(struct usb_gadget *gadget)
{
- struct eth_dev *dev = get_gadget_data(gadget);
+ struct eth_dev *dev = get_gadget_data(gadget);
debug("%s...\n", __func__);
+ rndis_deregister(dev->rndis_config);
+ rndis_exit();
/* we've already been disconnected ... no i/o is active */
if (dev->req) {
@@ -1463,6 +1810,7 @@ static void eth_unbind(struct usb_gadget *gadget)
static void eth_disconnect(struct usb_gadget *gadget)
{
eth_reset_config(get_gadget_data(gadget));
+ /* FIXME RNDIS should enter RNDIS_UNINITIALIZED */
}
static void eth_suspend(struct usb_gadget *gadget)
@@ -1477,6 +1825,127 @@ static void eth_resume(struct usb_gadget *gadget)
/*-------------------------------------------------------------------------*/
+#ifdef CONFIG_USB_ETH_RNDIS
+
+/*
+ * The interrupt endpoint is used in RNDIS to notify the host when messages
+ * other than data packets are available ... notably the REMOTE_NDIS_*_CMPLT
+ * messages, but also REMOTE_NDIS_INDICATE_STATUS_MSG and potentially even
+ * REMOTE_NDIS_KEEPALIVE_MSG.
+ *
+ * The RNDIS control queue is processed by GET_ENCAPSULATED_RESPONSE, and
+ * normally just one notification will be queued.
+ */
+
+static void rndis_control_ack_complete(struct usb_ep *ep,
+ struct usb_request *req)
+{
+ struct eth_dev *dev = ep->driver_data;
+
+ debug("%s...\n", __func__);
+ if (req->status || req->actual != req->length)
+ debug("rndis control ack complete --> %d, %d/%d\n",
+ req->status, req->actual, req->length);
+
+ if (!l_ethdev.network_started) {
+ if (rndis_get_state(dev->rndis_config)
+ == RNDIS_DATA_INITIALIZED) {
+ l_ethdev.network_started = 1;
+ printf("USB RNDIS network up!\n");
+ }
+ }
+
+ req->context = NULL;
+
+ if (req != dev->stat_req)
+ usb_ep_free_request(ep, req);
+}
+
+static char rndis_resp_buf[8] __attribute__((aligned(sizeof(__le32))));
+
+static int rndis_control_ack(struct eth_device *net)
+{
+ struct eth_dev *dev = &l_ethdev;
+ int length;
+ struct usb_request *resp = dev->stat_req;
+
+ /* in case RNDIS calls this after disconnect */
+ if (!dev->status) {
+ debug("status ENODEV\n");
+ return -ENODEV;
+ }
+
+ /* in case queue length > 1 */
+ if (resp->context) {
+ resp = usb_ep_alloc_request(dev->status_ep, GFP_ATOMIC);
+ if (!resp)
+ return -ENOMEM;
+ resp->buf = rndis_resp_buf;
+ }
+
+ /*
+ * Send RNDIS RESPONSE_AVAILABLE notification;
+ * USB_CDC_NOTIFY_RESPONSE_AVAILABLE should work too
+ */
+ resp->length = 8;
+ resp->complete = rndis_control_ack_complete;
+ resp->context = dev;
+
+ *((__le32 *) resp->buf) = __constant_cpu_to_le32(1);
+ *((__le32 *) (resp->buf + 4)) = __constant_cpu_to_le32(0);
+
+ length = usb_ep_queue(dev->status_ep, resp, GFP_ATOMIC);
+ if (length < 0) {
+ resp->status = 0;
+ rndis_control_ack_complete(dev->status_ep, resp);
+ }
+
+ return 0;
+}
+
+#else
+
+#define rndis_control_ack NULL
+
+#endif /* RNDIS */
+
+static void eth_start(struct eth_dev *dev, gfp_t gfp_flags)
+{
+ if (rndis_active(dev)) {
+ rndis_set_param_medium(dev->rndis_config,
+ NDIS_MEDIUM_802_3,
+ BITRATE(dev->gadget)/100);
+ rndis_signal_connect(dev->rndis_config);
+ }
+}
+
+static int eth_stop(struct eth_dev *dev)
+{
+#ifdef RNDIS_COMPLETE_SIGNAL_DISCONNECT
+ unsigned long ts;
+ unsigned long timeout = CONFIG_SYS_HZ; /* 1 sec to stop RNDIS */
+#endif
+
+ if (rndis_active(dev)) {
+ rndis_set_param_medium(dev->rndis_config, NDIS_MEDIUM_802_3, 0);
+ rndis_signal_disconnect(dev->rndis_config);
+
+#ifdef RNDIS_COMPLETE_SIGNAL_DISCONNECT
+ /* Wait until host receives OID_GEN_MEDIA_CONNECT_STATUS */
+ ts = get_timer(0);
+ while (get_timer(ts) < timeout)
+ usb_gadget_handle_interrupts();
+#endif
+
+ rndis_uninit(dev->rndis_config);
+ dev->rndis = 0;
+ }
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
static int is_eth_addr_valid(char *str)
{
if (strlen(str) == 17) {
@@ -1538,8 +2007,9 @@ static int get_ether_addr(const char *str, u8 *dev_addr)
static int eth_bind(struct usb_gadget *gadget)
{
struct eth_dev *dev = &l_ethdev;
- u8 cdc = 1, zlp = 1;
+ u8 cdc = 1, zlp = 1, rndis = 1;
struct usb_ep *in_ep, *out_ep, *status_ep = NULL;
+ int status = -ENOMEM;
int gcnum;
u8 tmp[7];
@@ -1547,6 +2017,9 @@ static int eth_bind(struct usb_gadget *gadget)
#ifndef DEV_CONFIG_CDC
cdc = 0;
#endif
+#ifndef CONFIG_USB_ETH_RNDIS
+ rndis = 0;
+#endif
/*
* Because most host side USB stacks handle CDC Ethernet, that
* standard protocol is _strongly_ preferred for interop purposes.
@@ -1561,6 +2034,7 @@ static int eth_bind(struct usb_gadget *gadget)
} else if (gadget_is_sh(gadget)) {
/* sh doesn't support multiple interfaces or configs */
cdc = 0;
+ rndis = 0;
} else if (gadget_is_sa1100(gadget)) {
/* hardware can't write zlps */
zlp = 0;
@@ -1586,22 +2060,45 @@ static int eth_bind(struct usb_gadget *gadget)
}
/*
- * CDC subset ... recognized by Linux since 2.4.10, but Windows
- * drivers aren't widely available. (That may be improved by
- * supporting one submode of the "SAFE" variant of MDLM.)
+ * If there's an RNDIS configuration, that's what Windows wants to
+ * be using ... so use these product IDs here and in the "linux.inf"
+ * needed to install MSFT drivers. Current Linux kernels will use
+ * the second configuration if it's CDC Ethernet, and need some help
+ * to choose the right configuration otherwise.
*/
- if (!cdc) {
+ if (rndis) {
+#if defined(CONFIG_USB_RNDIS_VENDOR_ID) && defined(CONFIG_USB_RNDIS_PRODUCT_ID)
device_desc.idVendor =
- __constant_cpu_to_le16(SIMPLE_VENDOR_NUM);
+ __constant_cpu_to_le16(CONFIG_USB_RNDIS_VENDOR_ID);
device_desc.idProduct =
- __constant_cpu_to_le16(SIMPLE_PRODUCT_NUM);
- }
+ __constant_cpu_to_le16(CONFIG_USB_RNDIS_PRODUCT_ID);
+#else
+ device_desc.idVendor =
+ __constant_cpu_to_le16(RNDIS_VENDOR_NUM);
+ device_desc.idProduct =
+ __constant_cpu_to_le16(RNDIS_PRODUCT_NUM);
+#endif
+ sprintf(product_desc, "RNDIS/%s", driver_desc);
- /* support optional vendor/distro customization */
+ /*
+ * CDC subset ... recognized by Linux since 2.4.10, but Windows
+ * drivers aren't widely available. (That may be improved by
+ * supporting one submode of the "SAFE" variant of MDLM.)
+ */
+ } else {
#if defined(CONFIG_USB_CDC_VENDOR_ID) && defined(CONFIG_USB_CDC_PRODUCT_ID)
- device_desc.idVendor = cpu_to_le16(CONFIG_USB_CDC_VENDOR_ID);
- device_desc.idProduct = cpu_to_le16(CONFIG_USB_CDC_PRODUCT_ID);
+ device_desc.idVendor = cpu_to_le16(CONFIG_USB_CDC_VENDOR_ID);
+ device_desc.idProduct = cpu_to_le16(CONFIG_USB_CDC_PRODUCT_ID);
+#else
+ if (!cdc) {
+ device_desc.idVendor =
+ __constant_cpu_to_le16(SIMPLE_VENDOR_NUM);
+ device_desc.idProduct =
+ __constant_cpu_to_le16(SIMPLE_PRODUCT_NUM);
+ }
#endif
+ }
+ /* support optional vendor/distro customization */
if (bcdDevice)
device_desc.bcdDevice = cpu_to_le16(bcdDevice);
if (iManufacturer)
@@ -1629,18 +2126,23 @@ autoconf_fail:
goto autoconf_fail;
out_ep->driver_data = out_ep; /* claim */
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* CDC Ethernet control interface doesn't require a status endpoint.
* Since some hosts expect one, try to allocate one anyway.
*/
- if (cdc) {
+ if (cdc || rndis) {
status_ep = usb_ep_autoconfig(gadget, &fs_status_desc);
if (status_ep) {
status_ep->driver_data = status_ep; /* claim */
+ } else if (rndis) {
+ error("can't run RNDIS on %s", gadget->name);
+ return -ENODEV;
+#ifdef DEV_CONFIG_CDC
} else if (cdc) {
control_intf.bNumEndpoints = 0;
/* FIXME remove endpoint from descriptor list */
+#endif
}
}
#endif
@@ -1661,8 +2163,14 @@ autoconf_fail:
device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
usb_gadget_set_selfpowered(gadget);
+ /* For now RNDIS is always a second config */
+ if (rndis)
+ device_desc.bNumConfigurations = 2;
+
if (gadget_is_dualspeed(gadget)) {
- if (!cdc)
+ if (rndis)
+ dev_qualifier.bNumConfigurations = 2;
+ else if (!cdc)
dev_qualifier.bDeviceClass = USB_CLASS_VENDOR_SPEC;
/* assumes ep0 uses the same value for both speeds ... */
@@ -1673,7 +2181,7 @@ autoconf_fail:
fs_source_desc.bEndpointAddress;
hs_sink_desc.bEndpointAddress =
fs_sink_desc.bEndpointAddress;
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (status_ep)
hs_status_desc.bEndpointAddress =
fs_status_desc.bEndpointAddress;
@@ -1684,8 +2192,14 @@ autoconf_fail:
otg_descriptor.bmAttributes |= USB_OTG_HNP,
eth_config.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
eth_config.bMaxPower = 4;
+#ifdef CONFIG_USB_ETH_RNDIS
+ rndis_config.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+ rndis_config.bMaxPower = 4;
+#endif
}
+
+ /* network device setup */
dev->net = &l_netdev;
dev->cdc = cdc;
@@ -1697,7 +2211,7 @@ autoconf_fail:
/*
* Module params for these addresses should come from ID proms.
- * The host side address is used with CDC, and commonly
+ * The host side address is used with CDC and RNDIS, and commonly
* ends up in a persistent config database. It's not clear if
* host side code for the SAFE thing cares -- its original BLAN
* thing didn't, Sharp never assigned those addresses on Zaurii.
@@ -1714,21 +2228,12 @@ autoconf_fail:
dev->host_mac[2], dev->host_mac[3],
dev->host_mac[4], dev->host_mac[5]);
- printf("using %s, OUT %s IN %s%s%s\n", gadget->name,
- out_ep->name, in_ep->name,
- status_ep ? " STATUS " : "",
- status_ep ? status_ep->name : ""
- );
- printf("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->net->enetaddr[0], dev->net->enetaddr[1],
- dev->net->enetaddr[2], dev->net->enetaddr[3],
- dev->net->enetaddr[4], dev->net->enetaddr[5]);
-
- if (cdc) {
- printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->host_mac[0], dev->host_mac[1],
- dev->host_mac[2], dev->host_mac[3],
- dev->host_mac[4], dev->host_mac[5]);
+ if (rndis) {
+ status = rndis_init();
+ if (status < 0) {
+ error("can't init RNDIS, %d", status);
+ goto fail;
+ }
}
/*
@@ -1745,7 +2250,7 @@ autoconf_fail:
dev->req->complete = eth_setup_complete;
/* ... and maybe likewise for status transfer */
-#if defined(DEV_CONFIG_CDC)
+#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (dev->status_ep) {
dev->stat_req = usb_ep_alloc_request(dev->status_ep,
GFP_KERNEL);
@@ -1769,14 +2274,60 @@ autoconf_fail:
* - iff DATA transfer is active, carrier is "on"
* - tx queueing enabled if open *and* carrier is "on"
*/
+
+ printf("using %s, OUT %s IN %s%s%s\n", gadget->name,
+ out_ep->name, in_ep->name,
+ status_ep ? " STATUS " : "",
+ status_ep ? status_ep->name : ""
+ );
+ printf("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->net->enetaddr[0], dev->net->enetaddr[1],
+ dev->net->enetaddr[2], dev->net->enetaddr[3],
+ dev->net->enetaddr[4], dev->net->enetaddr[5]);
+
+ if (cdc || rndis)
+ printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->host_mac[0], dev->host_mac[1],
+ dev->host_mac[2], dev->host_mac[3],
+ dev->host_mac[4], dev->host_mac[5]);
+
+ if (rndis) {
+ u32 vendorID = 0;
+
+ /* FIXME RNDIS vendor id == "vendor NIC code" == ? */
+
+ dev->rndis_config = rndis_register(rndis_control_ack);
+ if (dev->rndis_config < 0) {
+fail0:
+ eth_unbind(gadget);
+ debug("RNDIS setup failed\n");
+ status = -ENODEV;
+ goto fail;
+ }
+
+ /* these set up a lot of the OIDs that RNDIS needs */
+ rndis_set_host_mac(dev->rndis_config, dev->host_mac);
+ if (rndis_set_param_dev(dev->rndis_config, dev->net, dev->mtu,
+ &dev->stats, &dev->cdc_filter))
+ goto fail0;
+ if (rndis_set_param_vendor(dev->rndis_config, vendorID,
+ manufacturer))
+ goto fail0;
+ if (rndis_set_param_medium(dev->rndis_config,
+ NDIS_MEDIUM_802_3, 0))
+ goto fail0;
+ printf("RNDIS ready\n");
+ }
return 0;
fail:
- error("%s failed", __func__);
+ error("%s failed, status = %d", __func__, status);
eth_unbind(gadget);
- return -ENOMEM;
+ return status;
}
+/*-------------------------------------------------------------------------*/
+
static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
{
struct eth_dev *dev = &l_ethdev;
@@ -1849,6 +2400,7 @@ static int usb_eth_send(struct eth_device *netdev,
volatile void *packet, int length)
{
int retval;
+ void *rndis_pkt = NULL;
struct eth_dev *dev = &l_ethdev;
struct usb_request *req = dev->tx_req;
unsigned long ts;
@@ -1856,6 +2408,20 @@ static int usb_eth_send(struct eth_device *netdev,
debug("%s:...\n", __func__);
+ /* new buffer is needed to include RNDIS header */
+ if (rndis_active(dev)) {
+ rndis_pkt = malloc(length +
+ sizeof(struct rndis_packet_msg_type));
+ if (!rndis_pkt) {
+ error("No memory to alloc RNDIS packet");
+ goto drop;
+ }
+ rndis_add_hdr(rndis_pkt, length);
+ memcpy(rndis_pkt + sizeof(struct rndis_packet_msg_type),
+ (void *)packet, length);
+ packet = rndis_pkt;
+ length += sizeof(struct rndis_packet_msg_type);
+ }
req->buf = (void *)packet;
req->context = NULL;
req->complete = tx_complete;
@@ -1891,8 +2457,13 @@ static int usb_eth_send(struct eth_device *netdev,
}
usb_gadget_handle_interrupts();
}
+ if (rndis_pkt)
+ free(rndis_pkt);
return 0;
+drop:
+ dev->stats.tx_dropped++;
+ return -ENOMEM;
}
static int usb_eth_recv(struct eth_device *netdev)
@@ -1927,7 +2498,27 @@ void usb_eth_halt(struct eth_device *netdev)
if (!dev->gadget)
return;
+ /*
+ * Some USB controllers may need additional deinitialization here
+ * before dropping pull-up (also due to hardware issues).
+ * For example: unhandled interrupt with status stage started may
+ * bring the controller to fully broken state (until board reset).
+ * There are some variants to debug and fix such cases:
+ * 1) In the case of RNDIS connection eth_stop can perform additional
+ * interrupt handling. See RNDIS_COMPLETE_SIGNAL_DISCONNECT definition.
+ * 2) 'pullup' callback in your UDC driver can be improved to perform
+ * this deinitialization.
+ */
+ eth_stop(dev);
+
usb_gadget_disconnect(dev->gadget);
+
+ /* Clear pending interrupt */
+ if (dev->network_started) {
+ usb_gadget_handle_interrupts();
+ dev->network_started = 0;
+ }
+
usb_gadget_unregister_driver(&eth_driver);
}
diff --git a/drivers/usb/gadget/ndis.h b/drivers/usb/gadget/ndis.h
new file mode 100644
index 000000000..753838f79
--- /dev/null
+++ b/drivers/usb/gadget/ndis.h
@@ -0,0 +1,217 @@
+/*
+ * ndis.h
+ *
+ * ntddndis.h modified by Benedikt Spranger <b.spranger@pengutronix.de>
+ *
+ * Thanks to the cygwin development team,
+ * espacially to Casper S. Hornstrup <chorns@users.sourceforge.net>
+ *
+ * THIS SOFTWARE IS NOT COPYRIGHTED
+ *
+ * This source code is offered for use in the public domain. You may
+ * use, modify or distribute it freely.
+ *
+ * This code is distributed in the hope that it will be useful but
+ * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY
+ * DISCLAIMED. This includes but is not limited to warranties of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef _USBGADGET_NDIS_H
+#define _USBGADGET_NDIS_H
+
+
+#define NDIS_STATUS_MULTICAST_FULL 0xC0010009
+#define NDIS_STATUS_MULTICAST_EXISTS 0xC001000A
+#define NDIS_STATUS_MULTICAST_NOT_FOUND 0xC001000B
+
+enum NDIS_DEVICE_POWER_STATE {
+ NdisDeviceStateUnspecified = 0,
+ NdisDeviceStateD0,
+ NdisDeviceStateD1,
+ NdisDeviceStateD2,
+ NdisDeviceStateD3,
+ NdisDeviceStateMaximum
+};
+
+struct NDIS_PM_WAKE_UP_CAPABILITIES {
+ enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp;
+ enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp;
+ enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp;
+};
+
+/* NDIS_PNP_CAPABILITIES.Flags constants */
+#define NDIS_DEVICE_WAKE_UP_ENABLE 0x00000001
+#define NDIS_DEVICE_WAKE_ON_PATTERN_MATCH_ENABLE 0x00000002
+#define NDIS_DEVICE_WAKE_ON_MAGIC_PACKET_ENABLE 0x00000004
+
+struct NDIS_PNP_CAPABILITIES {
+ __le32 Flags;
+ struct NDIS_PM_WAKE_UP_CAPABILITIES WakeUpCapabilities;
+};
+
+struct NDIS_PM_PACKET_PATTERN {
+ __le32 Priority;
+ __le32 Reserved;
+ __le32 MaskSize;
+ __le32 PatternOffset;
+ __le32 PatternSize;
+ __le32 PatternFlags;
+};
+
+
+/* Required Object IDs (OIDs) */
+#define OID_GEN_SUPPORTED_LIST 0x00010101
+#define OID_GEN_HARDWARE_STATUS 0x00010102
+#define OID_GEN_MEDIA_SUPPORTED 0x00010103
+#define OID_GEN_MEDIA_IN_USE 0x00010104
+#define OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105
+#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106
+#define OID_GEN_LINK_SPEED 0x00010107
+#define OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108
+#define OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109
+#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A
+#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B
+#define OID_GEN_VENDOR_ID 0x0001010C
+#define OID_GEN_VENDOR_DESCRIPTION 0x0001010D
+#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010E
+#define OID_GEN_CURRENT_LOOKAHEAD 0x0001010F
+#define OID_GEN_DRIVER_VERSION 0x00010110
+#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111
+#define OID_GEN_PROTOCOL_OPTIONS 0x00010112
+#define OID_GEN_MAC_OPTIONS 0x00010113
+#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114
+#define OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115
+#define OID_GEN_VENDOR_DRIVER_VERSION 0x00010116
+#define OID_GEN_SUPPORTED_GUIDS 0x00010117
+#define OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118
+#define OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119
+#define OID_GEN_MACHINE_NAME 0x0001021A
+#define OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B
+#define OID_GEN_VLAN_ID 0x0001021C
+
+/* Optional OIDs */
+#define OID_GEN_MEDIA_CAPABILITIES 0x00010201
+#define OID_GEN_PHYSICAL_MEDIUM 0x00010202
+
+/* Required statistics OIDs */
+#define OID_GEN_XMIT_OK 0x00020101
+#define OID_GEN_RCV_OK 0x00020102
+#define OID_GEN_XMIT_ERROR 0x00020103
+#define OID_GEN_RCV_ERROR 0x00020104
+#define OID_GEN_RCV_NO_BUFFER 0x00020105
+
+/* Optional statistics OIDs */
+#define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201
+#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
+#define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203
+#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
+#define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205
+#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
+#define OID_GEN_DIRECTED_BYTES_RCV 0x00020207
+#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
+#define OID_GEN_MULTICAST_BYTES_RCV 0x00020209
+#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
+#define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B
+#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
+#define OID_GEN_RCV_CRC_ERROR 0x0002020D
+#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
+#define OID_GEN_GET_TIME_CAPS 0x0002020F
+#define OID_GEN_GET_NETCARD_TIME 0x00020210
+#define OID_GEN_NETCARD_LOAD 0x00020211
+#define OID_GEN_DEVICE_PROFILE 0x00020212
+#define OID_GEN_INIT_TIME_MS 0x00020213
+#define OID_GEN_RESET_COUNTS 0x00020214
+#define OID_GEN_MEDIA_SENSE_COUNTS 0x00020215
+#define OID_GEN_FRIENDLY_NAME 0x00020216
+#define OID_GEN_MINIPORT_INFO 0x00020217
+#define OID_GEN_RESET_VERIFY_PARAMETERS 0x00020218
+
+/* IEEE 802.3 (Ethernet) OIDs */
+#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001
+
+#define OID_802_3_PERMANENT_ADDRESS 0x01010101
+#define OID_802_3_CURRENT_ADDRESS 0x01010102
+#define OID_802_3_MULTICAST_LIST 0x01010103
+#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104
+#define OID_802_3_MAC_OPTIONS 0x01010105
+#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
+#define OID_802_3_XMIT_ONE_COLLISION 0x01020102
+#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
+#define OID_802_3_XMIT_DEFERRED 0x01020201
+#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
+#define OID_802_3_RCV_OVERRUN 0x01020203
+#define OID_802_3_XMIT_UNDERRUN 0x01020204
+#define OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205
+#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
+#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
+
+/* OID_GEN_MINIPORT_INFO constants */
+#define NDIS_MINIPORT_BUS_MASTER 0x00000001
+#define NDIS_MINIPORT_WDM_DRIVER 0x00000002
+#define NDIS_MINIPORT_SG_LIST 0x00000004
+#define NDIS_MINIPORT_SUPPORTS_MEDIA_QUERY 0x00000008
+#define NDIS_MINIPORT_INDICATES_PACKETS 0x00000010
+#define NDIS_MINIPORT_IGNORE_PACKET_QUEUE 0x00000020
+#define NDIS_MINIPORT_IGNORE_REQUEST_QUEUE 0x00000040
+#define NDIS_MINIPORT_IGNORE_TOKEN_RING_ERRORS 0x00000080
+#define NDIS_MINIPORT_INTERMEDIATE_DRIVER 0x00000100
+#define NDIS_MINIPORT_IS_NDIS_5 0x00000200
+#define NDIS_MINIPORT_IS_CO 0x00000400
+#define NDIS_MINIPORT_DESERIALIZE 0x00000800
+#define NDIS_MINIPORT_REQUIRES_MEDIA_POLLING 0x00001000
+#define NDIS_MINIPORT_SUPPORTS_MEDIA_SENSE 0x00002000
+#define NDIS_MINIPORT_NETBOOT_CARD 0x00004000
+#define NDIS_MINIPORT_PM_SUPPORTED 0x00008000
+#define NDIS_MINIPORT_SUPPORTS_MAC_ADDRESS_OVERWRITE 0x00010000
+#define NDIS_MINIPORT_USES_SAFE_BUFFER_APIS 0x00020000
+#define NDIS_MINIPORT_HIDDEN 0x00040000
+#define NDIS_MINIPORT_SWENUM 0x00080000
+#define NDIS_MINIPORT_SURPRISE_REMOVE_OK 0x00100000
+#define NDIS_MINIPORT_NO_HALT_ON_SUSPEND 0x00200000
+#define NDIS_MINIPORT_HARDWARE_DEVICE 0x00400000
+#define NDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS 0x00800000
+#define NDIS_MINIPORT_64BITS_DMA 0x01000000
+
+#define NDIS_MEDIUM_802_3 0x00000000
+#define NDIS_MEDIUM_802_5 0x00000001
+#define NDIS_MEDIUM_FDDI 0x00000002
+#define NDIS_MEDIUM_WAN 0x00000003
+#define NDIS_MEDIUM_LOCAL_TALK 0x00000004
+#define NDIS_MEDIUM_DIX 0x00000005
+#define NDIS_MEDIUM_ARCENT_RAW 0x00000006
+#define NDIS_MEDIUM_ARCENT_878_2 0x00000007
+#define NDIS_MEDIUM_ATM 0x00000008
+#define NDIS_MEDIUM_WIRELESS_LAN 0x00000009
+#define NDIS_MEDIUM_IRDA 0x0000000A
+#define NDIS_MEDIUM_BPC 0x0000000B
+#define NDIS_MEDIUM_CO_WAN 0x0000000C
+#define NDIS_MEDIUM_1394 0x0000000D
+
+#define NDIS_PACKET_TYPE_DIRECTED 0x00000001
+#define NDIS_PACKET_TYPE_MULTICAST 0x00000002
+#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004
+#define NDIS_PACKET_TYPE_BROADCAST 0x00000008
+#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010
+#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020
+#define NDIS_PACKET_TYPE_SMT 0x00000040
+#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080
+#define NDIS_PACKET_TYPE_GROUP 0x00000100
+#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200
+#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400
+#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800
+
+#define NDIS_MEDIA_STATE_CONNECTED 0x00000000
+#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001
+
+#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA 0x00000001
+#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED 0x00000002
+#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND 0x00000004
+#define NDIS_MAC_OPTION_NO_LOOPBACK 0x00000008
+#define NDIS_MAC_OPTION_FULL_DUPLEX 0x00000010
+#define NDIS_MAC_OPTION_EOTX_INDICATION 0x00000020
+#define NDIS_MAC_OPTION_8021P_PRIORITY 0x00000040
+#define NDIS_MAC_OPTION_RESERVED 0x80000000
+
+#endif /* _USBGADGET_NDIS_H */
diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c
new file mode 100644
index 000000000..886c0936e
--- /dev/null
+++ b/drivers/usb/gadget/rndis.c
@@ -0,0 +1,1317 @@
+/*
+ * RNDIS MSG parser
+ *
+ * Authors: Benedikt Spranger, Pengutronix
+ * Robert Schwebel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This software was originally developed in conformance with
+ * Microsoft's Remote NDIS Specification License Agreement.
+ *
+ * 03/12/2004 Kai-Uwe Bloem <linux-development@auerswald.de>
+ * Fixed message length bug in init_response
+ *
+ * 03/25/2004 Kai-Uwe Bloem <linux-development@auerswald.de>
+ * Fixed rndis_rm_hdr length bug.
+ *
+ * Copyright (C) 2004 by David Brownell
+ * updates to merge with Linux 2.6, better match RNDIS spec
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <asm/errno.h>
+
+#undef RNDIS_PM
+#undef RNDIS_WAKEUP
+#undef VERBOSE
+
+#include "rndis.h"
+
+#define ETH_ALEN 6 /* Octets in one ethernet addr */
+#define ETH_HLEN 14 /* Total octets in header. */
+#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN 1500 /* Max. octets in payload */
+#define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN 4 /* Octets in the FCS */
+#define ENOTSUPP 524 /* Operation is not supported */
+
+
+/*
+ * The driver for your USB chip needs to support ep0 OUT to work with
+ * RNDIS, plus all three CDC Ethernet endpoints (interrupt not optional).
+ *
+ * Windows hosts need an INF file like Documentation/usb/linux.inf
+ * and will be happier if you provide the host_addr module parameter.
+ */
+
+#define RNDIS_MAX_CONFIGS 1
+
+static rndis_params rndis_per_dev_params[RNDIS_MAX_CONFIGS];
+
+/* Driver Version */
+static const __le32 rndis_driver_version = __constant_cpu_to_le32(1);
+
+/* Function Prototypes */
+static rndis_resp_t *rndis_add_response(int configNr, u32 length);
+
+
+/* supported OIDs */
+static const u32 oid_supported_list[] = {
+ /* the general stuff */
+ OID_GEN_SUPPORTED_LIST,
+ OID_GEN_HARDWARE_STATUS,
+ OID_GEN_MEDIA_SUPPORTED,
+ OID_GEN_MEDIA_IN_USE,
+ OID_GEN_MAXIMUM_FRAME_SIZE,
+ OID_GEN_LINK_SPEED,
+ OID_GEN_TRANSMIT_BLOCK_SIZE,
+ OID_GEN_RECEIVE_BLOCK_SIZE,
+ OID_GEN_VENDOR_ID,
+ OID_GEN_VENDOR_DESCRIPTION,
+ OID_GEN_VENDOR_DRIVER_VERSION,
+ OID_GEN_CURRENT_PACKET_FILTER,
+ OID_GEN_MAXIMUM_TOTAL_SIZE,
+ OID_GEN_MEDIA_CONNECT_STATUS,
+ OID_GEN_PHYSICAL_MEDIUM,
+#if 0
+ OID_GEN_RNDIS_CONFIG_PARAMETER,
+#endif
+
+ /* the statistical stuff */
+ OID_GEN_XMIT_OK,
+ OID_GEN_RCV_OK,
+ OID_GEN_XMIT_ERROR,
+ OID_GEN_RCV_ERROR,
+ OID_GEN_RCV_NO_BUFFER,
+#ifdef RNDIS_OPTIONAL_STATS
+ OID_GEN_DIRECTED_BYTES_XMIT,
+ OID_GEN_DIRECTED_FRAMES_XMIT,
+ OID_GEN_MULTICAST_BYTES_XMIT,
+ OID_GEN_MULTICAST_FRAMES_XMIT,
+ OID_GEN_BROADCAST_BYTES_XMIT,
+ OID_GEN_BROADCAST_FRAMES_XMIT,
+ OID_GEN_DIRECTED_BYTES_RCV,
+ OID_GEN_DIRECTED_FRAMES_RCV,
+ OID_GEN_MULTICAST_BYTES_RCV,
+ OID_GEN_MULTICAST_FRAMES_RCV,
+ OID_GEN_BROADCAST_BYTES_RCV,
+ OID_GEN_BROADCAST_FRAMES_RCV,
+ OID_GEN_RCV_CRC_ERROR,
+ OID_GEN_TRANSMIT_QUEUE_LENGTH,
+#endif /* RNDIS_OPTIONAL_STATS */
+
+ /* mandatory 802.3 */
+ /* the general stuff */
+ OID_802_3_PERMANENT_ADDRESS,
+ OID_802_3_CURRENT_ADDRESS,
+ OID_802_3_MULTICAST_LIST,
+ OID_802_3_MAC_OPTIONS,
+ OID_802_3_MAXIMUM_LIST_SIZE,
+
+ /* the statistical stuff */
+ OID_802_3_RCV_ERROR_ALIGNMENT,
+ OID_802_3_XMIT_ONE_COLLISION,
+ OID_802_3_XMIT_MORE_COLLISIONS,
+#ifdef RNDIS_OPTIONAL_STATS
+ OID_802_3_XMIT_DEFERRED,
+ OID_802_3_XMIT_MAX_COLLISIONS,
+ OID_802_3_RCV_OVERRUN,
+ OID_802_3_XMIT_UNDERRUN,
+ OID_802_3_XMIT_HEARTBEAT_FAILURE,
+ OID_802_3_XMIT_TIMES_CRS_LOST,
+ OID_802_3_XMIT_LATE_COLLISIONS,
+#endif /* RNDIS_OPTIONAL_STATS */
+
+#ifdef RNDIS_PM
+ /* PM and wakeup are mandatory for USB: */
+
+ /* power management */
+ OID_PNP_CAPABILITIES,
+ OID_PNP_QUERY_POWER,
+ OID_PNP_SET_POWER,
+
+#ifdef RNDIS_WAKEUP
+ /* wake up host */
+ OID_PNP_ENABLE_WAKE_UP,
+ OID_PNP_ADD_WAKE_UP_PATTERN,
+ OID_PNP_REMOVE_WAKE_UP_PATTERN,
+#endif /* RNDIS_WAKEUP */
+#endif /* RNDIS_PM */
+};
+
+
+/* NDIS Functions */
+static int gen_ndis_query_resp(int configNr, u32 OID, u8 *buf,
+ unsigned buf_len, rndis_resp_t *r)
+{
+ int retval = -ENOTSUPP;
+ u32 length = 4; /* usually */
+ __le32 *outbuf;
+ int i, count;
+ rndis_query_cmplt_type *resp;
+ rndis_params *params;
+
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_query_cmplt_type *) r->buf;
+
+ if (!resp)
+ return -ENOMEM;
+
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ if (buf_len) {
+ debug("query OID %08x value, len %d:\n", OID, buf_len);
+ for (i = 0; i < buf_len; i += 16) {
+ debug("%03d: %08x %08x %08x %08x\n", i,
+ get_unaligned_le32(&buf[i]),
+ get_unaligned_le32(&buf[i + 4]),
+ get_unaligned_le32(&buf[i + 8]),
+ get_unaligned_le32(&buf[i + 12]));
+ }
+ }
+#endif
+
+ /* response goes here, right after the header */
+ outbuf = (__le32 *) &resp[1];
+ resp->InformationBufferOffset = __constant_cpu_to_le32(16);
+
+ params = &rndis_per_dev_params[configNr];
+ switch (OID) {
+
+ /* general oids (table 4-1) */
+
+ /* mandatory */
+ case OID_GEN_SUPPORTED_LIST:
+ debug("%s: OID_GEN_SUPPORTED_LIST\n", __func__);
+ length = sizeof(oid_supported_list);
+ count = length / sizeof(u32);
+ for (i = 0; i < count; i++)
+ outbuf[i] = cpu_to_le32(oid_supported_list[i]);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_HARDWARE_STATUS:
+ debug("%s: OID_GEN_HARDWARE_STATUS\n", __func__);
+ /*
+ * Bogus question!
+ * Hardware must be ready to receive high level protocols.
+ * BTW:
+ * reddite ergo quae sunt Caesaris Caesari
+ * et quae sunt Dei Deo!
+ */
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_MEDIA_SUPPORTED:
+ debug("%s: OID_GEN_MEDIA_SUPPORTED\n", __func__);
+ *outbuf = cpu_to_le32(params->medium);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_MEDIA_IN_USE:
+ debug("%s: OID_GEN_MEDIA_IN_USE\n", __func__);
+ /* one medium, one transport... (maybe you do it better) */
+ *outbuf = cpu_to_le32(params->medium);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_MAXIMUM_FRAME_SIZE:
+ debug("%s: OID_GEN_MAXIMUM_FRAME_SIZE\n", __func__);
+ if (params->dev) {
+ *outbuf = cpu_to_le32(params->mtu);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_LINK_SPEED:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_LINK_SPEED\n", __func__);
+#endif
+ if (params->media_state == NDIS_MEDIA_STATE_DISCONNECTED)
+ *outbuf = __constant_cpu_to_le32(0);
+ else
+ *outbuf = cpu_to_le32(params->speed);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_TRANSMIT_BLOCK_SIZE:
+ debug("%s: OID_GEN_TRANSMIT_BLOCK_SIZE\n", __func__);
+ if (params->dev) {
+ *outbuf = cpu_to_le32(params->mtu);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_RECEIVE_BLOCK_SIZE:
+ debug("%s: OID_GEN_RECEIVE_BLOCK_SIZE\n", __func__);
+ if (params->dev) {
+ *outbuf = cpu_to_le32(params->mtu);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_VENDOR_ID:
+ debug("%s: OID_GEN_VENDOR_ID\n", __func__);
+ *outbuf = cpu_to_le32(params->vendorID);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_VENDOR_DESCRIPTION:
+ debug("%s: OID_GEN_VENDOR_DESCRIPTION\n", __func__);
+ length = strlen(params->vendorDescr);
+ memcpy(outbuf, params->vendorDescr, length);
+ retval = 0;
+ break;
+
+ case OID_GEN_VENDOR_DRIVER_VERSION:
+ debug("%s: OID_GEN_VENDOR_DRIVER_VERSION\n", __func__);
+ /* Created as LE */
+ *outbuf = rndis_driver_version;
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_CURRENT_PACKET_FILTER:
+ debug("%s: OID_GEN_CURRENT_PACKET_FILTER\n", __func__);
+ *outbuf = cpu_to_le32(*params->filter);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_MAXIMUM_TOTAL_SIZE:
+ debug("%s: OID_GEN_MAXIMUM_TOTAL_SIZE\n", __func__);
+ *outbuf = __constant_cpu_to_le32(RNDIS_MAX_TOTAL_SIZE);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_GEN_MEDIA_CONNECT_STATUS:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_MEDIA_CONNECT_STATUS\n", __func__);
+#endif
+ *outbuf = cpu_to_le32(params->media_state);
+ retval = 0;
+ break;
+
+ case OID_GEN_PHYSICAL_MEDIUM:
+ debug("%s: OID_GEN_PHYSICAL_MEDIUM\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+ /*
+ * The RNDIS specification is incomplete/wrong. Some versions
+ * of MS-Windows expect OIDs that aren't specified there. Other
+ * versions emit undefined RNDIS messages. DOCUMENT ALL THESE!
+ */
+ case OID_GEN_MAC_OPTIONS: /* from WinME */
+ debug("%s: OID_GEN_MAC_OPTIONS\n", __func__);
+ *outbuf = __constant_cpu_to_le32(
+ NDIS_MAC_OPTION_RECEIVE_SERIALIZED
+ | NDIS_MAC_OPTION_FULL_DUPLEX);
+ retval = 0;
+ break;
+
+ /* statistics OIDs (table 4-2) */
+
+ /* mandatory */
+ case OID_GEN_XMIT_OK:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_XMIT_OK\n", __func__);
+#endif
+ if (params->stats) {
+ *outbuf = cpu_to_le32(
+ params->stats->tx_packets -
+ params->stats->tx_errors -
+ params->stats->tx_dropped);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_RCV_OK:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_RCV_OK\n", __func__);
+#endif
+ if (params->stats) {
+ *outbuf = cpu_to_le32(
+ params->stats->rx_packets -
+ params->stats->rx_errors -
+ params->stats->rx_dropped);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_XMIT_ERROR:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_XMIT_ERROR\n", __func__);
+#endif
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->tx_errors);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_RCV_ERROR:
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: OID_GEN_RCV_ERROR\n", __func__);
+#endif
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_errors);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_GEN_RCV_NO_BUFFER:
+ debug("%s: OID_GEN_RCV_NO_BUFFER\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_dropped);
+ retval = 0;
+ }
+ break;
+
+#ifdef RNDIS_OPTIONAL_STATS
+ case OID_GEN_DIRECTED_BYTES_XMIT:
+ debug("%s: OID_GEN_DIRECTED_BYTES_XMIT\n", __func__);
+ /*
+ * Aunt Tilly's size of shoes
+ * minus antarctica count of penguins
+ * divided by weight of Alpha Centauri
+ */
+ if (params->stats) {
+ *outbuf = cpu_to_le32(
+ (params->stats->tx_packets -
+ params->stats->tx_errors -
+ params->stats->tx_dropped)
+ * 123);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_DIRECTED_FRAMES_XMIT:
+ debug("%s: OID_GEN_DIRECTED_FRAMES_XMIT\n", __func__);
+ /* dito */
+ if (params->stats) {
+ *outbuf = cpu_to_le32(
+ (params->stats->tx_packets -
+ params->stats->tx_errors -
+ params->stats->tx_dropped)
+ / 123);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_MULTICAST_BYTES_XMIT:
+ debug("%s: OID_GEN_MULTICAST_BYTES_XMIT\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->multicast * 1234);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_MULTICAST_FRAMES_XMIT:
+ debug("%s: OID_GEN_MULTICAST_FRAMES_XMIT\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->multicast);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_BROADCAST_BYTES_XMIT:
+ debug("%s: OID_GEN_BROADCAST_BYTES_XMIT\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->tx_packets/42*255);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_BROADCAST_FRAMES_XMIT:
+ debug("%s: OID_GEN_BROADCAST_FRAMES_XMIT\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->tx_packets / 42);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_DIRECTED_BYTES_RCV:
+ debug("%s: OID_GEN_DIRECTED_BYTES_RCV\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+ case OID_GEN_DIRECTED_FRAMES_RCV:
+ debug("%s: OID_GEN_DIRECTED_FRAMES_RCV\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+ case OID_GEN_MULTICAST_BYTES_RCV:
+ debug("%s: OID_GEN_MULTICAST_BYTES_RCV\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->multicast * 1111);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_MULTICAST_FRAMES_RCV:
+ debug("%s: OID_GEN_MULTICAST_FRAMES_RCV\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->multicast);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_BROADCAST_BYTES_RCV:
+ debug("%s: OID_GEN_BROADCAST_BYTES_RCV\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_packets/42*255);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_BROADCAST_FRAMES_RCV:
+ debug("%s: OID_GEN_BROADCAST_FRAMES_RCV\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_packets / 42);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_RCV_CRC_ERROR:
+ debug("%s: OID_GEN_RCV_CRC_ERROR\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_crc_errors);
+ retval = 0;
+ }
+ break;
+
+ case OID_GEN_TRANSMIT_QUEUE_LENGTH:
+ debug("%s: OID_GEN_TRANSMIT_QUEUE_LENGTH\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+#endif /* RNDIS_OPTIONAL_STATS */
+
+ /* ieee802.3 OIDs (table 4-3) */
+
+ /* mandatory */
+ case OID_802_3_PERMANENT_ADDRESS:
+ debug("%s: OID_802_3_PERMANENT_ADDRESS\n", __func__);
+ if (params->dev) {
+ length = ETH_ALEN;
+ memcpy(outbuf, params->host_mac, length);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_802_3_CURRENT_ADDRESS:
+ debug("%s: OID_802_3_CURRENT_ADDRESS\n", __func__);
+ if (params->dev) {
+ length = ETH_ALEN;
+ memcpy(outbuf, params->host_mac, length);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_802_3_MULTICAST_LIST:
+ debug("%s: OID_802_3_MULTICAST_LIST\n", __func__);
+ /* Multicast base address only */
+ *outbuf = __constant_cpu_to_le32(0xE0000000);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_802_3_MAXIMUM_LIST_SIZE:
+ debug("%s: OID_802_3_MAXIMUM_LIST_SIZE\n", __func__);
+ /* Multicast base address only */
+ *outbuf = __constant_cpu_to_le32(1);
+ retval = 0;
+ break;
+
+ case OID_802_3_MAC_OPTIONS:
+ debug("%s: OID_802_3_MAC_OPTIONS\n", __func__);
+ break;
+
+ /* ieee802.3 statistics OIDs (table 4-4) */
+
+ /* mandatory */
+ case OID_802_3_RCV_ERROR_ALIGNMENT:
+ debug("%s: OID_802_3_RCV_ERROR_ALIGNMENT\n", __func__);
+ if (params->stats) {
+ *outbuf = cpu_to_le32(params->stats->rx_frame_errors);
+ retval = 0;
+ }
+ break;
+
+ /* mandatory */
+ case OID_802_3_XMIT_ONE_COLLISION:
+ debug("%s: OID_802_3_XMIT_ONE_COLLISION\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+ /* mandatory */
+ case OID_802_3_XMIT_MORE_COLLISIONS:
+ debug("%s: OID_802_3_XMIT_MORE_COLLISIONS\n", __func__);
+ *outbuf = __constant_cpu_to_le32(0);
+ retval = 0;
+ break;
+
+#ifdef RNDIS_OPTIONAL_STATS
+ case OID_802_3_XMIT_DEFERRED:
+ debug("%s: OID_802_3_XMIT_DEFERRED\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_XMIT_MAX_COLLISIONS:
+ debug("%s: OID_802_3_XMIT_MAX_COLLISIONS\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_RCV_OVERRUN:
+ debug("%s: OID_802_3_RCV_OVERRUN\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_XMIT_UNDERRUN:
+ debug("%s: OID_802_3_XMIT_UNDERRUN\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_XMIT_HEARTBEAT_FAILURE:
+ debug("%s: OID_802_3_XMIT_HEARTBEAT_FAILURE\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_XMIT_TIMES_CRS_LOST:
+ debug("%s: OID_802_3_XMIT_TIMES_CRS_LOST\n", __func__);
+ /* TODO */
+ break;
+
+ case OID_802_3_XMIT_LATE_COLLISIONS:
+ debug("%s: OID_802_3_XMIT_LATE_COLLISIONS\n", __func__);
+ /* TODO */
+ break;
+#endif /* RNDIS_OPTIONAL_STATS */
+
+#ifdef RNDIS_PM
+ /* power management OIDs (table 4-5) */
+ case OID_PNP_CAPABILITIES:
+ debug("%s: OID_PNP_CAPABILITIES\n", __func__);
+
+ /* for now, no wakeup capabilities */
+ length = sizeof(struct NDIS_PNP_CAPABILITIES);
+ memset(outbuf, 0, length);
+ retval = 0;
+ break;
+ case OID_PNP_QUERY_POWER:
+ debug("%s: OID_PNP_QUERY_POWER D%d\n", __func__,
+ get_unaligned_le32(buf) - 1);
+ /*
+ * only suspend is a real power state, and
+ * it can't be entered by OID_PNP_SET_POWER...
+ */
+ length = 0;
+ retval = 0;
+ break;
+#endif
+
+ default:
+ debug("%s: query unknown OID 0x%08X\n", __func__, OID);
+ }
+ if (retval < 0)
+ length = 0;
+
+ resp->InformationBufferLength = cpu_to_le32(length);
+ r->length = length + sizeof *resp;
+ resp->MessageLength = cpu_to_le32(r->length);
+ return retval;
+}
+
+static int gen_ndis_set_resp(u8 configNr, u32 OID, u8 *buf, u32 buf_len,
+ rndis_resp_t *r)
+{
+ rndis_set_cmplt_type *resp;
+ int retval = -ENOTSUPP;
+ struct rndis_params *params;
+#if (defined(DEBUG) && defined(DEBUG_VERBOSE)) || defined(RNDIS_PM)
+ int i;
+#endif
+
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_set_cmplt_type *) r->buf;
+ if (!resp)
+ return -ENOMEM;
+
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ if (buf_len) {
+ debug("set OID %08x value, len %d:\n", OID, buf_len);
+ for (i = 0; i < buf_len; i += 16) {
+ debug("%03d: %08x %08x %08x %08x\n", i,
+ get_unaligned_le32(&buf[i]),
+ get_unaligned_le32(&buf[i + 4]),
+ get_unaligned_le32(&buf[i + 8]),
+ get_unaligned_le32(&buf[i + 12]));
+ }
+ }
+#endif
+
+ params = &rndis_per_dev_params[configNr];
+ switch (OID) {
+ case OID_GEN_CURRENT_PACKET_FILTER:
+
+ /*
+ * these NDIS_PACKET_TYPE_* bitflags are shared with
+ * cdc_filter; it's not RNDIS-specific
+ * NDIS_PACKET_TYPE_x == USB_CDC_PACKET_TYPE_x for x in:
+ * PROMISCUOUS, DIRECTED,
+ * MULTICAST, ALL_MULTICAST, BROADCAST
+ */
+ *params->filter = (u16) get_unaligned_le32(buf);
+ debug("%s: OID_GEN_CURRENT_PACKET_FILTER %08x\n",
+ __func__, *params->filter);
+
+ /*
+ * this call has a significant side effect: it's
+ * what makes the packet flow start and stop, like
+ * activating the CDC Ethernet altsetting.
+ */
+#ifdef RNDIS_PM
+update_linkstate:
+#endif
+ retval = 0;
+ if (*params->filter)
+ params->state = RNDIS_DATA_INITIALIZED;
+ else
+ params->state = RNDIS_INITIALIZED;
+ break;
+
+ case OID_802_3_MULTICAST_LIST:
+ /* I think we can ignore this */
+ debug("%s: OID_802_3_MULTICAST_LIST\n", __func__);
+ retval = 0;
+ break;
+#if 0
+ case OID_GEN_RNDIS_CONFIG_PARAMETER:
+ {
+ struct rndis_config_parameter *param;
+ param = (struct rndis_config_parameter *) buf;
+ debug("%s: OID_GEN_RNDIS_CONFIG_PARAMETER '%*s'\n",
+ __func__,
+ min(cpu_to_le32(param->ParameterNameLength), 80),
+ buf + param->ParameterNameOffset);
+ retval = 0;
+ }
+ break;
+#endif
+
+#ifdef RNDIS_PM
+ case OID_PNP_SET_POWER:
+ /*
+ * The only real power state is USB suspend, and RNDIS requests
+ * can't enter it; this one isn't really about power. After
+ * resuming, Windows forces a reset, and then SET_POWER D0.
+ * FIXME ... then things go batty; Windows wedges itself.
+ */
+ i = get_unaligned_le32(buf);
+ debug("%s: OID_PNP_SET_POWER D%d\n", __func__, i - 1);
+ switch (i) {
+ case NdisDeviceStateD0:
+ *params->filter = params->saved_filter;
+ goto update_linkstate;
+ case NdisDeviceStateD3:
+ case NdisDeviceStateD2:
+ case NdisDeviceStateD1:
+ params->saved_filter = *params->filter;
+ retval = 0;
+ break;
+ }
+ break;
+
+#ifdef RNDIS_WAKEUP
+ /*
+ * no wakeup support advertised, so wakeup OIDs always fail:
+ * - OID_PNP_ENABLE_WAKE_UP
+ * - OID_PNP_{ADD,REMOVE}_WAKE_UP_PATTERN
+ */
+#endif
+
+#endif /* RNDIS_PM */
+
+ default:
+ debug("%s: set unknown OID 0x%08X, size %d\n",
+ __func__, OID, buf_len);
+ }
+
+ return retval;
+}
+
+/*
+ * Response Functions
+ */
+
+static int rndis_init_response(int configNr, rndis_init_msg_type *buf)
+{
+ rndis_init_cmplt_type *resp;
+ rndis_resp_t *r;
+
+ if (!rndis_per_dev_params[configNr].dev)
+ return -ENOTSUPP;
+
+ r = rndis_add_response(configNr, sizeof(rndis_init_cmplt_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_init_cmplt_type *) r->buf;
+
+ resp->MessageType = __constant_cpu_to_le32(
+ REMOTE_NDIS_INITIALIZE_CMPLT);
+ resp->MessageLength = __constant_cpu_to_le32(52);
+ resp->RequestID = get_unaligned(&buf->RequestID); /* Still LE in msg buffer */
+ resp->Status = __constant_cpu_to_le32(RNDIS_STATUS_SUCCESS);
+ resp->MajorVersion = __constant_cpu_to_le32(RNDIS_MAJOR_VERSION);
+ resp->MinorVersion = __constant_cpu_to_le32(RNDIS_MINOR_VERSION);
+ resp->DeviceFlags = __constant_cpu_to_le32(RNDIS_DF_CONNECTIONLESS);
+ resp->Medium = __constant_cpu_to_le32(RNDIS_MEDIUM_802_3);
+ resp->MaxPacketsPerTransfer = __constant_cpu_to_le32(1);
+ resp->MaxTransferSize = cpu_to_le32(
+ rndis_per_dev_params[configNr].mtu
+ + ETHER_HDR_SIZE
+ + sizeof(struct rndis_packet_msg_type)
+ + 22);
+ resp->PacketAlignmentFactor = __constant_cpu_to_le32(0);
+ resp->AFListOffset = __constant_cpu_to_le32(0);
+ resp->AFListSize = __constant_cpu_to_le32(0);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+
+ return 0;
+}
+
+static int rndis_query_response(int configNr, rndis_query_msg_type *buf)
+{
+ rndis_query_cmplt_type *resp;
+ rndis_resp_t *r;
+
+ debug("%s: OID = %08X\n", __func__, get_unaligned_le32(&buf->OID));
+ if (!rndis_per_dev_params[configNr].dev)
+ return -ENOTSUPP;
+
+ /*
+ * we need more memory:
+ * gen_ndis_query_resp expects enough space for
+ * rndis_query_cmplt_type followed by data.
+ * oid_supported_list is the largest data reply
+ */
+ r = rndis_add_response(configNr,
+ sizeof(oid_supported_list) + sizeof(rndis_query_cmplt_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_query_cmplt_type *) r->buf;
+
+ resp->MessageType = __constant_cpu_to_le32(REMOTE_NDIS_QUERY_CMPLT);
+ resp->RequestID = get_unaligned(&buf->RequestID); /* Still LE in msg buffer */
+
+ if (gen_ndis_query_resp(configNr, get_unaligned_le32(&buf->OID),
+ get_unaligned_le32(&buf->InformationBufferOffset)
+ + 8 + (u8 *) buf,
+ get_unaligned_le32(&buf->InformationBufferLength),
+ r)) {
+ /* OID not supported */
+ resp->Status = __constant_cpu_to_le32(
+ RNDIS_STATUS_NOT_SUPPORTED);
+ resp->MessageLength = __constant_cpu_to_le32(sizeof *resp);
+ resp->InformationBufferLength = __constant_cpu_to_le32(0);
+ resp->InformationBufferOffset = __constant_cpu_to_le32(0);
+ } else
+ resp->Status = __constant_cpu_to_le32(RNDIS_STATUS_SUCCESS);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+ return 0;
+}
+
+static int rndis_set_response(int configNr, rndis_set_msg_type *buf)
+{
+ u32 BufLength, BufOffset;
+ rndis_set_cmplt_type *resp;
+ rndis_resp_t *r;
+
+ r = rndis_add_response(configNr, sizeof(rndis_set_cmplt_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_set_cmplt_type *) r->buf;
+
+ BufLength = get_unaligned_le32(&buf->InformationBufferLength);
+ BufOffset = get_unaligned_le32(&buf->InformationBufferOffset);
+
+#ifdef VERBOSE
+ debug("%s: Length: %d\n", __func__, BufLength);
+ debug("%s: Offset: %d\n", __func__, BufOffset);
+ debug("%s: InfoBuffer: ", __func__);
+
+ for (i = 0; i < BufLength; i++)
+ debug("%02x ", *(((u8 *) buf) + i + 8 + BufOffset));
+
+ debug("\n");
+#endif
+
+ resp->MessageType = __constant_cpu_to_le32(REMOTE_NDIS_SET_CMPLT);
+ resp->MessageLength = __constant_cpu_to_le32(16);
+ resp->RequestID = get_unaligned(&buf->RequestID); /* Still LE in msg buffer */
+ if (gen_ndis_set_resp(configNr, get_unaligned_le32(&buf->OID),
+ ((u8 *) buf) + 8 + BufOffset, BufLength, r))
+ resp->Status = __constant_cpu_to_le32(
+ RNDIS_STATUS_NOT_SUPPORTED);
+ else
+ resp->Status = __constant_cpu_to_le32(RNDIS_STATUS_SUCCESS);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+
+ return 0;
+}
+
+static int rndis_reset_response(int configNr, rndis_reset_msg_type *buf)
+{
+ rndis_reset_cmplt_type *resp;
+ rndis_resp_t *r;
+
+ r = rndis_add_response(configNr, sizeof(rndis_reset_cmplt_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_reset_cmplt_type *) r->buf;
+
+ resp->MessageType = __constant_cpu_to_le32(REMOTE_NDIS_RESET_CMPLT);
+ resp->MessageLength = __constant_cpu_to_le32(16);
+ resp->Status = __constant_cpu_to_le32(RNDIS_STATUS_SUCCESS);
+ /* resent information */
+ resp->AddressingReset = __constant_cpu_to_le32(1);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+
+ return 0;
+}
+
+static int rndis_keepalive_response(int configNr,
+ rndis_keepalive_msg_type *buf)
+{
+ rndis_keepalive_cmplt_type *resp;
+ rndis_resp_t *r;
+
+ /* host "should" check only in RNDIS_DATA_INITIALIZED state */
+
+ r = rndis_add_response(configNr, sizeof(rndis_keepalive_cmplt_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_keepalive_cmplt_type *) r->buf;
+
+ resp->MessageType = __constant_cpu_to_le32(
+ REMOTE_NDIS_KEEPALIVE_CMPLT);
+ resp->MessageLength = __constant_cpu_to_le32(16);
+ resp->RequestID = get_unaligned(&buf->RequestID); /* Still LE in msg buffer */
+ resp->Status = __constant_cpu_to_le32(RNDIS_STATUS_SUCCESS);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+
+ return 0;
+}
+
+
+/*
+ * Device to Host Comunication
+ */
+static int rndis_indicate_status_msg(int configNr, u32 status)
+{
+ rndis_indicate_status_msg_type *resp;
+ rndis_resp_t *r;
+
+ if (rndis_per_dev_params[configNr].state == RNDIS_UNINITIALIZED)
+ return -ENOTSUPP;
+
+ r = rndis_add_response(configNr,
+ sizeof(rndis_indicate_status_msg_type));
+ if (!r)
+ return -ENOMEM;
+ resp = (rndis_indicate_status_msg_type *) r->buf;
+
+ resp->MessageType = __constant_cpu_to_le32(
+ REMOTE_NDIS_INDICATE_STATUS_MSG);
+ resp->MessageLength = __constant_cpu_to_le32(20);
+ resp->Status = cpu_to_le32(status);
+ resp->StatusBufferLength = __constant_cpu_to_le32(0);
+ resp->StatusBufferOffset = __constant_cpu_to_le32(0);
+
+ if (rndis_per_dev_params[configNr].ack)
+ rndis_per_dev_params[configNr].ack(
+ rndis_per_dev_params[configNr].dev);
+ return 0;
+}
+
+int rndis_signal_connect(int configNr)
+{
+ rndis_per_dev_params[configNr].media_state
+ = NDIS_MEDIA_STATE_CONNECTED;
+ return rndis_indicate_status_msg(configNr,
+ RNDIS_STATUS_MEDIA_CONNECT);
+}
+
+int rndis_signal_disconnect(int configNr)
+{
+ rndis_per_dev_params[configNr].media_state
+ = NDIS_MEDIA_STATE_DISCONNECTED;
+
+#ifdef RNDIS_COMPLETE_SIGNAL_DISCONNECT
+ return rndis_indicate_status_msg(configNr,
+ RNDIS_STATUS_MEDIA_DISCONNECT);
+#else
+ return 0;
+#endif
+}
+
+void rndis_uninit(int configNr)
+{
+ u8 *buf;
+ u32 length;
+
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return;
+ rndis_per_dev_params[configNr].used = 0;
+ rndis_per_dev_params[configNr].state = RNDIS_UNINITIALIZED;
+
+ /* drain the response queue */
+ while ((buf = rndis_get_next_response(configNr, &length)))
+ rndis_free_response(configNr, buf);
+}
+
+void rndis_set_host_mac(int configNr, const u8 *addr)
+{
+ rndis_per_dev_params[configNr].host_mac = addr;
+}
+
+enum rndis_state rndis_get_state(int configNr)
+{
+ if (configNr >= RNDIS_MAX_CONFIGS || configNr < 0)
+ return -ENOTSUPP;
+ return rndis_per_dev_params[configNr].state;
+}
+
+/*
+ * Message Parser
+ */
+int rndis_msg_parser(u8 configNr, u8 *buf)
+{
+ u32 MsgType, MsgLength;
+ __le32 *tmp;
+ struct rndis_params *params;
+
+ debug("%s: configNr = %d, %p\n", __func__, configNr, buf);
+
+ if (!buf)
+ return -ENOMEM;
+
+ tmp = (__le32 *) buf;
+ MsgType = get_unaligned_le32(tmp++);
+ MsgLength = get_unaligned_le32(tmp++);
+
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return -ENOTSUPP;
+ params = &rndis_per_dev_params[configNr];
+
+ /*
+ * NOTE: RNDIS is *EXTREMELY* chatty ... Windows constantly polls for
+ * rx/tx statistics and link status, in addition to KEEPALIVE traffic
+ * and normal HC level polling to see if there's any IN traffic.
+ */
+
+ /* For USB: responses may take up to 10 seconds */
+ switch (MsgType) {
+ case REMOTE_NDIS_INITIALIZE_MSG:
+ debug("%s: REMOTE_NDIS_INITIALIZE_MSG\n", __func__);
+ params->state = RNDIS_INITIALIZED;
+ return rndis_init_response(configNr,
+ (rndis_init_msg_type *) buf);
+
+ case REMOTE_NDIS_HALT_MSG:
+ debug("%s: REMOTE_NDIS_HALT_MSG\n", __func__);
+ params->state = RNDIS_UNINITIALIZED;
+ return 0;
+
+ case REMOTE_NDIS_QUERY_MSG:
+ return rndis_query_response(configNr,
+ (rndis_query_msg_type *) buf);
+
+ case REMOTE_NDIS_SET_MSG:
+ return rndis_set_response(configNr,
+ (rndis_set_msg_type *) buf);
+
+ case REMOTE_NDIS_RESET_MSG:
+ debug("%s: REMOTE_NDIS_RESET_MSG\n", __func__);
+ return rndis_reset_response(configNr,
+ (rndis_reset_msg_type *) buf);
+
+ case REMOTE_NDIS_KEEPALIVE_MSG:
+ /* For USB: host does this every 5 seconds */
+#if defined(DEBUG) && defined(DEBUG_VERBOSE)
+ debug("%s: REMOTE_NDIS_KEEPALIVE_MSG\n", __func__);
+#endif
+ return rndis_keepalive_response(configNr,
+ (rndis_keepalive_msg_type *) buf);
+
+ default:
+ /*
+ * At least Windows XP emits some undefined RNDIS messages.
+ * In one case those messages seemed to relate to the host
+ * suspending itself.
+ */
+ debug("%s: unknown RNDIS message 0x%08X len %d\n",
+ __func__ , MsgType, MsgLength);
+ {
+ unsigned i;
+ for (i = 0; i < MsgLength; i += 16) {
+ debug("%03d: "
+ " %02x %02x %02x %02x"
+ " %02x %02x %02x %02x"
+ " %02x %02x %02x %02x"
+ " %02x %02x %02x %02x"
+ "\n",
+ i,
+ buf[i], buf[i+1],
+ buf[i+2], buf[i+3],
+ buf[i+4], buf[i+5],
+ buf[i+6], buf[i+7],
+ buf[i+8], buf[i+9],
+ buf[i+10], buf[i+11],
+ buf[i+12], buf[i+13],
+ buf[i+14], buf[i+15]);
+ }
+ }
+ break;
+ }
+
+ return -ENOTSUPP;
+}
+
+int rndis_register(int (*rndis_control_ack)(struct eth_device *))
+{
+ u8 i;
+
+ for (i = 0; i < RNDIS_MAX_CONFIGS; i++) {
+ if (!rndis_per_dev_params[i].used) {
+ rndis_per_dev_params[i].used = 1;
+ rndis_per_dev_params[i].ack = rndis_control_ack;
+ debug("%s: configNr = %d\n", __func__, i);
+ return i;
+ }
+ }
+ debug("%s failed\n", __func__);
+
+ return -1;
+}
+
+void rndis_deregister(int configNr)
+{
+ debug("%s: configNr = %d\n", __func__, configNr);
+
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return;
+ rndis_per_dev_params[configNr].used = 0;
+
+ return;
+}
+
+int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
+ struct net_device_stats *stats, u16 *cdc_filter)
+{
+ debug("%s: configNr = %d\n", __func__, configNr);
+ if (!dev || !stats)
+ return -1;
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return -1;
+
+ rndis_per_dev_params[configNr].dev = dev;
+ rndis_per_dev_params[configNr].stats = stats;
+ rndis_per_dev_params[configNr].mtu = mtu;
+ rndis_per_dev_params[configNr].filter = cdc_filter;
+
+ return 0;
+}
+
+int rndis_set_param_vendor(u8 configNr, u32 vendorID, const char *vendorDescr)
+{
+ debug("%s: configNr = %d\n", __func__, configNr);
+ if (!vendorDescr)
+ return -1;
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return -1;
+
+ rndis_per_dev_params[configNr].vendorID = vendorID;
+ rndis_per_dev_params[configNr].vendorDescr = vendorDescr;
+
+ return 0;
+}
+
+int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed)
+{
+ debug("%s: configNr = %d, %u %u\n", __func__, configNr, medium, speed);
+ if (configNr >= RNDIS_MAX_CONFIGS)
+ return -1;
+
+ rndis_per_dev_params[configNr].medium = medium;
+ rndis_per_dev_params[configNr].speed = speed;
+
+ return 0;
+}
+
+void rndis_add_hdr(void *buf, int length)
+{
+ struct rndis_packet_msg_type *header;
+
+ header = buf;
+ memset(header, 0, sizeof *header);
+ header->MessageType = __constant_cpu_to_le32(REMOTE_NDIS_PACKET_MSG);
+ header->MessageLength = cpu_to_le32(length + sizeof *header);
+ header->DataOffset = __constant_cpu_to_le32(36);
+ header->DataLength = cpu_to_le32(length);
+}
+
+void rndis_free_response(int configNr, u8 *buf)
+{
+ rndis_resp_t *r;
+ struct list_head *act, *tmp;
+
+ list_for_each_safe(act, tmp,
+ &(rndis_per_dev_params[configNr].resp_queue))
+ {
+ r = list_entry(act, rndis_resp_t, list);
+ if (r && r->buf == buf) {
+ list_del(&r->list);
+ free(r);
+ }
+ }
+}
+
+u8 *rndis_get_next_response(int configNr, u32 *length)
+{
+ rndis_resp_t *r;
+ struct list_head *act, *tmp;
+
+ if (!length)
+ return NULL;
+
+ list_for_each_safe(act, tmp,
+ &(rndis_per_dev_params[configNr].resp_queue))
+ {
+ r = list_entry(act, rndis_resp_t, list);
+ if (!r->send) {
+ r->send = 1;
+ *length = r->length;
+ return r->buf;
+ }
+ }
+
+ return NULL;
+}
+
+static rndis_resp_t *rndis_add_response(int configNr, u32 length)
+{
+ rndis_resp_t *r;
+
+ /* NOTE: this gets copied into ether.c USB_BUFSIZ bytes ... */
+ r = malloc(sizeof(rndis_resp_t) + length);
+ if (!r)
+ return NULL;
+
+ r->buf = (u8 *) (r + 1);
+ r->length = length;
+ r->send = 0;
+
+ list_add_tail(&r->list,
+ &(rndis_per_dev_params[configNr].resp_queue));
+ return r;
+}
+
+int rndis_rm_hdr(void *buf, int length)
+{
+ /* tmp points to a struct rndis_packet_msg_type */
+ __le32 *tmp = buf;
+ int offs, len;
+
+ /* MessageType, MessageLength */
+ if (__constant_cpu_to_le32(REMOTE_NDIS_PACKET_MSG)
+ != get_unaligned(tmp++))
+ return -EINVAL;
+ tmp++;
+
+ /* DataOffset, DataLength */
+ offs = get_unaligned_le32(tmp++) + 8 /* offset of DataOffset */;
+ if (offs != sizeof(struct rndis_packet_msg_type))
+ debug("%s: unexpected DataOffset: %d\n", __func__, offs);
+ if (offs >= length)
+ return -EOVERFLOW;
+
+ len = get_unaligned_le32(tmp++);
+ if (len + sizeof(struct rndis_packet_msg_type) != length)
+ debug("%s: unexpected DataLength: %d, packet length=%d\n",
+ __func__, len, length);
+
+ memmove(buf, buf + offs, len);
+
+ return offs;
+}
+
+int rndis_init(void)
+{
+ u8 i;
+
+ for (i = 0; i < RNDIS_MAX_CONFIGS; i++) {
+ rndis_per_dev_params[i].confignr = i;
+ rndis_per_dev_params[i].used = 0;
+ rndis_per_dev_params[i].state = RNDIS_UNINITIALIZED;
+ rndis_per_dev_params[i].media_state
+ = NDIS_MEDIA_STATE_DISCONNECTED;
+ INIT_LIST_HEAD(&(rndis_per_dev_params[i].resp_queue));
+ }
+
+ return 0;
+}
+
+void rndis_exit(void)
+{
+ /* Nothing to do */
+}
+
diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h
new file mode 100644
index 000000000..d9e3a7528
--- /dev/null
+++ b/drivers/usb/gadget/rndis.h
@@ -0,0 +1,260 @@
+/*
+ * RNDIS Definitions for Remote NDIS
+ *
+ * Authors: Benedikt Spranger, Pengutronix
+ * Robert Schwebel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This software was originally developed in conformance with
+ * Microsoft's Remote NDIS Specification License Agreement.
+ */
+
+#ifndef _USBGADGET_RNDIS_H
+#define _USBGADGET_RNDIS_H
+
+#include "ndis.h"
+
+/*
+ * By default rndis_signal_disconnect does not send status message about
+ * RNDIS disconnection to USB host (indicated as cable disconnected).
+ * Define RNDIS_COMPLETE_SIGNAL_DISCONNECT to send it.
+ * However, this will cause 1 sec delay on Ethernet device halt.
+ * Usually you do not need to define it. Mostly usable for debugging.
+ */
+
+#define RNDIS_MAXIMUM_FRAME_SIZE 1518
+#define RNDIS_MAX_TOTAL_SIZE 1558
+
+/* Remote NDIS Versions */
+#define RNDIS_MAJOR_VERSION 1
+#define RNDIS_MINOR_VERSION 0
+
+/* Status Values */
+#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
+#define RNDIS_STATUS_FAILURE 0xC0000001U /* Unspecified error */
+#define RNDIS_STATUS_INVALID_DATA 0xC0010015U /* Invalid data */
+#define RNDIS_STATUS_NOT_SUPPORTED 0xC00000BBU /* Unsupported request */
+#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000BU /* Device connected */
+#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000CU /* Device disconnected */
+/*
+ * For all not specified status messages:
+ * RNDIS_STATUS_Xxx -> NDIS_STATUS_Xxx
+ */
+
+/* Message Set for Connectionless (802.3) Devices */
+#define REMOTE_NDIS_PACKET_MSG 0x00000001U
+#define REMOTE_NDIS_INITIALIZE_MSG 0x00000002U /* Initialize device */
+#define REMOTE_NDIS_HALT_MSG 0x00000003U
+#define REMOTE_NDIS_QUERY_MSG 0x00000004U
+#define REMOTE_NDIS_SET_MSG 0x00000005U
+#define REMOTE_NDIS_RESET_MSG 0x00000006U
+#define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007U
+#define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008U
+
+/* Message completion */
+#define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002U
+#define REMOTE_NDIS_QUERY_CMPLT 0x80000004U
+#define REMOTE_NDIS_SET_CMPLT 0x80000005U
+#define REMOTE_NDIS_RESET_CMPLT 0x80000006U
+#define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008U
+
+/* Device Flags */
+#define RNDIS_DF_CONNECTIONLESS 0x00000001U
+#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002U
+
+#define RNDIS_MEDIUM_802_3 0x00000000U
+
+/* from drivers/net/sk98lin/h/skgepnmi.h */
+#define OID_PNP_CAPABILITIES 0xFD010100
+#define OID_PNP_SET_POWER 0xFD010101
+#define OID_PNP_QUERY_POWER 0xFD010102
+#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103
+#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104
+#define OID_PNP_ENABLE_WAKE_UP 0xFD010106
+
+
+typedef struct rndis_init_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 MajorVersion;
+ __le32 MinorVersion;
+ __le32 MaxTransferSize;
+} rndis_init_msg_type;
+
+typedef struct rndis_init_cmplt_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 Status;
+ __le32 MajorVersion;
+ __le32 MinorVersion;
+ __le32 DeviceFlags;
+ __le32 Medium;
+ __le32 MaxPacketsPerTransfer;
+ __le32 MaxTransferSize;
+ __le32 PacketAlignmentFactor;
+ __le32 AFListOffset;
+ __le32 AFListSize;
+} rndis_init_cmplt_type;
+
+typedef struct rndis_halt_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+} rndis_halt_msg_type;
+
+typedef struct rndis_query_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 OID;
+ __le32 InformationBufferLength;
+ __le32 InformationBufferOffset;
+ __le32 DeviceVcHandle;
+} rndis_query_msg_type;
+
+typedef struct rndis_query_cmplt_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 Status;
+ __le32 InformationBufferLength;
+ __le32 InformationBufferOffset;
+} rndis_query_cmplt_type;
+
+typedef struct rndis_set_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 OID;
+ __le32 InformationBufferLength;
+ __le32 InformationBufferOffset;
+ __le32 DeviceVcHandle;
+} rndis_set_msg_type;
+
+typedef struct rndis_set_cmplt_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 Status;
+} rndis_set_cmplt_type;
+
+typedef struct rndis_reset_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 Reserved;
+} rndis_reset_msg_type;
+
+typedef struct rndis_reset_cmplt_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 Status;
+ __le32 AddressingReset;
+} rndis_reset_cmplt_type;
+
+typedef struct rndis_indicate_status_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 Status;
+ __le32 StatusBufferLength;
+ __le32 StatusBufferOffset;
+} rndis_indicate_status_msg_type;
+
+typedef struct rndis_keepalive_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+} rndis_keepalive_msg_type;
+
+typedef struct rndis_keepalive_cmplt_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 RequestID;
+ __le32 Status;
+} rndis_keepalive_cmplt_type;
+
+struct rndis_packet_msg_type {
+ __le32 MessageType;
+ __le32 MessageLength;
+ __le32 DataOffset;
+ __le32 DataLength;
+ __le32 OOBDataOffset;
+ __le32 OOBDataLength;
+ __le32 NumOOBDataElements;
+ __le32 PerPacketInfoOffset;
+ __le32 PerPacketInfoLength;
+ __le32 VcHandle;
+ __le32 Reserved;
+} __attribute__ ((packed));
+
+struct rndis_config_parameter {
+ __le32 ParameterNameOffset;
+ __le32 ParameterNameLength;
+ __le32 ParameterType;
+ __le32 ParameterValueOffset;
+ __le32 ParameterValueLength;
+};
+
+/* implementation specific */
+enum rndis_state {
+ RNDIS_UNINITIALIZED,
+ RNDIS_INITIALIZED,
+ RNDIS_DATA_INITIALIZED,
+};
+
+typedef struct rndis_resp_t {
+ struct list_head list;
+ u8 *buf;
+ u32 length;
+ int send;
+} rndis_resp_t;
+
+typedef struct rndis_params {
+ u8 confignr;
+ u8 used;
+ u16 saved_filter;
+ enum rndis_state state;
+ u32 medium;
+ u32 speed;
+ u32 media_state;
+
+ const u8 *host_mac;
+ u16 *filter;
+ struct eth_device *dev;
+ struct net_device_stats *stats;
+ int mtu;
+
+ u32 vendorID;
+ const char *vendorDescr;
+ int (*ack)(struct eth_device *);
+ struct list_head resp_queue;
+} rndis_params;
+
+/* RNDIS Message parser and other useless functions */
+int rndis_msg_parser(u8 configNr, u8 *buf);
+enum rndis_state rndis_get_state(int configNr);
+int rndis_register(int (*rndis_control_ack)(struct eth_device *));
+void rndis_deregister(int configNr);
+int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
+ struct net_device_stats *stats, u16 *cdc_filter);
+int rndis_set_param_vendor(u8 configNr, u32 vendorID,
+ const char *vendorDescr);
+int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed);
+void rndis_add_hdr(void *bug, int length);
+int rndis_rm_hdr(void *bug, int length);
+u8 *rndis_get_next_response(int configNr, u32 *length);
+void rndis_free_response(int configNr, u8 *buf);
+
+void rndis_uninit(int configNr);
+int rndis_signal_connect(int configNr);
+int rndis_signal_disconnect(int configNr);
+extern void rndis_set_host_mac(int configNr, const u8 *addr);
+
+int rndis_init(void);
+void rndis_exit(void);
+
+#endif /* _USBGADGET_RNDIS_H */
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 6eb38a413..70c02c9de 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -319,6 +319,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
uint32_t endpt, token, usbsts;
uint32_t c, toggle;
uint32_t cmd;
+ int timeout;
int ret = 0;
debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
@@ -447,6 +448,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
/* Wait for TDs to be processed. */
ts = get_timer(0);
vtd = td;
+ timeout = USB_TIMEOUT_MS(pipe);
do {
/* Invalidate dcache */
ehci_invalidate_dcache(&qh_list);
@@ -454,7 +456,13 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
if (!(token & 0x80))
break;
WATCHDOG_RESET();
- } while (get_timer(ts) < CONFIG_SYS_HZ);
+ } while (get_timer(ts) < timeout);
+
+ /* Check that the TD processing happened */
+ if (token & 0x80) {
+ printf("EHCI timed out on TD - token=%#x\n", token);
+ goto fail;
+ }
/* Disable async schedule. */
cmd = ehci_readl(&hcor->or_usbcmd);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index d24697896..bc8bb2061 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1524,12 +1524,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* ohci_dump_status(&gohci); */
#endif
- /* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipebulk(pipe))
- timeout = BULK_TO;
- else
- timeout = 1000;
+ timeout = USB_TIMEOUT_MS(pipe);
/* wait for it to complete */
for (;;) {
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index e6b60cf28..bf2fdd668 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -136,6 +136,7 @@
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -654,12 +655,12 @@
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 8a6b8d06b..7d9368c5a 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -59,6 +59,7 @@
#define MIGO_R_FLASH_BASE_1 (0xA0000000)
#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index bf3474004..982cdd501 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -344,7 +344,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
@@ -357,7 +356,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index e7f37f59f..711dd3c3a 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -63,6 +63,8 @@
#define AP325RXA_FLASH_BASE_1 (0xA0000000)
#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
/* undef to save memory */
#define CONFIG_SYS_LONGHELP
/* Monitor Command Prompt */
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
index 706365f80..fd35f3e11 100644
--- a/include/configs/aspenite.h
+++ b/include/configs/aspenite.h
@@ -41,6 +41,13 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
@@ -53,6 +60,7 @@
* to enable certain macros
*/
#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
/*
* Environment variables configurations
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
new file mode 100644
index 000000000..638af5e33
--- /dev/null
+++ b/include/configs/dkb.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_DKB_H
+#define __CONFIG_DKB_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
+#define CONFIG_PANTHEON 1 /* SOC Family Name */
+#define CONFIG_MACH_TTC_DKB 1 /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#define CONFIG_ENV_SIZE 0x20000 /* 64k */
+
+#endif /* __CONFIG_DKB_H */
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
new file mode 100644
index 000000000..f7609d71a
--- /dev/null
+++ b/include/configs/dlvision-10g.h
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME dlvsion-10g
+#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
+#define CONFIG_SYS_FPGA1_BASE 0x7f200000
+#define CONFIG_SYS_LATCH_BASE 0x7f300000
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+ (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+ (k ? 0x2000 : 0x1000)
+
+#define CONFIG_SYS_FPGA_COUNT 2
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffcf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(2) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(4) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_64MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA0) */
+#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(5) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 2 (FPGA1) */
+#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(6) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 78cab29e8..34a9d6866 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -30,125 +30,117 @@
#define __CONFIG_H
/*
- * Stuff still to be dealt with -
- */
-#define CONFIG_RTC_MC146818
-
-/*
* High Level Configuration Options
* (easy to change)
*/
-#define DEBUG_PARSER
-
-#define CONFIG_X86 1 /* Intel X86 CPU */
-#define CONFIG_SYS_SC520 1 /* AMD SC520 */
+#define CONFIG_X86
+#define CONFIG_SYS_SC520
#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define CONFIG_LAST_STAGE_INIT 1
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
-/*
- * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+/*-----------------------------------------------------------------------
+ * Watchdog Configuration
+ * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
* bottom (processor) board MUST be removed!
*/
#undef CONFIG_WATCHDOG
#define CONFIG_HW_WATCHDOG
- /*-----------------------------------------------------------------------
- * Serial Configuration
- */
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 1843200
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
+#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
+#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
#define CONFIG_SYS_NS16550_PORT_MAPPED
- /*-----------------------------------------------------------------------
- * Video Configuration
- */
-#undef CONFIG_VIDEO /* No Video Hardware */
-#undef CONFIG_CFB_CONSOLE
-
-/*
- * Size of malloc() pool
+/*-----------------------------------------------------------------------
+ * Video Configuration
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
/*-----------------------------------------------------------------------
* Command line configuration.
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_BDI /* bdinfo */
-#define CONFIG_CMD_BOOTD /* bootd */
-#define CONFIG_CMD_CONSOLE /* coninfo */
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
-#define CONFIG_CMD_IMI /* iminfo */
-#define CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_IRQ /* IRQ Information */
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
-#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
-#undef CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_PCI /* PCI support */
-#define CONFIG_CMD_PING /* ICMP echo support */
-#define CONFIG_CMD_RUN /* run command in env variable */
-#define CONFIG_CMD_SAVEENV /* saveenv */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-#define CONFIG_CMD_SOURCE /* "source" command Support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-
-#define CONFIG_BOOTDELAY 15
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
-/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY 15
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 115200
+#define CONFIG_KGDB_SER_INDEX 2
#endif
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "boot > "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* SDRAM Configuration
*/
-#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
-#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
+#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
+#define CONFIG_NR_DRAM_BANKS 4
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_REFRESH_RATE
#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
@@ -156,106 +148,465 @@
/*-----------------------------------------------------------------------
* CPU Features
*/
-#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
-#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
-#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
-#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
-#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
-#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
- * in the SC520 on the CDP */
+#define CONFIG_SYS_SC520_HIGH_SPEED 0
+#define CONFIG_SYS_SC520_RESET
+#define CONFIG_SYS_SC520_TIMER
+#undef CONFIG_SYS_GENERIC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_NUM_IRQS 16
+#define CONFIG_SYS_NUM_IRQS 16
/*-----------------------------------------------------------------------
- * Memory organization
+ * Memory organization:
+ * 32kB Stack
+ * 256kB Monitor
*/
-#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
-#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
-#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
-#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
-#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
+#define CONFIG_SYS_STACK_SIZE 0x8000
+#define CONFIG_SYS_CAR_ADDR 0x19200000
+#define CONFIG_SYS_CAR_SIZE 0x00004000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
+ CONFIG_SYS_CAR_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+/* Address of temporary Global Data */
+#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
- /*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
+ * 16MB StrataFlash #1 @ 0x10000000
+ * 16MB StrataFlash #2 @ 0x11000000
+ */
+#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE_1, \
- CONFIG_SYS_FLASH_BASE_2}
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_FLASH_BASE 0x38000000
+#define CONFIG_SYS_FLASH_BASE_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE_2 0x11000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2}
#define CONFIG_SYS_FLASH_EMPTY_INFO
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-
- /*-----------------------------------------------------------------------
- * Environment configuration
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
/* Redundant Copy */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
-
-
- /*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-#define CONFIG_SYS_FIRST_PCI_IRQ 10
-#define CONFIG_SYS_SECOND_PCI_IRQ 9
-#define CONFIG_SYS_THIRD_PCI_IRQ 11
-#define CONFIG_SYS_FORTH_PCI_IRQ 15
-
- /*
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_SYS_FIRST_PCI_IRQ 10
+#define CONFIG_SYS_SECOND_PCI_IRQ 9
+#define CONFIG_SYS_THIRD_PCI_IRQ 11
+#define CONFIG_SYS_FORTH_PCI_IRQ 15
+
+/*-----------------------------------------------------------------------
* Network device (TRL8100B) support
*/
#define CONFIG_NET_MULTI
#define CONFIG_RTL8139
/*-----------------------------------------------------------------------
- * FPGA configuration
- */
-#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
-#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
-#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
-#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
-#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
-#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
-#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
-#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
-#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
-#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
-#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
-
-#ifndef __ASSEMBLER__
-extern unsigned long ip;
-
-#define PRINTIP asm ("call 0\n" \
- "0:\n" \
- "pop %%eax\n" \
- "movl %%eax, %0\n" \
- :"=r"(ip) \
- : /* No Input Registers */ \
- :"%eax"); \
- printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
+ * BOOTCS Control (for AM29LV040B-120JC)
+ *
+ * 000 0 00 0 000 11 0 011 }- 0x0033
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 3 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 3 Wait States (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Non-Paged Mode
+ * | | +------------------ 8 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
+
+/*-----------------------------------------------------------------------
+ * ROMCS Control (for E28F128J3A-150 StrataFlash)
+ *
+ * 000 0 01 1 000 01 0 101 }- 0x0615
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 5 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 1 Wait State (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Paged Mode
+ * | | +------------------ 16 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
+#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
+
+/*-----------------------------------------------------------------------
+ * SC520 General Purpose Bus configuration
+ *
+ * Chip Select Offset 1 Clock Cycle
+ * Chip Select Pulse Width 8 Clock Cycles
+ * Chip Select Read Offset 2 Clock Cycles
+ * Chip Select Read Width 6 Clock Cycles
+ * Chip Select Write Offset 2 Clock Cycles
+ * Chip Select Write Width 6 Clock Cycles
+ * Chip Select Recovery Time 2 Clock Cycles
+ *
+ * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
+ *
+ * |<-------------General Purpose Bus Cycle---------------->|
+ * | |
+ * ----------------------\__________________/------------------
+ * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
+ *
+ * ------------------------\_______________/-------------------
+ * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
+ *
+ * --------------------------\_______________/-----------------
+ * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
+ *
+ * ________/-----------\_______________________________________
+ * |<--->|<--------->|
+ * ^ ^
+ * (GPALEOFF + 1) |
+ * |
+ * (GPALEW + 1)
+ */
+#define CONFIG_SYS_SC520_GPCSOFF 0x00
+#define CONFIG_SYS_SC520_GPCSPW 0x07
+#define CONFIG_SYS_SC520_GPRDOFF 0x01
+#define CONFIG_SYS_SC520_GPRDW 0x05
+#define CONFIG_SYS_SC520_GPWROFF 0x01
+#define CONFIG_SYS_SC520_GPWRW 0x05
+#define CONFIG_SYS_SC520_GPCSRT 0x01
+
+/*-----------------------------------------------------------------------
+ * SC520 Programmable I/O configuration
+ *
+ * Pin Mode Dir. Description
+ * ----------------------------------------------------------------------
+ * PIO0 PIO Output Unused
+ * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
+ * PIO2 PIO Output Auxiliary power output enable
+ * PIO3 GPAEN Output GP Bus Address Enable
+ * PIO4 PIO Output Top Board Enable (active low)
+ * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
+ * PIO6 PIO Input Data output of Power Supply ADC
+ * PIO7 PIO Output Clock input to Power Supply ADC
+ * PIO8 PIO Output Chip Select input of Power Supply ADC
+ * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
+ * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
+ * PIO11 PIO Input StrataFlash 1 Status
+ * PIO12 PIO Input StrataFlash 2 Status
+ * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
+ * PIO14 PIO Input Low Input Voltage Warning (active low)
+ * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
+ * PIO16 PIO Input Power Fail
+ * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
+ * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
+ * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
+ * PIO20 GPIRQ3 Input UART D IRQ
+ * PIO21 GPIRQ2 Input UART C IRQ
+ * PIO22 GPIRQ1 Input UART B IRQ
+ * PIO23 GPIRQ0 Input UART A IRQ
+ * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
+ * PIO25 PIO Input Battery OK Indication
+ * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
+ * PIO27 GPCS0# Output SRAM 1 Chip Select
+ * PIO28 PIO Input Top Board UART CTS
+ * PIO29 PIO Output FPGA Program Mode (active low)
+ * PIO30 PIO Input FPGA Initialised (active low)
+ * PIO31 PIO Input FPGA Done (active low)
+ */
+#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
+#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
+#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
+#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
+
+/*-----------------------------------------------------------------------
+ * PIO Pin defines
+ */
+#define CONFIG_SYS_ENET_AUX_PWR 0x0004
+#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
+#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
+#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
+#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
+#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
+#define CONFIG_SYS_ENET_SF1_MODE 0x0200
+#define CONFIG_SYS_ENET_SF2_MODE 0x0400
+#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
+#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
+#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
+#define CONFIG_SYS_ENET_WATCHDOG 0x8000
+
+#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
+#define CONFIG_SYS_ENET_BAT_OK 0x0200
+#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
+#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
+#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
+#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
+
+/*-----------------------------------------------------------------------
+ * Chip Select Pin Function Select
+ *
+ * 1 1 1 1 1 0 0 0 }- 0xf8
+ * | | | | | | | |
+ * | | | | | | | +--- Reserved
+ * | | | | | | +----- GPCS1_SEL = ROMCS1#
+ * | | | | | +------- GPCS2_SEL = ROMCS2#
+ * | | | | +--------- GPCS3_SEL = GPCS3
+ * | | | +----------- GPCS4_SEL = GPCS4
+ * | | +------------- GPCS5_SEL = GPCS5
+ * | +--------------- GPCS6_SEL = GPCS6
+ * +----------------- GPCS7_SEL = GPCS7
+ */
+#define CONFIG_SYS_SC520_CSPFS 0xf8
+
+/*-----------------------------------------------------------------------
+ * Clock Select (CLKTIMER[CLKTEST] pin)
+ *
+ * 0 111 00 1 0 }- 0x72
+ * | \ / \| | |
+ * | | | | +--- Pin Disabled
+ * | | | +----- Pin is an output
+ * | | +------- Reserved
+ * | +----------- Disabled (pin stays Low)
+ * +-------------- Reserved
+ */
+#define CONFIG_SYS_SC520_CLKSEL 0x72
+
+/*-----------------------------------------------------------------------
+ * Address Decode Control
+ *
+ * 0 00 0 0 0 0 0 }- 0x00
+ * | \| | | | | |
+ * | | | | | | +--- Integrated UART 1 is enabled
+ * | | | | | +----- Integrated UART 2 is enabled
+ * | | | | +------- Integrated RTC is enabled
+ * | | | +--------- Reserved
+ * | | +----------- I/O Hole accesses are forwarded to the external GP bus
+ * | +------------- Reserved
+ * +---------------- Write-protect violations do not generate an IRQ
+ */
+#define CONFIG_SYS_SC520_ADDDECCTL 0x00
+
+/*-----------------------------------------------------------------------
+ * UART Control
+ *
+ * 00000 1 1 1 }- 0x07
+ * \___/ | | |
+ * | | | +--- Transmit TC interrupt enable
+ * | | +----- Receive TC interrupt enable
+ * | +------- 1.8432 MHz
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_UART1CTL 0x07
+#define CONFIG_SYS_SC520_UART2CTL 0x07
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Control
+ *
+ * 00000 1 1 0 }- 0x06
+ * \___/ | | |
+ * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
+ * | | +----- The system arbiter operates in concurrent mode
+ * | +------- Park the PCI bus on the last master that acquired the bus
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBCTL 0x06
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 00000000000 0 0 0 1 1 }- 0x06
+ * \_________/ | | | | |
+ * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
+ * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
+ * | | | +------- PCI master REQ2 disabled
+ * | | +--------- PCI master REQ3 disabled
+ * | +----------- PCI master REQ4 disabled
+ * +------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 0 0000 0 00 0000 1 000 }- 0x06
+ * | \__/ | \| \__/ | \_/
+ * | | | | | | +---- Reserved
+ * | | | | | +------- Enable CPU-to-PCI bus write posting
+ * | | | | +---------- Reserved
+ * | | | +-------------- PCI bus reads to SDRAM are not automatically
+ * | | | retried
+ * | | +----------------- Target read FIFOs are not snooped during write
+ * | | transactions
+ * | +-------------------- Reserved
+ * +------------------------ Deassert the PCI bus reset signal
+ */
+#define CONFIG_SYS_SC520_HBCTL 0x08
+
+/*-----------------------------------------------------------------------
+ * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
+ * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x38000000
+ * | | | | | +----------------------- 512kB Region Size
+ * | | | | | ((7 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled (So it can be
+ * | | | reprogrammed!)
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
+
+/*-----------------------------------------------------------------------
+ * Cache-As-RAM (Targets Boot Flash)
+ *
+ * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
+ * \ / | | | | \--+--/ \-------+--------/
+ * | | | | | | +------------ Start at 0x19200000
+ * | | | | | +------------------------- 64k Region Size
+ * | | | | | ((15 + 1) * 4kB)
+ * | | | | +------------------------------ 4kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Prevented
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
+
+/*-----------------------------------------------------------------------
+ * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
+ *
+ * 001 110 0 000100000 0001000000000000 }- 0x38201000
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x00001000
+ * | | | +------------------------ 33 Bytes (0x20 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
+
+/*-----------------------------------------------------------------------
+ * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
+ * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
+ *
+ * 010 101 0 0000000 100000000000000000 }- 0x54020000
+ * 010 111 0 0000000 100000000000000001 }- 0x5c020001
+ * \ / \ / | \--+--/ \-------+--------/
+ * | | | | +------------ Start at 0x200000000
+ * | | | | 0x200010000
+ * | | | +------------------------- 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4k Page Size
+ * | +--------------------------------- GPCS5
+ * | GPCS7
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
+#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
+
+/*-----------------------------------------------------------------------
+ * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
+ * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
+ * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
+ * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
+ *
+ * 001 000 0 000000111 0001001111111000 }- 0x200713f8
+ * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
+ * 001 011 0 000000111 0001001011111000 }- 0x300711f8
+ * 001 011 0 000000111 0001001011111000 }- 0x340710f8
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x013f8
+ * | | | | 0x012f8
+ * | | | | 0x011f8
+ * | | | | 0x010f8
+ * | | | +------------------------ 33 Bytes (32 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
+#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
+#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
+#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
+
+/*-----------------------------------------------------------------------
+ * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
+ * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
+ *
+ * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
+ * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x10000000
+ * | | | | | | 0x11000000
+ * | | | | | +----------------------- 16MB Region Size
+ * | | | | | ((255 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- ROMCS1
+ * ROMCS2
+ */
+#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
+#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
+
+/*-----------------------------------------------------------------------
+ * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
+ * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
+ *
+ * 010 000 1 00000001111 01100100000000 }- 0x4203d900
+ * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
+ * \ / \ / | \----+----/ \-----+------/
+ * | | | | +---------- Start at 0x19000000
+ * | | | | 0x19100000
+ * | | | +----------------------- 1MB Region Size
+ * | | | ((15 + 1) * 64kB)
+ * | | +------------------------------ 64kB Page Size
+ * | +--------------------------------- GPCS0
+ * | GPCS3
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
+#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
+
+/*-----------------------------------------------------------------------
+ * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
+ *
+ * 010 100 0 00000000 11000000100000000 }- 0x50018100
+ * \ / \ / | \---+--/ \-------+-------/
+ * | | | | +----------- Start at 0x18100000
+ * | | | +------------------------ 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4kB Page Size
+ * | +--------------------------------- GPCS4
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 26389ed02..ad3c335b0 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -56,6 +56,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF0 1
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
new file mode 100644
index 000000000..d004f319d
--- /dev/null
+++ b/include/configs/harmony.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
+#define V_PROMPT "Tegra2 (Harmony) # "
+#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTD
+
+/* UARTD: keyboard satellite board UART, default */
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+/* UARTA: debug board UART */
+#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
+#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index b7ba6f4fb..f2950e8d5 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -31,9 +31,12 @@
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
-#ifndef CPU_CLOCK_RATE
-/* allowed values: 100000000, 133000000, and 150000000 */
-#define CPU_CLOCK_RATE 150000000 /* default: 150 MHz clock for the MIPS core */
+/*
+ * Clock for the MIPS core (MHz)
+ * allowed values: 100000000, 133000000, and 150000000 (default)
+ */
+#ifndef CONFIG_CPU_CLOCK_RATE
+#define CONFIG_CPU_CLOCK_RATE 150000000
#endif
#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
diff --git a/include/configs/io.h b/include/configs/io.h
index a66c70436..9d2a87d22 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -229,13 +229,15 @@
#define CONFIG_SYS_EBC_PB1CR 0x7f318000
/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02025080
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
-#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
+
+#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5e61b1137..9fcc6430c 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -131,6 +131,12 @@ int fpga_gpio_get(int pin);
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
/*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
+/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
@@ -231,13 +237,15 @@ int fpga_gpio_get(int pin);
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFB858000
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE 0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02825080
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
-#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
+#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
@@ -249,4 +257,11 @@ int fpga_gpio_get(int pin);
#define CONFIG_SYS_LATCH1_RESET 0xffff
#define CONFIG_SYS_LATCH1_BOOT 0xffff
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+
#endif /* __CONFIG_H */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 311f52402..f32899f47 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -58,6 +58,8 @@
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
/* Memory */
#define CONFIG_SYS_SDRAM_BASE 0x8C000000
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 5304237a7..dd79b2d92 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -52,6 +52,7 @@
#define MS7720SE_FLASH_BASE_1 0xA0000000
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 1ddadf696..c8d04f7cf 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -57,6 +57,7 @@
#define MS7722SE_FLASH_BASE_1 (0xA0000000)
#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 9b43acb20..16fb0d4fe 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -64,6 +64,7 @@
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 97b69713a..a8937dde2 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -37,54 +37,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
-
-/* ====> Kirkwood Platform Common Definations */
-#if defined(CONFIG_KIRKWOOD)
-#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
-#define MV_UART_CONSOLE_BASE KW_UART0_BASE
-#define MV_SATA_BASE KW_SATA_BASE
-#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
-#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
-
-/* ====> ARMADA100 Platform Common Definations */
-#elif defined (CONFIG_ARMADA100)
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE ARMD1_MFPR_BASE
-#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-/*
- * There is no internal RAM in ARMADA100, using DRAM
- * TBD: dcache to be used for this
- */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-#else
-#error "Unsupported SoC Platform..."
-#endif
/*
* Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
@@ -138,31 +90,6 @@
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
- * NAND configuration
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL 1
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-#endif
-
-/*
- * SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH 1
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
-#endif
-
-/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
@@ -176,9 +103,7 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
-#ifndef CONFIG_ARMADA100 /* will be removed latter */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
-#endif /* CONFIG_ARMADA100 */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
@@ -199,27 +124,32 @@
#endif
#endif /* CONFIG_NR_DRAM_BANKS */
+/* ====> Include platform Common Definations */
+#include <asm/arch/config.h>
+
+/* ====> Include driver Common Definations */
/*
- * Ethernet Driver configuration
+ * Common NAND configuration
*/
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* specify more that one ports available */
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
-#endif /* CONFIG_CMD_NET */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+/*
+ * Common SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_MACRONIX 1
+#endif
/*
- * USB/EHCI
+ * Common USB/EHCI configuration
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_KIRKWOOD
-#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
@@ -227,44 +157,9 @@
#endif /* CONFIG_CMD_USB */
/*
- * IDE Support on SATA ports
- */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_CMD_EXT2
-#define CONFIG_MVSATA_IDE
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT1
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
-#endif /* CONFIG_CMD_IDE */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
-/*
* File system
*/
-#ifndef CONFIG_ARMADA100 /* will be removed latter */
+#ifdef CONFIG_SYS_MVFS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_FAT
@@ -275,6 +170,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
-#endif /* CONFIG_ARMADA100 */
+#endif
#endif /* _MV_COMMON_H */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 3b90a0162..86c758f2a 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -154,6 +154,13 @@
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
/*-----------------------------------------------------------------------
* FLASH and environment organization
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 8689513fb..5534b4992 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -40,6 +40,7 @@
#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
+#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 256
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 802416f3e..e1febf36b 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -60,6 +60,7 @@
/* check for keypress on bootdelay==0 */
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
#define CONFIG_SYS_SDRAM_BASE (0x08000000)
#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index b3feaa8c3..0802140ea 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -54,6 +54,7 @@
#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE 0x0C7C0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
new file mode 100644
index 000000000..fd8756070
--- /dev/null
+++ b/include/configs/seaboard.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
+#define V_PROMPT "Tegra2 (SeaBoard) # "
+#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD
+#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
new file mode 100644
index 000000000..9799767c5
--- /dev/null
+++ b/include/configs/sh7757lcr.h
@@ -0,0 +1,146 @@
+/*
+ * Configuation settings for the sh7757lcr board
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH7757LCR_H
+#define __SH7757LCR_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_SH_32BIT 1
+#define CONFIG_CPU_SH7757 1
+#define CONFIG_SH7757LCR 1
+
+#define CONFIG_SYS_TEXT_BASE 0x8ef80000
+#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define SH7757LCR_SDRAM_BASE (0x80000000)
+#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
+#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
+#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF2 1
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 224 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ (128 + 16) * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 1
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
+
+#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
+#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
+#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
+#define SH7757LCR_ETHERNET_MAC_SIZE 17
+#define SH7757LCR_ETHERNET_NUM_CH 2
+#define BOARD_LATE_INIT 1
+
+/* Gigabit Ether */
+#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
+
+/* SPI */
+#define CONFIG_SH_SPI 1
+#define CONFIG_SH_SPI_BASE 0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO 1
+
+/* SH7757 board */
+#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
+#define SH7757LCR_GRA_OFFSET 0x1f000000
+#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
+#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
+#define SH7757LCR_PCIEBRG_ADDR 0x00090000
+#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_ADDR (0x00080000)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 48000000
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+#endif /* __SH7757LCR_H */
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 209cb88f3..6a08413aa 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -56,6 +56,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF2 1
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index a95a75962..8eb9a1299 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -63,6 +63,7 @@
/* MEMORY */
#if defined(CONFIG_SH_32BIT)
+#define CONFIG_SYS_TEXT_BASE 0x8FF80000
/* 0x40000000 - 0x47FFFFFF does not use */
#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
@@ -72,6 +73,7 @@
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xa6000000)
#else
+#define CONFIG_SYS_TEXT_BASE 0x0FF80000
#define SH7785LCR_SDRAM_BASE (0x08000000)
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
diff --git a/include/configs/shmin.h b/include/configs/shmin.h
index bee7e4437..3a008f0dc 100644
--- a/include/configs/shmin.h
+++ b/include/configs/shmin.h
@@ -56,6 +56,7 @@
#define SHMIN_SDRAM_BASE (0x8C000000)
#define SHMIN_FLASH_BASE_1 (0xA0000000)
+#define CONFIG_SYS_TEXT_BASE 0x8DFB0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
new file mode 100644
index 000000000..4f4374a74
--- /dev/null
+++ b/include/configs/tegra2-common.h
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA2_COMMON_H
+#define __TEGRA2_COMMON_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
+#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
+#define CONFIG_L2_OFF /* No L2 cache */
+
+#include <asm/arch/tegra2.h> /* get chip and board defs */
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
+
+/*
+ * PllX Configuration
+ */
+#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS /* NFS support */
+#undef CONFIG_CMD_NET /* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTOCOMPLETE
+
+#define CONFIG_SYS_NO_FLASH
+
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttyS0,115200n8\0" \
+ "mem=" TEGRA2_SYSMEM "\0" \
+ "smpflag=smp\0" \
+
+#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
+#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ * than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKBASE 0x2800000 /* 40MB */
+#define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
+
+#define CONFIG_SYS_TEXT_BASE 0x00E08000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __TEGRA2_COMMON_H */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 4894969bf..325ac8c73 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -109,17 +109,20 @@
/*
* Only Premium/Platinum have ethernet support right now
*/
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
+ !defined(CONFIG_VCT_SMALL_IMAGE)
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#else
#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
#endif
/*
* Only Premium/Platinum have USB-EHCI support right now
*/
-#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
+ !defined(CONFIG_VCT_SMALL_IMAGE)
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#endif
diff --git a/include/environment.h b/include/environment.h
index 082b3e15b..53d92df1f 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -107,7 +107,8 @@ extern unsigned long nand_env_oob_offset;
#ifdef CONFIG_ENV_IS_EMBEDDED
# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
!defined(CONFIG_ENV_IS_IN_NAND) && \
- !defined(CONFIG_ENV_IS_IN_ONENAND)
+ !defined(CONFIG_ENV_IS_IN_ONENAND) && \
+ !defined(CONFIG_ENV_IS_IN_SPI_FLASH)
# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
# endif
#endif
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
new file mode 100644
index 000000000..1fccd27cc
--- /dev/null
+++ b/include/gdsys_fpga.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GDSYS_FPGA_H
+#define __GDSYS_FPGA_H
+
+enum {
+ FPGA_STATE_DONE_FAILED = 1 << 0,
+ FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+};
+
+int get_fpga_state(unsigned dev);
+void print_fpga_state(unsigned dev);
+
+typedef struct ihs_gpio {
+ u16 read;
+ u16 clear;
+ u16 set;
+} ihs_gpio_t;
+
+typedef struct ihs_i2c {
+ u16 write_mailbox;
+ u16 write_mailbox_ext;
+ u16 read_mailbox;
+ u16 read_mailbox_ext;
+} ihs_i2c_t;
+
+typedef struct ihs_osd {
+ u16 version;
+ u16 features;
+ u16 control;
+ u16 xy_size;
+} ihs_osd_t;
+
+#ifdef CONFIG_IO
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_features; /* 0x0004 */
+ u16 fpga_version; /* 0x0006 */
+ u16 reserved_0[5]; /* 0x0008 */
+ u16 quad_serdes_reset; /* 0x0012 */
+ u16 reserved_1[8181]; /* 0x0014 */
+ u16 reflection_high; /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_IOCON
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[6]; /* 0x0008 */
+ ihs_gpio_t gpio; /* 0x0014 */
+ u16 mpc3w_control; /* 0x001a */
+ u16 reserved_1[19]; /* 0x001c */
+ u16 videocontrol; /* 0x0042 */
+ u16 reserved_2[93]; /* 0x0044 */
+ u16 reflection_high; /* 0x00fe */
+ ihs_osd_t osd; /* 0x0100 */
+ u16 reserved_3[892]; /* 0x0108 */
+ u16 videomem; /* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_DLVISION_10G
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[10]; /* 0x0008 */
+ u16 extended_interrupt; /* 0x001c */
+ u16 reserved_1[9]; /* 0x001e */
+ ihs_i2c_t i2c; /* 0x0030 */
+ u16 reserved_2[35]; /* 0x0038 */
+ u16 reflection_high; /* 0x007e */
+ u16 reserved_3[15]; /* 0x0080 */
+ u16 videocontrol; /* 0x009e */
+ u16 reserved_4[176]; /* 0x00a0 */
+ ihs_osd_t osd; /* 0x0200 */
+ u16 reserved_5[764]; /* 0x0208 */
+ u16 videomem; /* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#endif
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
new file mode 100644
index 000000000..870d8b41f
--- /dev/null
+++ b/include/linux/netdevice.h
@@ -0,0 +1,65 @@
+/*
+ * INET An implementation of the TCP/IP protocol suite for the LINUX
+ * operating system. INET is implemented using the BSD Socket
+ * interface as the means of communication with the user level.
+ *
+ * Definitions for the Interfaces handler.
+ *
+ * Version: @(#)dev.h 1.0.10 08/12/93
+ *
+ * Authors: Ross Biro
+ * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
+ * Corey Minyard <wf-rch!minyard@relay.EU.net>
+ * Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
+ * Alan Cox, <Alan.Cox@linux.org>
+ * Bjorn Ekwall. <bj0rn@blox.se>
+ * Pekka Riikonen <priikone@poseidon.pspt.fi>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Moved to /usr/include/linux for NET3
+ */
+#ifndef _LINUX_NETDEVICE_H
+#define _LINUX_NETDEVICE_H
+
+/*
+ * Network device statist