aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-iop13xx/include/mach/adma.h
blob: 5722e86f2174a93aa4b91975f2c2b608a5b4a1af (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
/*
 * Copyright(c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */
#ifndef _ADMA_H
#define _ADMA_H
#include <linux/types.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/hardware/iop_adma.h>

#define ADMA_ACCR(chan)	(chan->mmr_base + 0x0)
#define ADMA_ACSR(chan)	(chan->mmr_base + 0x4)
#define ADMA_ADAR(chan)	(chan->mmr_base + 0x8)
#define ADMA_IIPCR(chan)	(chan->mmr_base + 0x18)
#define ADMA_IIPAR(chan)	(chan->mmr_base + 0x1c)
#define ADMA_IIPUAR(chan)	(chan->mmr_base + 0x20)
#define ADMA_ANDAR(chan)	(chan->mmr_base + 0x24)
#define ADMA_ADCR(chan)	(chan->mmr_base + 0x28)
#define ADMA_CARMD(chan)	(chan->mmr_base + 0x2c)
#define ADMA_ABCR(chan)	(chan->mmr_base + 0x30)
#define ADMA_DLADR(chan)	(chan->mmr_base + 0x34)
#define ADMA_DUADR(chan)	(chan->mmr_base + 0x38)
#define ADMA_SLAR(src, chan)	(chan->mmr_base + (0x3c + (src << 3)))
#define ADMA_SUAR(src, chan)	(chan->mmr_base + (0x40 + (src << 3)))

struct iop13xx_adma_src {
	u32 src_addr;
	union {
		u32 upper_src_addr;
		struct {
			unsigned int pq_upper_src_addr:24;
			unsigned int pq_dmlt:8;
		};
	};
};

struct iop13xx_adma_desc_ctrl {
	unsigned int int_en:1;
	unsigned int xfer_dir:2;
	unsigned int src_select:4;
	unsigned int zero_result:1;
	unsigned int block_fill_en:1;
	unsigned int crc_gen_en:1;
	unsigned int crc_xfer_dis:1;
	unsigned int crc_seed_fetch_dis:1;
	unsigned int status_write_back_en:1;
	unsigned int endian_swap_en:1;
	unsigned int reserved0:2;
	unsigned int pq_update_xfer_en:1;
	unsigned int dual_xor_en:1;
	unsigned int pq_xfer_en:1;
	unsigned int p_xfer_dis:1;
	unsigned int reserved1:10;
	unsigned int relax_order_en:1;
	unsigned int no_snoop_en:1;
};

struct iop13xx_adma_byte_count {
	unsigned int byte_count:24;
	unsigned int host_if:3;
	unsigned int reserved:2;
	unsigned int zero_result_err_q:1;
	unsigned int zero_result_err:1;
	unsigned int tx_complete:1;
};

struct iop13xx_adma_desc_hw {
	u32 next_desc;
	union {
		u32 desc_ctrl;
		struct iop13xx_adma_desc_ctrl desc_ctrl_field;
	};
	union {
		u32 crc_addr;
		u32 block_fill_data;
		u32 q_dest_addr;
	};
	union {
		u32 byte_count;
		struct iop13xx_adma_byte_count byte_count_field;
	};
	union {
		u32 dest_addr;
		u32 p_dest_addr;
	};
	union {
		u32 upper_dest_addr;
		u32 pq_upper_dest_addr;
	};
	struct iop13xx_adma_src src[1];
};

struct iop13xx_adma_desc_dual_xor {
	u32 next_desc;
	u32 desc_ctrl;
	u32 reserved;
	u32 byte_count;
	u32 h_dest_addr;
	u32 h_upper_dest_addr;
	u32 src0_addr;
	u32 upper_src0_addr;
	u32 src1_addr;
	u32 upper_src1_addr;
	u32 h_src_addr;
	u32 h_upper_src_addr;
	u32 d_src_addr;
	u32 d_upper_src_addr;
	u32 d_dest_addr;
	u32 d_upper_dest_addr;
};

struct iop13xx_adma_desc_pq_update {
	u32 next_desc;
	u32 desc_ctrl;
	u32 reserved;
	u32 byte_count;
	u32 p_dest_addr;
	u32 p_upper_dest_addr;
	u32 src0_addr;
	u32 upper_src0_addr;
	u32 src1_addr;
	u32 upper_src1_addr;
	u32 p_src_addr;
	u32 p_upper_src_addr;
	u32 q_src_addr;
	struct {
		unsigned int q_upper_src_addr:24;
		unsigned int q_dmlt:8;
	};
	u32 q_dest_addr;
	u32 q_upper_dest_addr;
};

static inline int iop_adma_get_max_xor(void)
{
	return 16;
}

static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
{
	return __raw_readl(ADMA_ADAR(chan));
}

static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
						u32 next_desc_addr)
{
	__raw_writel(next_desc_addr, ADMA_ANDAR(chan));
}

#define ADMA_STATUS_BUSY (1 << 13)

static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
{
	if (__raw_readl(ADMA_ACSR(chan)) &
		ADMA_STATUS_BUSY)
		return 1;
	else
		return 0;
}

static inline int
iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
{
	return 1;
}
#define iop_desc_is_aligned(x, y) 1

static inline int
iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
{
	*slots_per_op = 1;
	return 1;
}

#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)

static inline int
iop_chan_memset_slot_count(size_t len, int *slots_per_op)
{
	*slots_per_op = 1;
	return 1;
}

static inline int
iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
{
	static const char slot_count_table[] = { 1, 2, 2, 2,
						 2, 3, 3, 3,
						 3, 4, 4, 4,
						 4, 5, 5, 5,
						};
	*slots_per_op = slot_count_table[src_cnt - 1];
	return *slots_per_op;
}

#define ADMA_MAX_BYTE_COUNT	(16 * 1024 * 1024)
#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)

static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	return hw_desc->dest_addr;
}

static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	return hw_desc->byte_count_field.byte_count;
}

static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan,
					int src_idx)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	return hw_desc->src[src_idx].src_addr;
}

static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	return hw_desc->desc_ctrl_field.src_select + 1;
}

static inline void
iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	union {
		u32 value;
		struct iop13xx_adma_desc_ctrl field;
	} u_desc_ctrl;

	u_desc_ctrl.value = 0;
	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
	hw_desc->desc_ctrl = u_desc_ctrl.value;
	hw_desc->crc_addr = 0;
}

static inline void
iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	union {
		u32 value;
		struct iop13xx_adma_desc_ctrl field;
	} u_desc_ctrl;

	u_desc_ctrl.value = 0;
	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
	u_desc_ctrl.field.block_fill_en = 1;
	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
	hw_desc->desc_ctrl = u_desc_ctrl.value;
	hw_desc->crc_addr = 0;
}

/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
static inline void
iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
		  unsigned long flags)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	union {
		u32 value;
		struct iop13xx_adma_desc_ctrl field;
	} u_desc_ctrl;

	u_desc_ctrl.value = 0;
	u_desc_ctrl.field.src_select = src_cnt - 1;
	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
	hw_desc->desc_ctrl = u_desc_ctrl.value;
	hw_desc->crc_addr = 0;

}
#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)

/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
static inline int
iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
		       unsigned long flags)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	union {
		u32 value;
		struct iop13xx_adma_desc_ctrl field;
	} u_desc_ctrl;

	u_desc_ctrl.value = 0;
	u_desc_ctrl.field.src_select = src_cnt - 1;
	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
	u_desc_ctrl.field.zero_result = 1;
	u_desc_ctrl.field.status_write_back_en = 1;
	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
	hw_desc->desc_ctrl = u_desc_ctrl.value;
	hw_desc->crc_addr = 0;

	return 1;
}

static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan,
					u32 byte_count)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	hw_desc->byte_count = byte_count;
}

static inline void
iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
{
	int slots_per_op = desc->slots_per_op;
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
	int i = 0;

	if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
		hw_desc->byte_count = len;
	} else {
		do {
			iter = iop_hw_desc_slot_idx(hw_desc, i);
			iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
			len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
			i += slots_per_op;
		} while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);

		if (len) {
			iter = iop_hw_desc_slot_idx(hw_desc, i);
			iter->byte_count = len;
		}
	}
}


static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
					struct iop_adma_chan *chan,
					dma_addr_t addr)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	hw_desc->dest_addr = addr;
	hw_desc->upper_dest_addr = 0;
}

static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
					dma_addr_t addr)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	hw_desc->src[0].src_addr = addr;
	hw_desc->src[0].upper_src_addr = 0;
}

static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
					int src_idx, dma_addr_t addr)
{
	int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
	int i = 0;

	do {
		iter = iop_hw_desc_slot_idx(hw_desc, i);
		iter->src[src_idx].src_addr = addr;
		iter->src[src_idx].upper_src_addr = 0;
		slot_cnt -= slots_per_op;
		if (slot_cnt) {
			i += slots_per_op;
			addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
		}
	} while (slot_cnt);
}

static inline void
iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
	struct iop_adma_chan *chan)
{
	iop_desc_init_memcpy(desc, 1);
	iop_desc_set_byte_count(desc, chan, 0);
	iop_desc_set_dest_addr(desc, chan, 0);
	iop_desc_set_memcpy_src_addr(desc, 0);
}

#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr

static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
					u32 next_desc_addr)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;

	iop_paranoia(hw_desc->next_desc);
	hw_desc->next_desc = next_desc_addr;
}

static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	return hw_desc->next_desc;
}

static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	hw_desc->next_desc = 0;
}

static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
						u32 val)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	hw_desc->block_fill_data = val;
}

static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
{
	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
	struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
	struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;

	BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));

	if (desc_ctrl.pq_xfer_en)
		return byte_count.zero_result_err_q;
	else
		return byte_count.zero_result_err;
}

static inline void iop_chan_append(struct iop_adma_chan *chan)
{
	u32 adma_accr;

	adma_accr = __raw_readl(ADMA_ACCR(chan));
	adma_accr |= 0x2;
	__raw_writel(adma_accr, ADMA_ACCR(chan));
}

static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
{
	return __raw_readl(ADMA_ACSR(chan));
}

static inline void iop_chan_disable(struct iop_adma_chan *chan)
{
	u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
	adma_chan_ctrl &= ~0x1;
	__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
}

static inline void iop_chan_enable(struct iop_adma_chan *chan)
{
	u32 adma_chan_ctrl;

	adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
	adma_chan_ctrl |= 0x1;
	__raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
}

static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
{
	u32 status = __raw_readl(ADMA_ACSR(chan));
	status &= (1 << 12);
	__raw_writel(status, ADMA_ACSR(chan));
}

static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
{
	u32 status = __raw_readl(ADMA_ACSR(chan));
	status &= (1 << 11);
	__raw_writel(status, ADMA_ACSR(chan));
}

static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
{
	u32 status = __raw_readl(ADMA_ACSR(chan));
	status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
	__raw_writel(status, ADMA_ACSR(chan));
}

static inline int
iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
{
	return test_bit(9, &status);
}

static inline int
iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
{
	return test_bit(5, &status);
}

static inline int
iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
{
	return test_bit(4, &status);
}

static inline int
iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
{
	return test_bit(3, &status);
}

static inline int
iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
{
	return 0;
}

static inline int
iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
{
	return 0;
}

static inline int
iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
{
	return 0;
}

#endif /* _ADMA_H */