1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/unified.h>
#define SRC_SCR 0x000
#define SRC_SIMR 0x018
#define SRC_GPR1 0x020
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE 22
#define BP_SRC_SCR_VPU_RST 2
#define BP_SRC_SCR_IPU1_RST 3
#define BP_SRC_SCR_IPU2_RST 12
#define BP_SRC_SIMR_VPU_MASK 1
#define BP_SRC_SIMR_IPU1_MASK 2
#define BP_SRC_SIMR_IPU2_MASK 4
void __iomem *src_base;
#ifndef CONFIG_SMP
#define cpu_logical_map(cpu) 0
#endif
void imx_reset_vpu(void)
{
u32 val;
/* mask interrupt due to vpu passed reset */
val = readl_relaxed(src_base + SRC_SIMR);
val |= (1 << BP_SRC_SIMR_VPU_MASK);
writel_relaxed(val, src_base + SRC_SIMR);
val = readl_relaxed(src_base + SRC_SCR);
val |= (1 << BP_SRC_SCR_VPU_RST); /* reset vpu */
writel_relaxed(val, src_base + SRC_SCR);
while (readl_relaxed(src_base + SRC_SCR) &
(1 << BP_SRC_SCR_VPU_RST))
;
}
void imx_reset_ipu(int ipu)
{
u32 val;
u32 scr_off = ipu ? BP_SRC_SCR_IPU2_RST : BP_SRC_SCR_IPU1_RST;
u32 simr_off = ipu ? BP_SRC_SIMR_IPU2_MASK : BP_SRC_SIMR_IPU1_MASK;
/* mask interrupt due to ipu passed reset */
val = readl_relaxed(src_base + SRC_SIMR);
val |= (1 << simr_off);
writel_relaxed(val, src_base + SRC_SIMR);
/* reset the IPU */
val = readl_relaxed(src_base + SRC_SCR);
val |= (1 << scr_off);
writel_relaxed(val, src_base + SRC_SCR);
while (readl_relaxed(src_base + SRC_SCR) &
(1 << scr_off))
;
}
void imx_enable_cpu(int cpu, bool enable)
{
u32 mask, val;
cpu = cpu_logical_map(cpu);
mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
val = readl_relaxed(src_base + SRC_SCR);
val = enable ? val | mask : val & ~mask;
writel_relaxed(val, src_base + SRC_SCR);
}
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
writel_relaxed(BSYM(virt_to_phys(jump_addr)),
src_base + SRC_GPR1 + cpu * 8);
}
void __init imx_src_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
src_base = of_iomap(np, 0);
WARN_ON(!src_base);
}
|