aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-imx/clock-imx6q.c
blob: 0dc408552ea66f6c7721e7a23a68ff285fc5d98b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/div64.h>
#include <asm/mach/map.h>
#include <mach/clock.h>
#include <mach/common.h>
#include <mach/hardware.h>

#define PLL_BASE		IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
#define PLL1_SYS		(PLL_BASE + 0x000)
#define PLL2_BUS		(PLL_BASE + 0x030)
#define PLL3_USB_OTG		(PLL_BASE + 0x010)
#define PLL4_AUDIO		(PLL_BASE + 0x070)
#define PLL5_VIDEO		(PLL_BASE + 0x0a0)
#define PLL6_MLB		(PLL_BASE + 0x0d0)
#define PLL7_USB_HOST		(PLL_BASE + 0x020)
#define PLL8_ENET		(PLL_BASE + 0x0e0)
#define PFD_480			(PLL_BASE + 0x0f0)
#define PFD_528			(PLL_BASE + 0x100)
#define PLL_NUM_OFFSET		0x010
#define PLL_DENOM_OFFSET	0x020

#define PFD0			7
#define PFD1			15
#define PFD2			23
#define PFD3			31
#define PFD_FRAC_MASK		0x3f

#define BM_PLL_BYPASS			(0x1 << 16)
#define BM_PLL_ENABLE			(0x1 << 13)
#define BM_PLL_POWER_DOWN		(0x1 << 12)
#define BM_PLL_LOCK			(0x1 << 31)
#define BP_PLL_SYS_DIV_SELECT		0
#define BM_PLL_SYS_DIV_SELECT		(0x7f << 0)
#define BP_PLL_BUS_DIV_SELECT		0
#define BM_PLL_BUS_DIV_SELECT		(0x1 << 0)
#define BP_PLL_USB_DIV_SELECT		0
#define BM_PLL_USB_DIV_SELECT		(0x3 << 0)
#define BP_PLL_AV_DIV_SELECT		0
#define BM_PLL_AV_DIV_SELECT		(0x7f << 0)
#define BP_PLL_ENET_DIV_SELECT		0
#define BM_PLL_ENET_DIV_SELECT		(0x3 << 0)
#define BM_PLL_ENET_EN_PCIE		(0x1 << 19)
#define BM_PLL_ENET_EN_SATA		(0x1 << 20)

#define CCM_BASE	IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
#define CCR		(CCM_BASE + 0x00)
#define CCDR		(CCM_BASE + 0x04)
#define CSR		(CCM_BASE + 0x08)
#define CCSR		(CCM_BASE + 0x0c)
#define CACRR		(CCM_BASE + 0x10)
#define CBCDR		(CCM_BASE + 0x14)
#define CBCMR		(CCM_BASE + 0x18)
#define CSCMR1		(CCM_BASE + 0x1c)
#define CSCMR2		(CCM_BASE + 0x20)
#define CSCDR1		(CCM_BASE + 0x24)
#define CS1CDR		(CCM_BASE + 0x28)
#define CS2CDR		(CCM_BASE + 0x2c)
#define CDCDR		(CCM_BASE + 0x30)
#define CHSCCDR		(CCM_BASE + 0x34)
#define CSCDR2		(CCM_BASE + 0x38)
#define CSCDR3		(CCM_BASE + 0x3c)
#define CSCDR4		(CCM_BASE + 0x40)
#define CWDR		(CCM_BASE + 0x44)
#define CDHIPR		(CCM_BASE + 0x48)
#define CDCR		(CCM_BASE + 0x4c)
#define CTOR		(CCM_BASE + 0x50)
#define CLPCR		(CCM_BASE + 0x54)
#define CISR		(CCM_BASE + 0x58)
#define CIMR		(CCM_BASE + 0x5c)
#define CCOSR		(CCM_BASE + 0x60)
#define CGPR		(CCM_BASE + 0x64)
#define CCGR0		(CCM_BASE + 0x68)
#define CCGR1		(CCM_BASE + 0x6c)
#define CCGR2		(CCM_BASE + 0x70)
#define CCGR3		(CCM_BASE + 0x74)
#define CCGR4		(CCM_BASE + 0x78)
#define CCGR5		(CCM_BASE + 0x7c)
#define CCGR6		(CCM_BASE + 0x80)
#define CCGR7		(CCM_BASE + 0x84)
#define CMEOR		(CCM_BASE + 0x88)

#define CG0		0
#define CG1		2
#define CG2		4
#define CG3		6
#define CG4		8
#define CG5		10
#define CG6		12
#define CG7		14
#define CG8		16
#define CG9		18
#define CG10		20
#define CG11		22
#define CG12		24
#define CG13		26
#define CG14		28
#define CG15		30

#define BM_CCSR_PLL1_SW_SEL		(0x1 << 2)
#define BM_CCSR_STEP_SEL		(0x1 << 8)

#define BP_CACRR_ARM_PODF		0
#define BM_CACRR_ARM_PODF		(0x7 << 0)

#define BP_CBCDR_PERIPH2_CLK2_PODF	0
#define BM_CBCDR_PERIPH2_CLK2_PODF	(0x7 << 0)
#define BP_CBCDR_MMDC_CH1_AXI_PODF	3
#define BM_CBCDR_MMDC_CH1_AXI_PODF	(0x7 << 3)
#define BP_CBCDR_AXI_SEL		6
#define BM_CBCDR_AXI_SEL		(0x3 << 6)
#define BP_CBCDR_IPG_PODF		8
#define BM_CBCDR_IPG_PODF		(0x3 << 8)
#define BP_CBCDR_AHB_PODF		10
#define BM_CBCDR_AHB_PODF		(0x7 << 10)
#define BP_CBCDR_AXI_PODF		16
#define BM_CBCDR_AXI_PODF		(0x7 << 16)
#define BP_CBCDR_MMDC_CH0_AXI_PODF	19
#define BM_CBCDR_MMDC_CH0_AXI_PODF	(0x7 << 19)
#define BP_CBCDR_PERIPH_CLK_SEL		25
#define BM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
#define BP_CBCDR_PERIPH2_CLK_SEL	26
#define BM_CBCDR_PERIPH2_CLK_SEL	(0x1 << 26)
#define BP_CBCDR_PERIPH_CLK2_PODF	27
#define BM_CBCDR_PERIPH_CLK2_PODF	(0x7 << 27)

#define BP_CBCMR_GPU2D_AXI_SEL		0
#define BM_CBCMR_GPU2D_AXI_SEL		(0x1 << 0)
#define BP_CBCMR_GPU3D_AXI_SEL		1
#define BM_CBCMR_GPU3D_AXI_SEL		(0x1 << 1)
#define BP_CBCMR_GPU3D_CORE_SEL		4
#define BM_CBCMR_GPU3D_CORE_SEL		(0x3 << 4)
#define BP_CBCMR_GPU3D_SHADER_SEL	8
#define BM_CBCMR_GPU3D_SHADER_SEL	(0x3 << 8)
#define BP_CBCMR_PCIE_AXI_SEL		10
#define BM_CBCMR_PCIE_AXI_SEL		(0x1 << 10)
#define BP_CBCMR_VDO_AXI_SEL		11
#define BM_CBCMR_VDO_AXI_SEL		(0x1 << 11)
#define BP_CBCMR_PERIPH_CLK2_SEL	12
#define BM_CBCMR_PERIPH_CLK2_SEL	(0x3 << 12)
#define BP_CBCMR_VPU_AXI_SEL		14
#define BM_CBCMR_VPU_AXI_SEL		(0x3 << 14)
#define BP_CBCMR_GPU2D_CORE_SEL		16
#define BM_CBCMR_GPU2D_CORE_SEL		(0x3 << 16)
#define BP_CBCMR_PRE_PERIPH_CLK_SEL	18
#define BM_CBCMR_PRE_PERIPH_CLK_SEL	(0x3 << 18)
#define BP_CBCMR_PERIPH2_CLK2_SEL	20
#define BM_CBCMR_PERIPH2_CLK2_SEL	(0x1 << 20)
#define BP_CBCMR_PRE_PERIPH2_CLK_SEL	21
#define BM_CBCMR_PRE_PERIPH2_CLK_SEL	(0x3 << 21)
#define BP_CBCMR_GPU2D_CORE_PODF	23
#define BM_CBCMR_GPU2D_CORE_PODF	(0x7 << 23)
#define BP_CBCMR_GPU3D_CORE_PODF	26
#define BM_CBCMR_GPU3D_CORE_PODF	(0x7 << 26)
#define BP_CBCMR_GPU3D_SHADER_PODF	29
#define BM_CBCMR_GPU3D_SHADER_PODF	(0x7 << 29)

#define BP_CSCMR1_PERCLK_PODF		0
#define BM_CSCMR1_PERCLK_PODF		(0x3f << 0)
#define BP_CSCMR1_SSI1_SEL		10
#define BM_CSCMR1_SSI1_SEL		(0x3 << 10)
#define BP_CSCMR1_SSI2_SEL		12
#define BM_CSCMR1_SSI2_SEL		(0x3 << 12)
#define BP_CSCMR1_SSI3_SEL		14
#define BM_CSCMR1_SSI3_SEL		(0x3 << 14)
#define BP_CSCMR1_USDHC1_SEL		16
#define BM_CSCMR1_USDHC1_SEL		(0x1 << 16)
#define BP_CSCMR1_USDHC2_SEL		17
#define BM_CSCMR1_USDHC2_SEL		(0x1 << 17)
#define BP_CSCMR1_USDHC3_SEL		18
#define BM_CSCMR1_USDHC3_SEL		(0x1 << 18)
#define BP_CSCMR1_USDHC4_SEL		19
#define BM_CSCMR1_USDHC4_SEL		(0x1 << 19)
#define BP_CSCMR1_EMI_PODF		20
#define BM_CSCMR1_EMI_PODF		(0x7 << 20)
#define BP_CSCMR1_EMI_SLOW_PODF		23
#define BM_CSCMR1_EMI_SLOW_PODF		(0x7 << 23)
#define BP_CSCMR1_EMI_SEL		27
#define BM_CSCMR1_EMI_SEL		(0x3 << 27)
#define BP_CSCMR1_EMI_SLOW_SEL		29
#define BM_CSCMR1_EMI_SLOW_SEL		(0x3 << 29)

#define BP_CSCMR2_CAN_PODF		2
#define BM_CSCMR2_CAN_PODF		(0x3f << 2)
#define BM_CSCMR2_LDB_DI0_IPU_DIV	(0x1 << 10)
#define BM_CSCMR2_LDB_DI1_IPU_DIV	(0x1 << 11)
#define BP_CSCMR2_ESAI_SEL		19
#define BM_CSCMR2_ESAI_SEL		(0x3 << 19)

#define BP_CSCDR1_UART_PODF		0
#define BM_CSCDR1_UART_PODF		(0x3f << 0)
#define BP_CSCDR1_USDHC1_PODF		11
#define BM_CSCDR1_USDHC1_PODF		(0x7 << 11)
#define BP_CSCDR1_USDHC2_PODF		16
#define BM_CSCDR1_USDHC2_PODF		(0x7 << 16)
#define BP_CSCDR1_USDHC3_PODF		19
#define BM_CSCDR1_USDHC3_PODF		(0x7 << 19)
#define BP_CSCDR1_USDHC4_PODF		22
#define BM_CSCDR1_USDHC4_PODF		(0x7 << 22)
#define BP_CSCDR1_VPU_AXI_PODF		25
#define BM_CSCDR1_VPU_AXI_PODF		(0x7 << 25)

#define BP_CS1CDR_SSI1_PODF		0
#define BM_CS1CDR_SSI1_PODF		(0x3f << 0)
#define BP_CS1CDR_SSI1_PRED		6
#define BM_CS1CDR_SSI1_PRED		(0x7 << 6)
#define BP_CS1CDR_ESAI_PRED		9
#define BM_CS1CDR_ESAI_PRED		(0x7 << 9)
#define BP_CS1CDR_SSI3_PODF		16
#define BM_CS1CDR_SSI3_PODF		(0x3f << 16)
#define BP_CS1CDR_SSI3_PRED		22
#define BM_CS1CDR_SSI3_PRED		(0x7 << 22)
#define BP_CS1CDR_ESAI_PODF		25
#define BM_CS1CDR_ESAI_PODF		(0x7 << 25)

#define BP_CS2CDR_SSI2_PODF		0
#define BM_CS2CDR_SSI2_PODF		(0x3f << 0)
#define BP_CS2CDR_SSI2_PRED		6
#define BM_CS2CDR_SSI2_PRED		(0x7 << 6)
#define BP_CS2CDR_LDB_DI0_SEL		9
#define BM_CS2CDR_LDB_DI0_SEL		(0x7 << 9)
#define BP_CS2CDR_LDB_DI1_SEL		12
#define BM_CS2CDR_LDB_DI1_SEL		(0x7 << 12)
#define BP_CS2CDR_ENFC_SEL		16
#define BM_CS2CDR_ENFC_SEL		(0x3 << 16)
#define BP_CS2CDR_ENFC_PRED		18
#define BM_CS2CDR_ENFC_PRED		(0x7 << 18)
#define BP_CS2CDR_ENFC_PODF		21
#define BM_CS2CDR_ENFC_PODF		(0x3f << 21)

#define BP_CDCDR_ASRC_SERIAL_SEL	7
#define BM_CDCDR_ASRC_SERIAL_SEL	(0x3 << 7)
#define BP_CDCDR_ASRC_SERIAL_PODF	9
#define BM_CDCDR_ASRC_SERIAL_PODF	(0x7 << 9)
#define BP_CDCDR_ASRC_SERIAL_PRED	12
#define BM_CDCDR_ASRC_SERIAL_PRED	(0x7 << 12)
#define BP_CDCDR_SPDIF_SEL		20
#define BM_CDCDR_SPDIF_SEL		(0x3 << 20)
#define BP_CDCDR_SPDIF_PODF		22
#define BM_CDCDR_SPDIF_PODF		(0x7 << 22)
#define BP_CDCDR_SPDIF_PRED		25
#define BM_CDCDR_SPDIF_PRED		(0x7 << 25)
#define BP_CDCDR_HSI_TX_PODF		29
#define BM_CDCDR_HSI_TX_PODF		(0x7 << 29)
#define BP_CDCDR_HSI_TX_SEL		28
#define BM_CDCDR_HSI_TX_SEL		(0x1 << 28)

#define BP_CHSCCDR_IPU1_DI0_SEL		0
#define BM_CHSCCDR_IPU1_DI0_SEL		(0x7 << 0)
#define BP_CHSCCDR_IPU1_DI0_PRE_PODF	3
#define BM_CHSCCDR_IPU1_DI0_PRE_PODF	(0x7 << 3)
#define BP_CHSCCDR_IPU1_DI0_PRE_SEL	6
#define BM_CHSCCDR_IPU1_DI0_PRE_SEL	(0x7 << 6)
#define BP_CHSCCDR_IPU1_DI1_SEL		9
#define BM_CHSCCDR_IPU1_DI1_SEL		(0x7 << 9)
#define BP_CHSCCDR_IPU1_DI1_PRE_PODF	12
#define BM_CHSCCDR_IPU1_DI1_PRE_PODF	(0x7 << 12)
#define BP_CHSCCDR_IPU1_DI1_PRE_SEL	15
#define BM_CHSCCDR_IPU1_DI1_PRE_SEL	(0x7 << 15)

#define BP_CSCDR2_IPU2_DI0_SEL		0
#define BM_CSCDR2_IPU2_DI0_SEL		(0x7)
#define BP_CSCDR2_IPU2_DI0_PRE_PODF	3
#define BM_CSCDR2_IPU2_DI0_PRE_PODF	(0x7 << 3)
#define BP_CSCDR2_IPU2_DI0_PRE_SEL	6
#define BM_CSCDR2_IPU2_DI0_PRE_SEL	(0x7 << 6)
#define BP_CSCDR2_IPU2_DI1_SEL		9
#define BM_CSCDR2_IPU2_DI1_SEL		(0x7 << 9)
#define BP_CSCDR2_IPU2_DI1_PRE_PODF	12
#define BM_CSCDR2_IPU2_DI1_PRE_PODF	(0x7 << 12)
#define BP_CSCDR2_IPU2_DI1_PRE_SEL	15
#define BM_CSCDR2_IPU2_DI1_PRE_SEL	(0x7 << 15)
#define BP_CSCDR2_ECSPI_CLK_PODF	19
#define BM_CSCDR2_ECSPI_CLK_PODF	(0x3f << 19)

#define BP_CSCDR3_IPU1_HSP_SEL		9
#define BM_CSCDR3_IPU1_HSP_SEL		(0x3 << 9)
#define BP_CSCDR3_IPU1_HSP_PODF		11
#define BM_CSCDR3_IPU1_HSP_PODF		(0x7 << 11)
#define BP_CSCDR3_IPU2_HSP_SEL		14
#define BM_CSCDR3_IPU2_HSP_SEL		(0x3 << 14)
#define BP_CSCDR3_IPU2_HSP_PODF		16
#define BM_CSCDR3_IPU2_HSP_PODF		(0x7 << 16)

#define BM_CDHIPR_AXI_PODF_BUSY		(0x1 << 0)
#define BM_CDHIPR_AHB_PODF_BUSY		(0x1 << 1)
#define BM_CDHIPR_MMDC_CH1_PODF_BUSY	(0x1 << 2)
#define BM_CDHIPR_PERIPH2_SEL_BUSY	(0x1 << 3)
#define BM_CDHIPR_MMDC_CH0_PODF_BUSY	(0x1 << 4)
#define BM_CDHIPR_PERIPH_SEL_BUSY	(0x1 << 5)
#define BM_CDHIPR_ARM_PODF_BUSY		(0x1 << 16)

#define BP_CLPCR_LPM			0
#define BM_CLPCR_LPM			(0x3 << 0)
#define BM_CLPCR_BYPASS_PMIC_READY	(0x1 << 2)
#define BM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
#define BM_CLPCR_SBYOS			(0x1 << 6)
#define BM_CLPCR_DIS_REF_OSC		(0x1 << 7)
#define BM_CLPCR_VSTBY			(0x1 << 8)
#define BP_CLPCR_STBY_COUNT		9
#define BM_CLPCR_STBY_COUNT		(0x3 << 9)
#define BM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
#define BM_CLPCR_WB_PER_AT_LPM		(0x1 << 16)
#define BM_CLPCR_WB_CORE_AT_LPM		(0x1 << 17)
#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS	(0x1 << 19)
#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS	(0x1 << 21)
#define BM_CLPCR_MASK_CORE0_WFI		(0x1 << 22)
#define BM_CLPCR_MASK_CORE1_WFI		(0x1 << 23)
#define BM_CLPCR_MASK_CORE2_WFI		(0x1 << 24)
#define BM_CLPCR_MASK_CORE3_WFI		(0x1 << 25)
#define BM_CLPCR_MASK_SCU_IDLE		(0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE		(0x1 << 27)

#define FREQ_480M	480000000
#define FREQ_528M	528000000
#define FREQ_594M	594000000
#define FREQ_650M	650000000
#define FREQ_1300M	1300000000

static struct clk pll1_sys;
static struct clk pll2_bus;
static struct clk pll3_usb_otg;
static struct clk pll4_audio;
static struct clk pll5_video;
static struct clk pll6_mlb;
static struct clk pll7_usb_host;
static struct clk pll8_enet;
static struct clk apbh_dma_clk;
static struct clk arm_clk;
static struct clk ipg_clk;
static struct clk ahb_clk;
static struct clk axi_clk;
static struct clk mmdc_ch0_axi_clk;
static struct clk mmdc_ch1_axi_clk;
static struct clk periph_clk;
static struct clk periph_pre_clk;
static struct clk periph_clk2_clk;
static struct clk periph2_clk;
static struct clk periph2_pre_clk;
static struct clk periph2_clk2_clk;
static struct clk gpu2d_core_clk;
static struct clk gpu3d_core_clk;
static struct clk gpu3d_shader_clk;
static struct clk ipg_perclk;
static struct clk emi_clk;
static struct clk emi_slow_clk;
static struct clk can1_clk;
static struct clk uart_clk;
static struct clk usdhc1_clk;
static struct clk usdhc2_clk;
static struct clk usdhc3_clk;
static struct clk usdhc4_clk;
static struct clk vpu_clk;
static struct clk hsi_tx_clk;
static struct clk ipu1_di0_pre_clk;
static struct clk ipu1_di1_pre_clk;
static struct clk ipu2_di0_pre_clk;
static struct clk ipu2_di1_pre_clk;
static struct clk ipu1_clk;
static struct clk ipu2_clk;
static struct clk ssi1_clk;
static struct clk ssi3_clk;
static struct clk esai_clk;
static struct clk ssi2_clk;
static struct clk spdif_clk;
static struct clk asrc_serial_clk;
static struct clk gpu2d_axi_clk;
static struct clk gpu3d_axi_clk;
static struct clk pcie_clk;
static struct clk vdo_axi_clk;
static struct clk ldb_di0_clk;
static struct clk ldb_di1_clk;
static struct clk ipu1_di0_clk;
static struct clk ipu1_di1_clk;
static struct clk ipu2_di0_clk;
static struct clk ipu2_di1_clk;
static struct clk enfc_clk;
static struct clk dummy_clk = {};

static unsigned long external_high_reference;
static unsigned long external_low_reference;
static unsigned long oscillator_reference;

static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
{
	return oscillator_reference;
}

static unsigned long get_high_reference_clock_rate(struct clk *clk)
{
	return external_high_reference;
}

static unsigned long get_low_reference_clock_rate(struct clk *clk)
{
	return external_low_reference;
}

static struct clk ckil_clk = {
	.get_rate = get_low_reference_clock_rate,
};

static struct clk ckih_clk = {
	.get_rate = get_high_reference_clock_rate,
};

static struct clk osc_clk = {
	.get_rate = get_oscillator_reference_clock_rate,
};

static inline void __iomem *pll_get_reg_addr(struct clk *pll)
{
	if (pll == &pll1_sys)
		return PLL1_SYS;
	else if (pll == &pll2_bus)
		return PLL2_BUS;
	else if (pll == &pll3_usb_otg)
		return PLL3_USB_OTG;
	else if (pll == &pll4_audio)
		return PLL4_AUDIO;
	else if (pll == &pll5_video)
		return PLL5_VIDEO;
	else if (pll == &pll6_mlb)
		return PLL6_MLB;
	else if (pll == &pll7_usb_host)
		return PLL7_USB_HOST;
	else if (pll == &pll8_enet)
		return PLL8_ENET;
	else
		BUG();

	return NULL;
}

static int pll_enable(struct clk *clk)
{
	int timeout = 0x100000;
	void __iomem *reg;
	u32 val;

	reg = pll_get_reg_addr(clk);
	val = readl_relaxed(reg);
	val &= ~BM_PLL_BYPASS;
	val &= ~BM_PLL_POWER_DOWN;
	/* 480MHz PLLs have the opposite definition for power bit */
	if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
		val |= BM_PLL_POWER_DOWN;
	writel_relaxed(val, reg);

	/* Wait for PLL to lock */
	while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
		cpu_relax();

	if (unlikely(!timeout))
		return -EBUSY;

	/* Enable the PLL output now */
	val = readl_relaxed(reg);
	val |= BM_PLL_ENABLE;
	writel_relaxed(val, reg);

	return 0;
}

static void pll_disable(struct clk *clk)
{
	void __iomem *reg;
	u32 val;

	reg = pll_get_reg_addr(clk);
	val = readl_relaxed(reg);
	val &= ~BM_PLL_ENABLE;
	val |= BM_PLL_BYPASS;
	val |= BM_PLL_POWER_DOWN;
	if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
		val &= ~BM_PLL_POWER_DOWN;
	writel_relaxed(val, reg);
}

static unsigned long pll1_sys_get_rate(struct clk *clk)
{
	u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
		  BP_PLL_SYS_DIV_SELECT;

	return clk_get_rate(clk->parent) * div / 2;
}

static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
{
	u32 val, div;

	if (rate < FREQ_650M || rate > FREQ_1300M)
		return -EINVAL;

	div = rate * 2 / clk_get_rate(clk->parent);
	val = readl_relaxed(PLL1_SYS);
	val &= ~BM_PLL_SYS_DIV_SELECT;
	val |= div << BP_PLL_SYS_DIV_SELECT;
	writel_relaxed(val, PLL1_SYS);

	return 0;
}

static unsigned long pll8_enet_get_rate(struct clk *clk)
{
	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
		  BP_PLL_ENET_DIV_SELECT;

	switch (div) {
	case 0:
		return 25000000;
	case 1:
		return 50000000;
	case 2:
		return 100000000;
	case 3:
		return 125000000;
	}

	return 0;
}

static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
{
	u32 val, div;

	switch (rate) {
	case 25000000:
		div = 0;
		break;
	case 50000000:
		div = 1;
		break;
	case 100000000:
		div = 2;
		break;
	case 125000000:
		div = 3;
		break;
	default:
		return -EINVAL;
	}

	val = readl_relaxed(PLL8_ENET);
	val &= ~BM_PLL_ENET_DIV_SELECT;
	val |= div << BP_PLL_ENET_DIV_SELECT;
	writel_relaxed(val, PLL8_ENET);

	return 0;
}

static unsigned long pll_av_get_rate(struct clk *clk)
{
	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
	unsigned long parent_rate = clk_get_rate(clk->parent);
	u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
	u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
	u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
		  BP_PLL_AV_DIV_SELECT;

	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
}

static int pll_av_set_rate(struct clk *clk, unsigned long rate)
{
	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
	unsigned int parent_rate = clk_get_rate(clk->parent);
	u32 val, div;
	u32 mfn, mfd = 1000000;
	s64 temp64;

	if (rate < FREQ_650M || rate > FREQ_1300M)
		return -EINVAL;

	div = rate / parent_rate;
	temp64 = (u64) (rate - div * parent_rate);
	temp64 *= mfd;
	do_div(temp64, parent_rate);
	mfn = temp64;

	val = readl_relaxed(reg);
	val &= ~BM_PLL_AV_DIV_SELECT;
	val |= div << BP_PLL_AV_DIV_SELECT;
	writel_relaxed(val, reg);
	writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
	writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);

	return 0;
}

static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
{
	void __iomem *reg;

	if (clk == &pll2_bus) {
		reg = PLL2_BUS;
		*bp = BP_PLL_BUS_DIV_SELECT;
		*bm = BM_PLL_BUS_DIV_SELECT;
	} else if (clk == &pll3_usb_otg) {
		reg = PLL3_USB_OTG;
		*bp = BP_PLL_USB_DIV_SELECT;
		*bm = BM_PLL_USB_DIV_SELECT;
	} else if (clk == &pll7_usb_host) {
		reg = PLL7_USB_HOST;
		*bp = BP_PLL_USB_DIV_SELECT;
		*bm = BM_PLL_USB_DIV_SELECT;
	} else {
		BUG();
	}

	return reg;
}

static unsigned long pll_get_rate(struct clk *clk)
{
	void __iomem *reg;
	u32 div, bp, bm;

	reg = pll_get_div_reg_bit(clk, &bp, &bm);
	div = (readl_relaxed(reg) & bm) >> bp;

	return (div == 1) ? clk_get_rate(clk->parent) * 22 :
			    clk_get_rate(clk->parent) * 20;
}

static int pll_set_rate(struct clk *clk, unsigned long rate)
{
	void __iomem *reg;
	u32 val, div, bp, bm;

	if (rate == FREQ_528M)
		div = 1;
	else if (rate == FREQ_480M)
		div = 0;
	else
		return -EINVAL;

	reg = pll_get_div_reg_bit(clk, &bp, &bm);
	val = readl_relaxed(reg);
	val &= ~bm;
	val |= div << bp;
	writel_relaxed(val, reg);

	return 0;
}

#define pll2_bus_get_rate	pll_get_rate
#define pll2_bus_set_rate	pll_set_rate
#define pll3_usb_otg_get_rate	pll_get_rate
#define pll3_usb_otg_set_rate	pll_set_rate
#define pll7_usb_host_get_rate	pll_get_rate
#define pll7_usb_host_set_rate	pll_set_rate
#define pll4_audio_get_rate	pll_av_get_rate
#define pll4_audio_set_rate	pll_av_set_rate
#define pll5_video_get_rate	pll_av_get_rate
#define pll5_video_set_rate	pll_av_set_rate
#define pll6_mlb_get_rate	NULL
#define pll6_mlb_set_rate	NULL

#define DEF_PLL(name)					\
	static struct clk name = {			\
		.enable		= pll_enable,		\
		.disable	= pll_disable,		\
		.get_rate	= name##_get_rate,	\
		.set_rate	= name##_set_rate,	\
		.parent		= &osc_clk,		\
	}

DEF_PLL(pll1_sys);
DEF_PLL(pll2_bus);
DEF_PLL(pll3_usb_otg);
DEF_PLL(pll4_audio);
DEF_PLL(pll5_video);
DEF_PLL(pll6_mlb);
DEF_PLL(pll7_usb_host);
DEF_PLL(pll8_enet);

static unsigned long pfd_get_rate(struct clk *clk)
{
	u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
	u32 frac, bp_frac;

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.enable(&apbh_dma_clk);

	bp_frac = clk->enable_shift - 7;
	frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
	do_div(tmp, frac);

	return tmp;
}

static int pfd_set_rate(struct clk *clk, unsigned long rate)
{
	u32 val, frac, bp_frac;
	u64 tmp = (u64) clk_get_rate(clk->parent) * 18;

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.enable(&apbh_dma_clk);

	/*
	 * Round up the divider so that we don't set a rate
	 * higher than what is requested
	 */
	tmp += rate / 2;
	do_div(tmp, rate);
	frac = tmp;
	frac = (frac < 12) ? 12 : frac;
	frac = (frac > 35) ? 35 : frac;

	/*
	 * The frac field always starts from 7 bits lower
	 * position of enable bit
	 */
	bp_frac = clk->enable_shift - 7;
	val = readl_relaxed(clk->enable_reg);
	val &= ~(PFD_FRAC_MASK << bp_frac);
	val |= frac << bp_frac;
	writel_relaxed(val, clk->enable_reg);

	tmp = (u64) clk_get_rate(clk->parent) * 18;
	do_div(tmp, frac);

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.disable(&apbh_dma_clk);

	return 0;
}

static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
{
	u32 frac;
	u64 tmp;

	tmp = (u64) clk_get_rate(clk->parent) * 18;
	tmp += rate / 2;
	do_div(tmp, rate);
	frac = tmp;
	frac = (frac < 12) ? 12 : frac;
	frac = (frac > 35) ? 35 : frac;
	tmp = (u64) clk_get_rate(clk->parent) * 18;
	do_div(tmp, frac);

	return tmp;
}

static int pfd_enable(struct clk *clk)
{
	u32 val;

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.enable(&apbh_dma_clk);

	val = readl_relaxed(clk->enable_reg);
	val &= ~(1 << clk->enable_shift);
	writel_relaxed(val, clk->enable_reg);

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.disable(&apbh_dma_clk);

	return 0;
}

static void pfd_disable(struct clk *clk)
{
	u32 val;

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.enable(&apbh_dma_clk);

	val = readl_relaxed(clk->enable_reg);
	val |= 1 << clk->enable_shift;
	writel_relaxed(val, clk->enable_reg);

	if (apbh_dma_clk.usecount == 0)
		apbh_dma_clk.disable(&apbh_dma_clk);
}

#define DEF_PFD(name, er, es, p)			\
	static struct clk name = {			\
		.enable_reg	= er,			\
		.enable_shift	= es,			\
		.enable		= pfd_enable,		\
		.disable	= pfd_disable,		\
		.get_rate	= pfd_get_rate,		\
		.set_rate	= pfd_set_rate,		\
		.round_rate	= pfd_round_rate,	\
		.parent		= p,			\
	}

DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);

static unsigned long pll2_200m_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 2;
}

static struct clk pll2_200m = {
	.parent = &pll2_pfd_400m,
	.get_rate = pll2_200m_get_rate,
};

static unsigned long pll3_120m_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 4;
}

static struct clk pll3_120m = {
	.parent = &pll3_usb_otg,
	.get_rate = pll3_120m_get_rate,
};

static unsigned long pll3_80m_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 6;
}

static struct clk pll3_80m = {
	.parent = &pll3_usb_otg,
	.get_rate = pll3_80m_get_rate,
};

static unsigned long pll3_60m_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / 8;
}

static struct clk pll3_60m = {
	.parent = &pll3_usb_otg,
	.get_rate = pll3_60m_get_rate,
};

static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
{
	u32 val = readl_relaxed(CCSR);

	if (parent == &pll1_sys) {
		val &= ~BM_CCSR_PLL1_SW_SEL;
		val &= ~BM_CCSR_STEP_SEL;
	} else if (parent == &osc_clk) {
		val |= BM_CCSR_PLL1_SW_SEL;
		val &= ~BM_CCSR_STEP_SEL;
	} else if (parent == &pll2_pfd_400m) {
		val |= BM_CCSR_PLL1_SW_SEL;
		val |= BM_CCSR_STEP_SEL;
	} else {
		return -EINVAL;
	}

	writel_relaxed(val, CCSR);

	return 0;
}

static struct clk pll1_sw_clk = {
	.parent = &pll1_sys,
	.set_parent = pll1_sw_clk_set_parent,
};

static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
{
	u32 min_pred, temp_pred, old_err, err;

	if (div >= 512) {
		*pred = 8;
		*podf = 64;
	} else if (div >= 8) {
		min_pred = (div - 1) / 64 + 1;
		old_err = 8;
		for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
			err = div % temp_pred;
			if (err == 0) {
				*pred = temp_pred;
				break;
			}
			err = temp_pred - err;
			if (err < old_err) {
				old_err = err;
				*pred = temp_pred;
			}
		}
		*podf = (div + *pred - 1) / *pred;
	} else if (div < 8) {
		*pred = div;
		*podf = 1;
	}
}

static int _clk_enable(struct clk *clk)
{
	u32 reg;
	reg = readl_relaxed(clk->enable_reg);
	reg |= 0x3 << clk->enable_shift;
	writel_relaxed(reg, clk->enable_reg);

	return 0;
}

static void _clk_disable(struct clk *clk)
{
	u32 reg;
	reg = readl_relaxed(clk->enable_reg);
	reg &= ~(0x3 << clk->enable_shift);
	writel_relaxed(reg, clk->enable_reg);
}

struct divider {
	struct clk *clk;
	void __iomem *reg;
	u32 bp_pred;
	u32 bm_pred;
	u32 bp_podf;
	u32 bm_podf;
};

#define DEF_CLK_DIV1(d, c, r, b)				\
	static struct divider d = {				\
		.clk = c,					\
		.reg = r,					\
		.bp_podf = BP_##r##_##b##_PODF,			\
		.bm_podf = BM_##r##_##b##_PODF,			\
	}

DEF_CLK_DIV1(arm_div,		&arm_clk,		CACRR,	ARM);
DEF_CLK_DIV1(ipg_div,		&ipg_clk,		CBCDR,	IPG);
DEF_CLK_DIV1(ahb_div,		&ahb_clk,		CBCDR,	AHB);
DEF_CLK_DIV1(axi_div,		&axi_clk,		CBCDR,	AXI);
DEF_CLK_DIV1(mmdc_ch0_axi_div,	&mmdc_ch0_axi_clk,	CBCDR,	MMDC_CH0_AXI);
DEF_CLK_DIV1(mmdc_ch1_axi_div,	&mmdc_ch1_axi_clk,	CBCDR,	MMDC_CH1_AXI);
DEF_CLK_DIV1(periph_clk2_div,	&periph_clk2_clk,	CBCDR,	PERIPH_CLK2);
DEF_CLK_DIV1(periph2_clk2_div,	&periph2_clk2_clk,	CBCDR,	PERIPH2_CLK2);
DEF_CLK_DIV1(gpu2d_core_div,	&gpu2d_core_clk,	CBCMR,	GPU2D_CORE);
DEF_CLK_DIV1(gpu3d_core_div,	&gpu3d_core_clk,	CBCMR,	GPU3D_CORE);
DEF_CLK_DIV1(gpu3d_shader_div,	&gpu3d_shader_clk,	CBCMR,	GPU3D_SHADER);
DEF_CLK_DIV1(ipg_perclk_div,	&ipg_perclk,		CSCMR1,	PERCLK);
DEF_CLK_DIV1(emi_div,		&emi_clk,		CSCMR1,	EMI);
DEF_CLK_DIV1(emi_slow_div,	&emi_slow_clk,		CSCMR1,	EMI_SLOW);
DEF_CLK_DIV1(can_div,		&can1_clk,		CSCMR2,	CAN);
DEF_CLK_DIV1(uart_div,		&uart_clk,		CSCDR1,	UART);
DEF_CLK_DIV1(usdhc1_div,	&usdhc1_clk,		CSCDR1,	USDHC1);
DEF_CLK_DIV1(usdhc2_div,	&usdhc2_clk,		CSCDR1,	USDHC2);
DEF_CLK_DIV1(usdhc3_div,	&usdhc3_clk,		CSCDR1,	USDHC3);
DEF_CLK_DIV1(usdhc4_div,	&usdhc4_clk,		CSCDR1,	USDHC4);
DEF_CLK_DIV1(vpu_div,		&vpu_clk,		CSCDR1,	VPU_AXI);
DEF_CLK_DIV1(hsi_tx_div,	&hsi_tx_clk,		CDCDR,	HSI_TX);
DEF_CLK_DIV1(ipu1_di0_pre_div,	&ipu1_di0_pre_clk,	CHSCCDR, IPU1_DI0_PRE);
DEF_CLK_DIV1(ipu1_di1_pre_div,	&ipu1_di1_pre_clk,	CHSCCDR, IPU1_DI1_PRE);
DEF_CLK_DIV1(ipu2_di0_pre_div,	&ipu2_di0_pre_clk,	CSCDR2,	IPU2_DI0_PRE);
DEF_CLK_DIV1(ipu2_di1_pre_div,	&ipu2_di1_pre_clk,	CSCDR2,	IPU2_DI1_PRE);
DEF_CLK_DIV1(ipu1_div,		&ipu1_clk,		CSCDR3,	IPU1_HSP);
DEF_CLK_DIV1(ipu2_div,		&ipu2_clk,		CSCDR3,	IPU2_HSP);

#define DEF_CLK_DIV2(d, c, r, b)				\
	static struct divider d = {				\
		.clk = c,					\
		.reg = r,					\
		.bp_pred = BP_##r##_##b##_PRED,			\
		.bm_pred = BM_##r##_##b##_PRED,			\
		.bp_podf = BP_##r##_##b##_PODF,			\
		.bm_podf = BM_##r##_##b##_PODF,			\
	}

DEF_CLK_DIV2(ssi1_div,		&ssi1_clk,		CS1CDR,	SSI1);
DEF_CLK_DIV2(ssi3_div,		&ssi3_clk,		CS1CDR,	SSI3);
DEF_CLK_DIV2(esai_div,		&esai_clk,		CS1CDR,	ESAI);
DEF_CLK_DIV2(ssi2_div,		&ssi2_clk,		CS2CDR,	SSI2);
DEF_CLK_DIV2(enfc_div,		&enfc_clk,		CS2CDR,	ENFC);
DEF_CLK_DIV2(spdif_div,		&spdif_clk,		CDCDR,	SPDIF);
DEF_CLK_DIV2(asrc_serial_div,	&asrc_serial_clk,	CDCDR,	ASRC_SERIAL);

static struct divider *dividers[] = {
	&arm_div,
	&ipg_div,
	&ahb_div,
	&axi_div,
	&mmdc_ch0_axi_div,
	&mmdc_ch1_axi_div,
	&periph_clk2_div,
	&periph2_clk2_div,
	&gpu2d_core_div,
	&gpu3d_core_div,
	&gpu3d_shader_div,
	&ipg_perclk_div,
	&emi_div,
	&emi_slow_div,
	&can_div,
	&uart_div,
	&usdhc1_div,
	&usdhc2_div,
	&usdhc3_div,
	&usdhc4_div,
	&vpu_div,
	&hsi_tx_div,
	&ipu1_di0_pre_div,
	&ipu1_di1_pre_div,
	&ipu2_di0_pre_div,
	&ipu2_di1_pre_div,
	&ipu1_div,
	&ipu2_div,
	&ssi1_div,
	&ssi3_div,
	&esai_div,
	&ssi2_div,
	&enfc_div,
	&spdif_div,
	&asrc_serial_div,
};

static unsigned long ldb_di_clk_get_rate(struct clk *clk)
{
	u32 val = readl_relaxed(CSCMR2);

	val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
				       BM_CSCMR2_LDB_DI1_IPU_DIV;
	if (val)
		return clk_get_rate(clk->parent) / 7;
	else
		return clk_get_rate(clk->parent) * 2 / 7;
}

static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	u32 val = readl_relaxed(CSCMR2);

	if (rate * 7 <= parent_rate + parent_rate / 20)
		val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
	else
		val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;

	writel_relaxed(val, CSCMR2);

	return 0;
}

static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);

	if (rate * 7 <= parent_rate + parent_rate / 20)
		return parent_rate / 7;
	else
		return 2 * parent_rate / 7;
}

static unsigned long _clk_get_rate(struct clk *clk)
{
	struct divider *d;
	u32 val, pred, podf;
	int i, num;

	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
		return ldb_di_clk_get_rate(clk);

	num = ARRAY_SIZE(dividers);
	for (i = 0; i < num; i++)
		if (dividers[i]->clk == clk) {
			d = dividers[i];
			break;
		}
	if (i == num)
		return clk_get_rate(clk->parent);

	val = readl_relaxed(d->reg);
	pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
	podf = ((val & d->bm_podf) >> d->bp_podf) + 1;

	return clk_get_rate(clk->parent) / (pred * podf);
}

static int clk_busy_wait(struct clk *clk)
{
	int timeout = 0x100000;
	u32 bm;

	if (clk == &axi_clk)
		bm = BM_CDHIPR_AXI_PODF_BUSY;
	else if (clk == &ahb_clk)
		bm = BM_CDHIPR_AHB_PODF_BUSY;
	else if (clk == &mmdc_ch0_axi_clk)
		bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
	else if (clk == &periph_clk)
		bm = BM_CDHIPR_PERIPH_SEL_BUSY;
	else if (clk == &arm_clk)
		bm = BM_CDHIPR_ARM_PODF_BUSY;
	else
		return -EINVAL;

	while ((readl_relaxed(CDHIPR) & bm) && --timeout)
		cpu_relax();

	if (unlikely(!timeout))
		return -EBUSY;

	return 0;
}

static int _clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	struct divider *d;
	u32 val, div, max_div, pred = 0, podf;
	int i, num;

	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
		return ldb_di_clk_set_rate(clk, rate);

	num = ARRAY_SIZE(dividers);
	for (i = 0; i < num; i++)
		if (dividers[i]->clk == clk) {
			d = dividers[i];
			break;
		}
	if (i == num)
		return -EINVAL;

	max_div = ((d->bm_pred >> d->bp_pred) + 1) *
		  ((d->bm_podf >> d->bp_podf) + 1);

	div = parent_rate / rate;
	if (div == 0)
		div++;

	if ((parent_rate / div != rate) || div > max_div)
		return -EINVAL;

	if (d->bm_pred) {
		calc_pred_podf_dividers(div, &pred, &podf);
	} else {
		pred = 1;
		podf = div;
	}

	val = readl_relaxed(d->reg);
	val &= ~(d->bm_pred | d->bm_podf);
	val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
	writel_relaxed(val, d->reg);

	if (clk == &axi_clk || clk == &ahb_clk ||
	    clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
		return clk_busy_wait(clk);

	return 0;
}

static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	u32 div = parent_rate / rate;
	u32 div_max, pred = 0, podf;
	struct divider *d;
	int i, num;

	if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
		return ldb_di_clk_round_rate(clk, rate);

	num = ARRAY_SIZE(dividers);
	for (i = 0; i < num; i++)
		if (dividers[i]->clk == clk) {
			d = dividers[i];
			break;
		}
	if (i == num)
		return -EINVAL;

	if (div == 0 || parent_rate % rate)
		div++;

	if (d->bm_pred) {
		calc_pred_podf_dividers(div, &pred, &podf);
		div = pred * podf;
	} else {
		div_max = (d->bm_podf >> d->bp_podf) + 1;
		if (div > div_max)
			div = div_max;
	}

	return parent_rate / div;
}

struct multiplexer {
	struct clk *clk;
	void __iomem *reg;
	u32 bp;
	u32 bm;
	int pnum;
	struct clk *parents[];
};

static struct multiplexer axi_mux = {
	.clk = &axi_clk,
	.reg = CBCDR,
	.bp = BP_CBCDR_AXI_SEL,
	.bm = BM_CBCDR_AXI_SEL,
	.parents = {
		&periph_clk,
		&pll2_pfd_400m,
		&pll3_pfd_540m,
		NULL
	},
};

static struct multiplexer periph_mux = {
	.clk = &periph_clk,
	.reg = CBCDR,
	.bp = BP_CBCDR_PERIPH_CLK_SEL,
	.bm = BM_CBCDR_PERIPH_CLK_SEL,
	.parents = {
		&periph_pre_clk,
		&periph_clk2_clk,
		NULL
	},
};

static struct multiplexer periph_pre_mux = {
	.clk = &periph_pre_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
	.bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
	.parents = {
		&pll2_bus,
		&pll2_pfd_400m,
		&pll2_pfd_352m,
		&pll2_200m,
		NULL
	},
};

static struct multiplexer periph_clk2_mux = {
	.clk = &periph_clk2_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_PERIPH_CLK2_SEL,
	.bm = BM_CBCMR_PERIPH_CLK2_SEL,
	.parents = {
		&pll3_usb_otg,
		&osc_clk,
		NULL
	},
};

static struct multiplexer periph2_mux = {
	.clk = &periph2_clk,
	.reg = CBCDR,
	.bp = BP_CBCDR_PERIPH2_CLK_SEL,
	.bm = BM_CBCDR_PERIPH2_CLK_SEL,
	.parents = {
		&periph2_pre_clk,
		&periph2_clk2_clk,
		NULL
	},
};

static struct multiplexer periph2_pre_mux = {
	.clk = &periph2_pre_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
	.bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
	.parents = {
		&pll2_bus,
		&pll2_pfd_400m,
		&pll2_pfd_352m,
		&pll2_200m,
		NULL
	},
};

static struct multiplexer periph2_clk2_mux = {
	.clk = &periph2_clk2_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_PERIPH2_CLK2_SEL,
	.bm = BM_CBCMR_PERIPH2_CLK2_SEL,
	.parents = {
		&pll3_usb_otg,
		&osc_clk,
		NULL
	},
};

static struct multiplexer gpu2d_axi_mux = {
	.clk = &gpu2d_axi_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_GPU2D_AXI_SEL,
	.bm = BM_CBCMR_GPU2D_AXI_SEL,
	.parents = {
		&axi_clk,
		&ahb_clk,
		NULL
	},
};

static struct multiplexer gpu3d_axi_mux = {
	.clk = &gpu3d_axi_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_GPU3D_AXI_SEL,
	.bm = BM_CBCMR_GPU3D_AXI_SEL,
	.parents = {
		&axi_clk,
		&ahb_clk,
		NULL
	},
};

static struct multiplexer gpu3d_core_mux = {
	.clk = &gpu3d_core_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_GPU3D_CORE_SEL,
	.bm = BM_CBCMR_GPU3D_CORE_SEL,
	.parents = {
		&mmdc_ch0_axi_clk,
		&pll3_usb_otg,
		&pll2_pfd_594m,
		&pll2_pfd_400m,
		NULL
	},
};

static struct multiplexer gpu3d_shader_mux = {
	.clk = &gpu3d_shader_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_GPU3D_SHADER_SEL,
	.bm = BM_CBCMR_GPU3D_SHADER_SEL,
	.parents = {
		&mmdc_ch0_axi_clk,
		&pll3_usb_otg,
		&pll2_pfd_594m,
		&pll3_pfd_720m,
		NULL
	},
};

static struct multiplexer pcie_axi_mux = {
	.clk = &pcie_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_PCIE_AXI_SEL,
	.bm = BM_CBCMR_PCIE_AXI_SEL,
	.parents = {
		&axi_clk,
		&ahb_clk,
		NULL
	},
};

static struct multiplexer vdo_axi_mux = {
	.clk = &vdo_axi_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_VDO_AXI_SEL,
	.bm = BM_CBCMR_VDO_AXI_SEL,
	.parents = {
		&axi_clk,
		&ahb_clk,
		NULL
	},
};

static struct multiplexer vpu_axi_mux = {
	.clk = &vpu_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_VPU_AXI_SEL,
	.bm = BM_CBCMR_VPU_AXI_SEL,
	.parents = {
		&axi_clk,
		&pll2_pfd_400m,
		&pll2_pfd_352m,
		NULL
	},
};

static struct multiplexer gpu2d_core_mux = {
	.clk = &gpu2d_core_clk,
	.reg = CBCMR,
	.bp = BP_CBCMR_GPU2D_CORE_SEL,
	.bm = BM_CBCMR_GPU2D_CORE_SEL,
	.parents = {
		&axi_clk,
		&pll3_usb_otg,
		&pll2_pfd_352m,
		&pll2_pfd_400m,
		NULL
	},
};

#define DEF_SSI_MUX(id)							\
	static struct multiplexer ssi##id##_mux = {			\
		.clk = &ssi##id##_clk,					\
		.reg = CSCMR1,						\
		.bp = BP_CSCMR1_SSI##id##_SEL,				\
		.bm = BM_CSCMR1_SSI##id##_SEL,				\
		.parents = {						\
			&pll3_pfd_508m,					\
			&pll3_pfd_454m,					\
			&pll4_audio,					\
			NULL						\
		},							\
	}

DEF_SSI_MUX(1);
DEF_SSI_MUX(2);
DEF_SSI_MUX(3);

#define DEF_USDHC_MUX(id)						\
	static struct multiplexer usdhc##id##_mux = {			\
		.clk = &usdhc##id##_clk,				\
		.reg = CSCMR1,						\
		.bp = BP_CSCMR1_USDHC##id##_SEL,			\
		.bm = BM_CSCMR1_USDHC##id##_SEL,			\
		.parents = {						\
			&pll2_pfd_400m,					\
			&pll2_pfd_352m,					\
			NULL						\
		},							\
	}

DEF_USDHC_MUX(1);
DEF_USDHC_MUX(2);
DEF_USDHC_MUX(3);
DEF_USDHC_MUX(4);

static struct multiplexer emi_mux = {
	.clk = &emi_clk,
	.reg = CSCMR1,
	.bp = BP_CSCMR1_EMI_SEL,
	.bm = BM_CSCMR1_EMI_SEL,
	.parents = {
		&axi_clk,
		&pll3_usb_otg,
		&pll2_pfd_400m,
		&pll2_pfd_352m,
		NULL
	},
};

static struct multiplexer emi_slow_mux = {
	.clk = &emi_slow_clk,
	.reg = CSCMR1,
	.bp = BP_CSCMR1_EMI_SLOW_SEL,
	.bm = BM_CSCMR1_EMI_SLOW_SEL,
	.parents = {
		&axi_clk,
		&pll3_usb_otg,
		&pll2_pfd_400m,
		&pll2_pfd_352m,
		NULL
	},
};

static struct multiplexer esai_mux = {
	.clk = &esai_clk,
	.reg = CSCMR2,
	.bp = BP_CSCMR2_ESAI_SEL,
	.bm = BM_CSCMR2_ESAI_SEL,
	.parents = {
		&pll4_audio,
		&pll3_pfd_508m,
		&pll3_pfd_454m,
		&pll3_usb_otg,
		NULL
	},
};

#define DEF_LDB_DI_MUX(id)						\
	static struct multiplexer ldb_di##id##_mux = {			\
		.clk = &ldb_di##id##_clk,				\
		.reg = CS2CDR,						\
		.bp = BP_CS2CDR_LDB_DI##id##_SEL,			\
		.bm = BM_CS2CDR_LDB_DI##id##_SEL,			\
		.parents = {						\
			&pll5_video,					\
			&pll2_pfd_352m,					\
			&pll2_pfd_400m,					\
			&pll3_pfd_540m,					\
			&pll3_usb_otg,					\
			NULL						\
		},							\
	}

DEF_LDB_DI_MUX(0);
DEF_LDB_DI_MUX(1);

static struct multiplexer enfc_mux = {
	.clk = &enfc_clk,
	.reg = CS2CDR,
	.bp = BP_CS2CDR_ENFC_SEL,
	.bm = BM_CS2CDR_ENFC_SEL,
	.parents = {
		&pll2_pfd_352m,
		&pll2_bus,
		&pll3_usb_otg,
		&pll2_pfd_400m,
		NULL
	},
};

static struct multiplexer spdif_mux = {
	.clk = &spdif_clk,
	.reg = CDCDR,
	.bp = BP_CDCDR_SPDIF_SEL,
	.bm = BM_CDCDR_SPDIF_SEL,
	.parents = {
		&pll4_audio,
		&pll3_pfd_508m,
		&pll3_pfd_454m,
		&pll3_usb_otg,
		NULL
	},
};

static struct multiplexer asrc_serial_mux = {
	.clk = &asrc_serial_clk,
	.reg = CDCDR,
	.bp = BP_CDCDR_ASRC_SERIAL_SEL,
	.bm = BM_CDCDR_ASRC_SERIAL_SEL,
	.parents = {
		&pll4_audio,
		&pll3_pfd_508m,
		&pll3_pfd_454m,
		&pll3_usb_otg,
		NULL
	},
};

static struct multiplexer hsi_tx_mux = {
	.clk = &hsi_tx_clk,
	.reg = CDCDR,
	.bp = BP_CDCDR_HSI_TX_SEL,
	.bm = BM_CDCDR_HSI_TX_SEL,
	.parents = {
		&pll3_120m,
		&pll2_pfd_400m,
		NULL
	},
};

#define DEF_IPU_DI_PRE_MUX(r, i, d)					\
	static struct multiplexer ipu##i##_di##d##_pre_mux = {		\
		.clk = &ipu##i##_di##d##_pre_clk,			\
		.reg = r,						\
		.bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,		\
		.bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,		\
		.parents = {						\
			&mmdc_ch0_axi_clk,				\
			&pll3_usb_otg,					\
			&pll5_video,					\
			&pll2_pfd_352m,					\
			&pll2_pfd_400m,					\
			&pll3_pfd_540m,					\
			NULL						\
		},							\
	}

DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);

#define DEF_IPU_DI_MUX(r, i, d)						\
	static struct multiplexer ipu##i##_di##d##_mux = {		\
		.clk = &ipu##i##_di##d##_clk,				\
		.reg = r,						\
		.bp = BP_##r##_IPU##i##_DI##d##_SEL,			\
		.bm = BM_##r##_IPU##i##_DI##d##_SEL,			\
		.parents = {						\
			&ipu##i##_di##d##_pre_clk,			\
			&dummy_clk,					\
			&dummy_clk,					\
			&ldb_di0_clk,					\
			&ldb_di1_clk,					\
			NULL						\
		},							\
	}

DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
DEF_IPU_DI_MUX(CSCDR2, 2, 0);
DEF_IPU_DI_MUX(CSCDR2, 2, 1);

#define DEF_IPU_MUX(id)							\
	static struct multiplexer ipu##id##_mux = {			\
		.clk = &ipu##id##_clk,					\
		.reg = CSCDR3,						\
		.bp = BP_CSCDR3_IPU##id##_HSP_SEL,			\
		.bm = BM_CSCDR3_IPU##id##_HSP_SEL,			\
		.parents = {						\
			&mmdc_ch0_axi_clk,				\
			&pll2_pfd_400m,					\
			&pll3_120m,					\
			&pll3_pfd_540m,					\
			NULL						\
		},							\
	}

DEF_IPU_MUX(1);
DEF_IPU_MUX(2);

static struct multiplexer *multiplexers[] = {
	&axi_mux,
	&periph_mux,
	&periph_pre_mux,
	&periph_clk2_mux,
	&periph2_mux,
	&periph2_pre_mux,
	&periph2_clk2_mux,
	&gpu2d_axi_mux,
	&gpu3d_axi_mux,
	&gpu3d_core_mux,
	&gpu3d_shader_mux,
	&pcie_axi_mux,
	&vdo_axi_mux,
	&vpu_axi_mux,
	&gpu2d_core_mux,
	&ssi1_mux,
	&ssi2_mux,
	&ssi3_mux,
	&usdhc1_mux,
	&usdhc2_mux,
	&usdhc3_mux,
	&usdhc4_mux,
	&emi_mux,
	&emi_slow_mux,
	&esai_mux,
	&ldb_di0_mux,
	&ldb_di1_mux,
	&enfc_mux,
	&spdif_mux,
	&asrc_serial_mux,
	&hsi_tx_mux,
	&ipu1_di0_pre_mux,
	&ipu1_di0_mux,
	&ipu1_di1_pre_mux,
	&ipu1_di1_mux,
	&ipu2_di0_pre_mux,
	&ipu2_di0_mux,
	&ipu2_di1_pre_mux,
	&ipu2_di1_mux,
	&ipu1_mux,
	&ipu2_mux,
};

static int _clk_set_parent(struct clk *clk, struct clk *parent)
{
	struct multiplexer *m;
	int i, num;
	u32 val;

	num = ARRAY_SIZE(multiplexers);
	for (i = 0; i < num; i++)
		if (multiplexers[i]->clk == clk) {
			m = multiplexers[i];
			break;
		}
	if (i == num)
		return -EINVAL;

	i = 0;
	while (m->parents[i]) {
		if (parent == m->parents[i])
			break;
		i++;
	}
	if (!m->parents[i])
		return -EINVAL;

	val = readl_relaxed(m->reg);
	val &= ~m->bm;
	val |= i << m->bp;
	writel_relaxed(val, m->reg);

	if (clk == &periph_clk)
		return clk_busy_wait(clk);

	return 0;
}

#define DEF_NG_CLK(name, p)				\
	static struct clk name = {			\
		.get_rate	= _clk_get_rate,	\
		.set_rate	= _clk_set_rate,	\
		.round_rate	= _clk_round_rate,	\
		.set_parent	= _clk_set_parent,	\
		.parent		= p,			\
	}

DEF_NG_CLK(periph_clk2_clk,	&osc_clk);
DEF_NG_CLK(periph_pre_clk,	&pll2_bus);
DEF_NG_CLK(periph_clk,		&periph_pre_clk);
DEF_NG_CLK(periph2_clk2_clk,	&osc_clk);
DEF_NG_CLK(periph2_pre_clk,	&pll2_bus);
DEF_NG_CLK(periph2_clk,		&periph2_pre_clk);
DEF_NG_CLK(axi_clk,		&periph_clk);
DEF_NG_CLK(emi_clk,		&axi_clk);
DEF_NG_CLK(arm_clk,		&pll1_sw_clk);
DEF_NG_CLK(ahb_clk,		&periph_clk);
DEF_NG_CLK(ipg_clk,		&ahb_clk);
DEF_NG_CLK(ipg_perclk,		&ipg_clk);
DEF_NG_CLK(ipu1_di0_pre_clk,	&pll3_pfd_540m);
DEF_NG_CLK(ipu1_di1_pre_clk,	&pll3_pfd_540m);
DEF_NG_CLK(ipu2_di0_pre_clk,	&pll3_pfd_540m);
DEF_NG_CLK(ipu2_di1_pre_clk,	&pll3_pfd_540m);
DEF_NG_CLK(asrc_serial_clk,	&pll3_usb_otg);

#define DEF_CLK(name, er, es, p, s)			\
	static struct clk name = {			\
		.enable_reg	= er,			\
		.enable_shift	= es,			\
		.enable		= _clk_enable,		\
		.disable	= _clk_disable,		\
		.get_rate	= _clk_get_rate,	\
		.set_rate	= _clk_set_rate,	\
		.round_rate	= _clk_round_rate,	\
		.set_parent	= _clk_set_parent,	\
		.parent		= p,			\
		.secondary	= s,			\
	}

DEF_CLK(aips_tz1_clk,	  CCGR0, CG0,  &ahb_clk,	  NULL);
DEF_CLK(aips_tz2_clk,	  CCGR0, CG1,  &ahb_clk,	  NULL);
DEF_CLK(apbh_dma_clk,	  CCGR0, CG2,  &ahb_clk,	  NULL);
DEF_CLK(asrc_clk,	  CCGR0, CG3,  &pll4_audio,	  NULL);
DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,	  NULL);
DEF_CLK(can1_clk,	  CCGR0, CG7,  &pll3_usb_otg,	  &can1_serial_clk);
DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,	  NULL);
DEF_CLK(can2_clk,	  CCGR0, CG9,  &pll3_usb_otg,	  &can2_serial_clk);
DEF_CLK(ecspi1_clk,	  CCGR1, CG0,  &pll3_60m,	  NULL);
DEF_CLK(ecspi2_clk,	  CCGR1, CG1,  &pll3_60m,	  NULL);
DEF_CLK(ecspi3_clk,	  CCGR1, CG2,  &pll3_60m,	  NULL);
DEF_CLK(ecspi4_clk,	  CCGR1, CG3,  &pll3_60m,	  NULL);
DEF_CLK(ecspi5_clk,	  CCGR1, CG4,  &pll3_60m,	  NULL);
DEF_CLK(enet_clk,	  CCGR1, CG5,  &ipg_clk,	  NULL);
DEF_CLK(esai_clk,	  CCGR1, CG8,  &pll3_usb_otg,	  NULL);
DEF_CLK(gpt_serial_clk,	  CCGR1, CG11, &ipg_perclk,	  NULL);
DEF_CLK(gpt_clk,	  CCGR1, CG10, &ipg_perclk,	  &gpt_serial_clk);
DEF_CLK(gpu2d_core_clk,	  CCGR1, CG12, &pll2_pfd_352m,	  &gpu2d_axi_clk);
DEF_CLK(gpu3d_core_clk,	  CCGR1, CG13, &pll2_pfd_594m,	  &gpu3d_axi_clk);
DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,	  &gpu3d_axi_clk);
DEF_CLK(hdmi_iahb_clk,	  CCGR2, CG0,  &ahb_clk,	  NULL);
DEF_CLK(hdmi_isfr_clk,	  CCGR2, CG2,  &pll3_pfd_540m,	  &hdmi_iahb_clk);
DEF_CLK(i2c1_clk,	  CCGR2, CG3,  &ipg_perclk,	  NULL);
DEF_CLK(i2c2_clk,	  CCGR2, CG4,  &ipg_perclk,	  NULL);
DEF_CLK(i2c3_clk,	  CCGR2, CG5,  &ipg_perclk,	  NULL);
DEF_CLK(iim_clk,	  CCGR2, CG6,  &ipg_clk,	  NULL);
DEF_CLK(enfc_clk,	  CCGR2, CG7,  &pll2_pfd_352m,	  NULL);
DEF_CLK(ipu1_clk,	  CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
DEF_CLK(ipu1_di0_clk,	  CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
DEF_CLK(ipu1_di1_clk,	  CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
DEF_CLK(ipu2_clk,	  CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
DEF_CLK(ipu2_di0_clk,	  CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
DEF_CLK(ipu2_di1_clk,	  CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
DEF_CLK(ldb_di0_clk,	  CCGR3, CG6,  &pll3_pfd_540m,	  NULL);
DEF_CLK(ldb_di1_clk,	  CCGR3, CG7,  &pll3_pfd_540m,	  NULL);
DEF_CLK(hsi_tx_clk,	  CCGR3, CG8,  &pll2_pfd_400m,	  NULL);
DEF_CLK(mlb_clk,	  CCGR3, CG9,  &pll6_mlb,	  NULL);
DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,	  NULL);
DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,	  &mmdc_ch0_ipg_clk);
DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,	  NULL);
DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,	  &mmdc_ch1_ipg_clk);
DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,	  NULL);
DEF_CLK(pwm1_clk,	  CCGR4, CG8,  &ipg_perclk,	  NULL);
DEF_CLK(pwm2_clk,	  CCGR4, CG9,  &ipg_perclk,	  NULL);
DEF_CLK(pwm3_clk,	  CCGR4, CG10, &ipg_perclk,	  NULL);
DEF_CLK(pwm4_clk,	  CCGR4, CG11, &ipg_perclk,	  NULL);
DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,	  NULL);
DEF_CLK(gpmi_bch_clk,	  CCGR4, CG13, &usdhc4_clk,	  &gpmi_bch_apb_clk);
DEF_CLK(gpmi_apb_clk,	  CCGR4, CG15, &usdhc3_clk,	  &gpmi_bch_clk);
DEF_CLK(gpmi_io_clk,	  CCGR4, CG14, &enfc_clk,	  &gpmi_apb_clk);
DEF_CLK(sdma_clk,	  CCGR5, CG3,  &ahb_clk,	  NULL);
DEF_CLK(spba_clk,	  CCGR5, CG6,  &ipg_clk,	  NULL);
DEF_CLK(spdif_clk,	  CCGR5, CG7,  &pll3_usb_otg,	  &spba_clk);
DEF_CLK(ssi1_clk,	  CCGR5, CG9,  &pll3_pfd_508m,	  NULL);
DEF_CLK(ssi2_clk,	  CCGR5, CG10, &pll3_pfd_508m,	  NULL);
DEF_CLK(ssi3_clk,	  CCGR5, CG11, &pll3_pfd_508m,	  NULL);
DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,	  NULL);
DEF_CLK(uart_clk,	  CCGR5, CG12, &pll3_80m,	  &uart_serial_clk);
DEF_CLK(usboh3_clk,	  CCGR6, CG0,  &ipg_clk,	  NULL);
DEF_CLK(usdhc1_clk,	  CCGR6, CG1,  &pll2_pfd_400m,	  NULL);
DEF_CLK(usdhc2_clk,	  CCGR6, CG2,  &pll2_pfd_400m,	  NULL);
DEF_CLK(usdhc3_clk,	  CCGR6, CG3,  &pll2_pfd_400m,	  NULL);
DEF_CLK(usdhc4_clk,	  CCGR6, CG4,  &pll2_pfd_400m,	  NULL);
DEF_CLK(emi_slow_clk,	  CCGR6, CG5,  &axi_clk,	  NULL);
DEF_CLK(vdo_axi_clk,	  CCGR6, CG6,  &axi_clk,	  NULL);
DEF_CLK(vpu_clk,	  CCGR6, CG7,  &axi_clk,	  NULL);

static int pcie_clk_enable(struct clk *clk)
{
	u32 val;

	val = readl_relaxed(PLL8_ENET);
	val |= BM_PLL_ENET_EN_PCIE;
	writel_relaxed(val, PLL8_ENET);

	return _clk_enable(clk);
}

static void pcie_clk_disable(struct clk *clk)
{
	u32 val;

	_clk_disable(clk);

	val = readl_relaxed(PLL8_ENET);
	val &= BM_PLL_ENET_EN_PCIE;
	writel_relaxed(val, PLL8_ENET);
}

static struct clk pcie_clk = {
	.enable_reg = CCGR4,
	.enable_shift = CG0,
	.enable = pcie_clk_enable,
	.disable = pcie_clk_disable,
	.set_parent = _clk_set_parent,
	.parent = &axi_clk,
	.secondary = &pll8_enet,
};

static int sata_clk_enable(struct clk *clk)
{
	u32 val;

	val = readl_relaxed(PLL8_ENET);
	val |= BM_PLL_ENET_EN_SATA;
	writel_relaxed(val, PLL8_ENET);

	return _clk_enable(clk);
}

static void sata_clk_disable(struct clk *clk)
{
	u32 val;

	_clk_disable(clk);

	val = readl_relaxed(PLL8_ENET);
	val &= BM_PLL_ENET_EN_SATA;
	writel_relaxed(val, PLL8_ENET);
}

static struct clk sata_clk = {
	.enable_reg = CCGR5,
	.enable_shift = CG2,
	.enable = sata_clk_enable,
	.disable = sata_clk_disable,
	.parent = &ipg_clk,
	.secondary = &pll8_enet,
};

#define _REGISTER_CLOCK(d, n, c) \
	{ \
		.dev_id = d, \
		.con_id = n, \
		.clk = &c, \
	}

static struct clk_lookup lookups[] = {
	_REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
	_REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
	_REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
	_REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
	_REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
	_REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
	_REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
	_REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
	_REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
	_REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
	_REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
	_REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
	_REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
	_REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
	_REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
	_REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
	_REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
	_REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
	_REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
	_REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
	_REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
	_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
	_REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
	_REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
	_REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
	_REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
	_REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
	_REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
	_REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
	_REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
	_REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
	_REGISTER_CLOCK("2080000.pwm", NULL, pwm1_clk),
	_REGISTER_CLOCK("2084000.pwm", NULL, pwm2_clk),
	_REGISTER_CLOCK("2088000.pwm", NULL, pwm3_clk),
	_REGISTER_CLOCK("208c000.pwm", NULL, pwm4_clk),
	_REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
	_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
	_REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
	_REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
	_REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
	_REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di0_clk),
	_REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di1_clk),
	_REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di0_clk),
	_REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di1_clk),
	_REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_iahb_clk),
};

int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
	u32 val = readl_relaxed(CLPCR);

	val &= ~BM_CLPCR_LPM;
	switch (mode) {
	case WAIT_CLOCKED:
		break;
	case WAIT_UNCLOCKED:
		val |= 0x1 << BP_CLPCR_LPM;
		break;
	case STOP_POWER_ON:
		val |= 0x2 << BP_CLPCR_LPM;
		break;
	case WAIT_UNCLOCKED_POWER_OFF:
		val |= 0x1 << BP_CLPCR_LPM;
		val &= ~BM_CLPCR_VSTBY;
		val &= ~BM_CLPCR_SBYOS;
		val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		break;
	case STOP_POWER_OFF:
		val |= 0x2 << BP_CLPCR_LPM;
		val |= 0x3 << BP_CLPCR_STBY_COUNT;
		val |= BM_CLPCR_VSTBY;
		val |= BM_CLPCR_SBYOS;
		val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		break;
	default:
		return -EINVAL;
	}
	writel_relaxed(val, CLPCR);

	return 0;
}

static struct map_desc imx6q_clock_desc[] = {
	imx_map_entry(MX6Q, CCM, MT_DEVICE),
	imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
};

void __init imx6q_clock_map_io(void)
{
	iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
}

int __init mx6q_clocks_init(void)
{
	struct device_node *np;
	void __iomem *base;
	int i, irq;

	/* retrieve the freqency of fixed clocks from device tree */
	for_each_compatible_node(np, NULL, "fixed-clock") {
		u32 rate;
		if (of_property_read_u32(np, "clock-frequency", &rate))
			continue;

		if (of_device_is_compatible(np, "fsl,imx-ckil"))
			external_low_reference = rate;
		else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
			external_high_reference = rate;
		else if (of_device_is_compatible(np, "fsl,imx-osc"))
			oscillator_reference = rate;
	}

	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);

	/* only keep necessary clocks on */
	writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,	CCGR0);
	writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10,	CCGR2);
	writel_relaxed(0x3 << CG10 | 0x3 << CG12,		CCGR3);
	writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,	CCGR4);
	writel_relaxed(0x3 << CG0,				CCGR5);
	writel_relaxed(0,					CCGR6);
	writel_relaxed(0,					CCGR7);

	clk_enable(&uart_clk);
	clk_enable(&mmdc_ch0_axi_clk);

	clk_set_rate(&pll4_audio, FREQ_650M);
	clk_set_rate(&pll5_video, FREQ_650M);
	clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
	clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
	clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
	clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
	clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
	clk_set_rate(&gpu3d_core_clk, FREQ_528M);
	clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
	clk_set_rate(&asrc_serial_clk, 1500000);
	clk_set_rate(&enfc_clk, 11000000);

	/*
	 * Before pinctrl API is available, we have to rely on the pad
	 * configuration set up by bootloader.  For usdhc example here,
	 * u-boot sets up the pads for 49.5 MHz case, and we have to lower
	 * the usdhc clock from 198 to 49.5 MHz to match the pad configuration.
	 *
	 * FIXME: This is should be removed after pinctrl API is available.
	 * At that time, usdhc driver can call pinctrl API to change pad
	 * configuration dynamically per different usdhc clock settings.
	 */
	clk_set_rate(&usdhc1_clk, 49500000);
	clk_set_rate(&usdhc2_clk, 49500000);
	clk_set_rate(&usdhc3_clk, 49500000);
	clk_set_rate(&usdhc4_clk, 49500000);

	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
	base = of_iomap(np, 0);
	WARN_ON(!base);
	irq = irq_of_parse_and_map(np, 0);
	mxc_timer_init(&gpt_clk, base, irq);

	return 0;
}