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2011-11-10ENGR00161487: Fix SD/USB/FEC performance issue.er3-previewRanjani Vaidyanathan
When WAIT mode is not enabled, execute cpu_do_idle() code. Currently WAIT mode requires the code to be run from IRAM with caches disabled. No L2 cache access should be done for a specified period after the system exits WAIT mode. This delay and running code from IRAM adversely affects the SDHC performance. Hardware team is looking into the extended delay that is required. Till its root caused, default should be to execute cpu_do_idle() and disable entry into WAIT mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00161484 Add HDMI audio support on MX6 Sabre-liteMahesh Mahadevan
Add support for HDMI audio on MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00161447-2 ARM2: fix section missmach warningFrank Li
fix section mismatch warning Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-11-10ENGR00159982 - [MX6Q]: Add FEC phy save power function.Fugang Duan
- Set Phy AR8031 to saving power mode while no cable connect. Signed-off-by: Fugang Duan <B38611@freescale.com>
2011-11-10ENGR00161382-2 MX6Q MIPI CSI2: initialize platform dataEven Xu
Initialize MIPI CSI2 platform data Signed-off-by: Even Xu <b21019@freescale.com>
2011-11-10ENGR00161383 [MX6Q] USB OTG: enable OTG drivermake shi
Enable OTG driver on mx6q board Signed-off-by: make shi <b15407@freescale.com>
2011-11-10ENGR00161314-1 mx6q usb-host: add hsic supportPeter Chen
MSL part Add HSIC support for Host2 and Host3, for HSIC mode, there is not usb phy needed, the usb device is always at the board - Validation hardware: iMX6Q Validation Port Card and Re-worked Rev X3 board, for hardware rework detail, contact Ken Sun (b03826) - Validation device: HSIC interface SMSC HUB(USB4640) and Host 3. Host 2 is coding finishes, but not verified due to hardware limitation. - Pin Conflict with Ethernet, order to use HSIC, the user need disable ethernet function at both u-boot and linux kernel. For u-boot: please undefine CONFIG_MXC_FEC at your board config file For kernel: please define CONFIG_USB_EHCI_ARC_HSIC, the entry is: Device Drivers---> USB support---> Support HSIC Host controller for Freescale SoC - Suspend/resume and wakeup are not supported due to IC issues, these IC issues will be fixed at TO1.1 for i.mx6, software will add these support after receiving TO1.1 chip. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-11-10ENGR00161285 [MX6Q ARM2] make spdif and i2c3 mutually exclusiveAlan Tull
Both S/PDIF in and I2C3 SDA use GPIO_16, so only one can be enabled at a time. Add early param "spdif_in" to enable S/PDIF in. Default is to enable I2C3 and leave S/PDIF in disabled. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-11-10ENGR00161256-2 mx6q arm2: add flexcan supportDong Aisheng
Add flexcan support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2011-11-10ENGR00161321 [MX6 ARM2]Disable Warm resetAnson Huang
Current warm reset is not working with MMDC_CH1 bypass bit set, now we disable warm reset to workaround it for the coming release. Then, wdog reset will be cold reset. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00161234-2: Enable ocotp clock for mx6qTerry Lv
Add clock enable code to arch. OCOTP driver missed code to enable clock in driver. Thus if ocotp clock is not enabled in clock.c, ocotp will not work. We will remove ocotp clock enable code in board file and leave this operation to driver. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-11-10ENGR00161219 [MX6Q] add backlight driver on ARM2Gary Zhang
add pwm-backlight driver on mx6q arm2 board Signed-off-by: Gary Zhang <b13634@freescale.com>
2011-11-10ENGR00161192 [MX6 Sabre-lite] Add dummy regulators for MMC and SD driversNancy Chen
Add dummy regulators for MMC and SD drivers. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00161175 [mx6q] Add dummy regulators for CS42888 CODECNancy Chen
Add dummy regulators for CS42888 CODEC. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00159981-1 MX6: Add MIPI DSI driver and support TRULY WVGA LCD panelWayne Zou
MX6 MIPI DSI: Add MIPI DSI driver and support for TRULY WVGA LCD panel Signed-off-by: Wayne Zou <b36644@freescale.com>
2011-11-10ENGR00161127 [mx6q] Add dummy regulators for MMC and SD driversNancy Chen
Add dummy regulators for MMC and SD drivers. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00160930-2 Add support for MX6 PWMMahesh Mahadevan
Add support for the PWM module under MX6. Sabre-lite uses this for controlling the LVDS backlight Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00160930-1 Add support for MX6 Sabre-liteMahesh Mahadevan
Add support for the MX6 Sabre-lite board Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00161119 Codec regulator registration updateMahesh Mahadevan
Move the codec regulator registration code to the board specific file Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00157253-1 MX6Q spi: add ecspi for MX6QRobin Gong
1.modify config 2.add board level support ecspi 3.add ecspi pad configure Signed-off-by: Robin Gong <B38343@freescale.com>
2011-11-10ENGR00161005-1 MX6Q Kernel Rename sabreauto to arm2 boardAnish Trivedi
Machine layer patch. Sabreauto is an inaccurate name for the Armadillo2 board that this code is actually meant for. So, renamed "sabreauto" board file, configs, and code to "arm2". Created a new machine id for ARM2 board. Signed-off-by: Anish Trivedi <anish@freescale.com>
2011-11-10ENGR00160797-1 [i.MX6q] Add Anatop regulator supportNancy Chen
1. Add Anatop regulator support. 2. Add some dummy regulators support for audio codec. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00160860-1 hdmi audio driverAlan Tull
Audio driver for i.Mx built-in HDMI Transmitter. * Uses HDMI Transmitter's built-in DMA. * Adds IEC958-style digital audio header info to the raw audio. * Gets pixel clock from the IPU driver and calculates clock regenerator values (cts and N). * Move ipu_id, and disp_id from the HDMI's platform data to the HDMI mfd's platform data. Saves them in the hdmi mfd. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-11-10ENGR00160940-1 [MX6Q]sdhci: add delay line setting in board dataTony Lin
driver could set delay line due to board data parameter. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-11-10ENGR00160798 [MX6]Workaround for NFSAnson Huang
Disable SCU standby mode will prevent SOC enter WAIT mode, so, by default, we would not enable WAIT mode to make NFS work, to enable WAIT mode, you should not use NFS, and pass "enable_wait_mode" from uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.Ranjani Vaidyanathan
When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power. Fixed warnings in dvfs_core driver. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00160863 Update clocking code to support all UARTsMahesh Mahadevan
The MX6 Sabre-lite board uses UART2 for console. Add clock code for this in the MX6 BSP Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00160874 Enable SSI audio support on the MX6Mahesh Mahadevan
The MX6 Sabre-lite board uses the SGTL codec through SSI to play audio. Add support for SSI audio on the MX6 Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00160709-3 Move board specific code out of FEC driverMahesh Mahadevan
Move the board specific code out of the FEC driver to the platform layer Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00160615 Clock updates to enable support clkoMahesh Mahadevan
Enable support for clko clock used for the audio codec on MX6 Sabre-lite board Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00139265-4 mxc alsa soc spdif driverAlan Tull
* Add support for S/PDIF on i.Mx6 Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-11-10ENGR00156766 [MX6Q]USB: Enable USB host1 functionmake shi
Add necessary implement to Enable USB host1 function Signed-off-by: make shi <b15407@freescale.com>
2011-11-10ENGR00160513 [MX6Q]Lower SOC power in dormantAnson Huang
Add necessary implement to lower the SOC power when dormant, on ddr3, ARM+SOC is ~3.8mA, and on LPDDR2, it is ~2.3mA. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00160296: MX6-Added secondary and dependent clocks for various peripherals.Ranjani Vaidyanathan
Add secondary and dependent clocks for efficient clock management and thereby reduce power. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00160112-3 MX6Q camera: config MCLK for csi0Yuxi
set cko1_clk0 as mclk for csi0 Signed-off-by: Yuxi Sun <b36102@freescale.com>
2011-11-10ENGR00160112-2 MX6Q camera: Add camera data and initial pin configurationYuxi
Add camera platform data and i2c bus data and initialize control pins Signed-off-by: Yuxi Sun <b36102@freescale.com>
2011-11-10ENGR00160061 - Mach-MX6: Optimize HDMI clock managementDanny Nold
- Decouple HDMI IAHB clock from HDMI ISFR clock, in order to allow IAHB clock to be disabled while keeping ISFR clock enabled. Signed-off-by: Danny Nold <dannynold@freescale.com>
2011-11-10ENGR00160291 MX6 correct cdcdr spdif0 podf definesAlan Tull
MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET/MASK were incorrect. Should be 22. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-11-10ENGR00159641: MX6-Add DVFS-CORE supportRanjani Vaidyanathan
Add DVFS-CORE support for MX6 quad/dual SOC. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00159959: MX6-Updated CPU voltages for different frequenciesRanjani Vaidyanathan
Update CPU voltages for different frequencies based on characterized values. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00159737 [Mx6]Add clock check for periph clkAnson Huang
For lpddr2 board, current freq only support up to 400MHz, in this case, periph clk will set to 400M in uboot, so in clock init, we need to check whether the ddr clock is set to 400M, if yes, then we should set periph clk parent to pll2_pfd_400M. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00155879: MX6: Enable ARM core to enter WAIT mode when system is idle.Ranjani Vaidyanathan
Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT mode when system is idle. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00156635 [MX6]Dormant random resume failAnson Huang
1. sometimes system can not resume successfully from dormant mode, there is still some defect with L2 cache array alive during dromant mode, add clean operation before dormant to make sure data alignment between L2 and DRAM, after doing it, dormant mode can resume fine. 2. local time no need to do store and restore during suspend/resume. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00156849 MX6Q: add relative clock for BCHHuang Shijie
The BCH needs the pl301_mx6qperl_bch clock. The BCH will not work if the clock is not enabled. So add it. Signed-off-by: Huang Shijie <b32955@freescale.com>
2011-11-10ENGR00156314-3 [mx6q]gic: save/restore mode for suspend/resumeTony Lin
save gic registers before suspend and restore these registers after resuming Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-11-10ENGR00156314-1 [mx6q]gic: add comments to explain start irq offset valueTony Lin
to be more clear why we start irq offset from 29. and list the irq ID table. Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-11-10ENGR00156329 [MX6]Avoid flushing L2 in dormantAnson Huang
We can leave L2 cache alone during dormant, just keep in mind don't access cache in dormant process, then it should be OK without flushing L2 cache, it will improve performance of suspend and resume. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00155147 mx5x mx6x: adjust dma zone max size to 184MJason Chen
adjust dma zone max size to 184M. keep default size as 96M. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00156232 [mx6q]change cpuinfo keywordTony Lin
MX[0-9] is the keyword for multimedia applications, so change the cpuinfo from i.MX 6Quad to MX6 Quad Signed-off-by: Tony Lin <tony.lin@freescale.com>
2011-11-10ENGR00156153: MX6- Fix bugs in clock code.Ranjani Vaidyanathan
Refer to the ipcg table in the spec to ensure that the parent clocks are set correctly. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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